1 #ifndef _ASM_POWERPC_IO_H 2 #define _ASM_POWERPC_IO_H 3 #ifdef __KERNEL__ 4 5 #define ARCH_HAS_IOREMAP_WC 6 #ifdef CONFIG_PPC32 7 #define ARCH_HAS_IOREMAP_WT 8 #endif 9 10 /* 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 /* Check of existence of legacy devices */ 18 extern int check_legacy_ioport(unsigned long base_port); 19 #define I8042_DATA_REG 0x60 20 #define FDC_BASE 0x3f0 21 22 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI) 23 extern struct pci_dev *isa_bridge_pcidev; 24 /* 25 * has legacy ISA devices ? 26 */ 27 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special) 28 #endif 29 30 #include <linux/device.h> 31 #include <linux/compiler.h> 32 #include <asm/page.h> 33 #include <asm/byteorder.h> 34 #include <asm/synch.h> 35 #include <asm/delay.h> 36 #include <asm/mmu.h> 37 #include <asm/ppc_asm.h> 38 39 #ifdef CONFIG_PPC64 40 #include <asm/paca.h> 41 #endif 42 43 #define SIO_CONFIG_RA 0x398 44 #define SIO_CONFIG_RD 0x399 45 46 #define SLOW_DOWN_IO 47 48 /* 32 bits uses slightly different variables for the various IO 49 * bases. Most of this file only uses _IO_BASE though which we 50 * define properly based on the platform 51 */ 52 #ifndef CONFIG_PCI 53 #define _IO_BASE 0 54 #define _ISA_MEM_BASE 0 55 #define PCI_DRAM_OFFSET 0 56 #elif defined(CONFIG_PPC32) 57 #define _IO_BASE isa_io_base 58 #define _ISA_MEM_BASE isa_mem_base 59 #define PCI_DRAM_OFFSET pci_dram_offset 60 #else 61 #define _IO_BASE pci_io_base 62 #define _ISA_MEM_BASE isa_mem_base 63 #define PCI_DRAM_OFFSET 0 64 #endif 65 66 extern unsigned long isa_io_base; 67 extern unsigned long pci_io_base; 68 extern unsigned long pci_dram_offset; 69 70 extern resource_size_t isa_mem_base; 71 72 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE 73 * is not set or addresses cannot be translated to MMIO. This is typically 74 * set when the platform supports "special" PIO accesses via a non memory 75 * mapped mechanism, and allows things like the early udbg UART code to 76 * function. 77 */ 78 extern bool isa_io_special; 79 80 #ifdef CONFIG_PPC32 81 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 82 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits 83 #endif 84 #endif 85 86 /* 87 * 88 * Low level MMIO accessors 89 * 90 * This provides the non-bus specific accessors to MMIO. Those are PowerPC 91 * specific and thus shouldn't be used in generic code. The accessors 92 * provided here are: 93 * 94 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 95 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 96 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns 97 * 98 * Those operate directly on a kernel virtual address. Note that the prototype 99 * for the out_* accessors has the arguments in opposite order from the usual 100 * linux PCI accessors. Unlike those, they take the address first and the value 101 * next. 102 * 103 * Note: I might drop the _ns suffix on the stream operations soon as it is 104 * simply normal for stream operations to not swap in the first place. 105 * 106 */ 107 108 #ifdef CONFIG_PPC64 109 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0) 110 #else 111 #define IO_SET_SYNC_FLAG() 112 #endif 113 114 #define DEF_MMIO_IN_X(name, size, insn) \ 115 static inline u##size name(const volatile u##size __iomem *addr) \ 116 { \ 117 u##size ret; \ 118 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ 119 : "=r" (ret) : "Z" (*addr) : "memory"); \ 120 return ret; \ 121 } 122 123 #define DEF_MMIO_OUT_X(name, size, insn) \ 124 static inline void name(volatile u##size __iomem *addr, u##size val) \ 125 { \ 126 __asm__ __volatile__("sync;"#insn" %1,%y0" \ 127 : "=Z" (*addr) : "r" (val) : "memory"); \ 128 IO_SET_SYNC_FLAG(); \ 129 } 130 131 #define DEF_MMIO_IN_D(name, size, insn) \ 132 static inline u##size name(const volatile u##size __iomem *addr) \ 133 { \ 134 u##size ret; \ 135 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ 136 : "=r" (ret) : "m" (*addr) : "memory"); \ 137 return ret; \ 138 } 139 140 #define DEF_MMIO_OUT_D(name, size, insn) \ 141 static inline void name(volatile u##size __iomem *addr, u##size val) \ 142 { \ 143 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ 144 : "=m" (*addr) : "r" (val) : "memory"); \ 145 IO_SET_SYNC_FLAG(); \ 146 } 147 148 DEF_MMIO_IN_D(in_8, 8, lbz); 149 DEF_MMIO_OUT_D(out_8, 8, stb); 150 151 #ifdef __BIG_ENDIAN__ 152 DEF_MMIO_IN_D(in_be16, 16, lhz); 153 DEF_MMIO_IN_D(in_be32, 32, lwz); 154 DEF_MMIO_IN_X(in_le16, 16, lhbrx); 155 DEF_MMIO_IN_X(in_le32, 32, lwbrx); 156 157 DEF_MMIO_OUT_D(out_be16, 16, sth); 158 DEF_MMIO_OUT_D(out_be32, 32, stw); 159 DEF_MMIO_OUT_X(out_le16, 16, sthbrx); 160 DEF_MMIO_OUT_X(out_le32, 32, stwbrx); 161 #else 162 DEF_MMIO_IN_X(in_be16, 16, lhbrx); 163 DEF_MMIO_IN_X(in_be32, 32, lwbrx); 164 DEF_MMIO_IN_D(in_le16, 16, lhz); 165 DEF_MMIO_IN_D(in_le32, 32, lwz); 166 167 DEF_MMIO_OUT_X(out_be16, 16, sthbrx); 168 DEF_MMIO_OUT_X(out_be32, 32, stwbrx); 169 DEF_MMIO_OUT_D(out_le16, 16, sth); 170 DEF_MMIO_OUT_D(out_le32, 32, stw); 171 172 #endif /* __BIG_ENDIAN */ 173 174 #ifdef __powerpc64__ 175 176 #ifdef __BIG_ENDIAN__ 177 DEF_MMIO_OUT_D(out_be64, 64, std); 178 DEF_MMIO_IN_D(in_be64, 64, ld); 179 180 /* There is no asm instructions for 64 bits reverse loads and stores */ 181 static inline u64 in_le64(const volatile u64 __iomem *addr) 182 { 183 return swab64(in_be64(addr)); 184 } 185 186 static inline void out_le64(volatile u64 __iomem *addr, u64 val) 187 { 188 out_be64(addr, swab64(val)); 189 } 190 #else 191 DEF_MMIO_OUT_D(out_le64, 64, std); 192 DEF_MMIO_IN_D(in_le64, 64, ld); 193 194 /* There is no asm instructions for 64 bits reverse loads and stores */ 195 static inline u64 in_be64(const volatile u64 __iomem *addr) 196 { 197 return swab64(in_le64(addr)); 198 } 199 200 static inline void out_be64(volatile u64 __iomem *addr, u64 val) 201 { 202 out_le64(addr, swab64(val)); 203 } 204 205 #endif 206 #endif /* __powerpc64__ */ 207 208 /* 209 * Low level IO stream instructions are defined out of line for now 210 */ 211 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); 212 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); 213 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); 214 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); 215 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); 216 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); 217 218 /* The _ns naming is historical and will be removed. For now, just #define 219 * the non _ns equivalent names 220 */ 221 #define _insw _insw_ns 222 #define _insl _insl_ns 223 #define _outsw _outsw_ns 224 #define _outsl _outsl_ns 225 226 227 /* 228 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line 229 */ 230 231 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); 232 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, 233 unsigned long n); 234 extern void _memcpy_toio(volatile void __iomem *dest, const void *src, 235 unsigned long n); 236 237 /* 238 * 239 * PCI and standard ISA accessors 240 * 241 * Those are globally defined linux accessors for devices on PCI or ISA 242 * busses. They follow the Linux defined semantics. The current implementation 243 * for PowerPC is as close as possible to the x86 version of these, and thus 244 * provides fairly heavy weight barriers for the non-raw versions 245 * 246 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO 247 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its 248 * own implementation of some or all of the accessors. 249 */ 250 251 /* 252 * Include the EEH definitions when EEH is enabled only so they don't get 253 * in the way when building for 32 bits 254 */ 255 #ifdef CONFIG_EEH 256 #include <asm/eeh.h> 257 #endif 258 259 /* Shortcut to the MMIO argument pointer */ 260 #define PCI_IO_ADDR volatile void __iomem * 261 262 /* Indirect IO address tokens: 263 * 264 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks 265 * on all MMIOs. (Note that this is all 64 bits only for now) 266 * 267 * To help platforms who may need to differentiate MMIO addresses in 268 * their hooks, a bitfield is reserved for use by the platform near the 269 * top of MMIO addresses (not PIO, those have to cope the hard way). 270 * 271 * This bit field is 12 bits and is at the top of the IO virtual 272 * addresses PCI_IO_INDIRECT_TOKEN_MASK. 273 * 274 * The kernel virtual space is thus: 275 * 276 * 0xD000000000000000 : vmalloc 277 * 0xD000080000000000 : PCI PHB IO space 278 * 0xD000080080000000 : ioremap 279 * 0xD0000fffffffffff : end of ioremap region 280 * 281 * Since the top 4 bits are reserved as the region ID, we use thus 282 * the next 12 bits and keep 4 bits available for the future if the 283 * virtual address space is ever to be extended. 284 * 285 * The direct IO mapping operations will then mask off those bits 286 * before doing the actual access, though that only happen when 287 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that 288 * mechanism 289 * 290 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes 291 * all PIO functions call through a hook. 292 */ 293 294 #ifdef CONFIG_PPC_INDIRECT_MMIO 295 #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul 296 #define PCI_IO_IND_TOKEN_SHIFT 48 297 #define PCI_FIX_ADDR(addr) \ 298 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) 299 #define PCI_GET_ADDR_TOKEN(addr) \ 300 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ 301 PCI_IO_IND_TOKEN_SHIFT) 302 #define PCI_SET_ADDR_TOKEN(addr, token) \ 303 do { \ 304 unsigned long __a = (unsigned long)(addr); \ 305 __a &= ~PCI_IO_IND_TOKEN_MASK; \ 306 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ 307 (addr) = (void __iomem *)__a; \ 308 } while(0) 309 #else 310 #define PCI_FIX_ADDR(addr) (addr) 311 #endif 312 313 314 /* 315 * Non ordered and non-swapping "raw" accessors 316 */ 317 318 static inline unsigned char __raw_readb(const volatile void __iomem *addr) 319 { 320 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); 321 } 322 static inline unsigned short __raw_readw(const volatile void __iomem *addr) 323 { 324 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); 325 } 326 static inline unsigned int __raw_readl(const volatile void __iomem *addr) 327 { 328 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); 329 } 330 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 331 { 332 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; 333 } 334 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 335 { 336 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; 337 } 338 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 339 { 340 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; 341 } 342 343 #ifdef __powerpc64__ 344 static inline unsigned long __raw_readq(const volatile void __iomem *addr) 345 { 346 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); 347 } 348 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 349 { 350 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; 351 } 352 353 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr) 354 { 355 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr); 356 } 357 358 /* 359 * Real mode versions of the above. Those instructions are only supposed 360 * to be used in hypervisor real mode as per the architecture spec. 361 */ 362 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr) 363 { 364 __asm__ __volatile__("stbcix %0,0,%1" 365 : : "r" (val), "r" (paddr) : "memory"); 366 } 367 368 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr) 369 { 370 __asm__ __volatile__("sthcix %0,0,%1" 371 : : "r" (val), "r" (paddr) : "memory"); 372 } 373 374 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr) 375 { 376 __asm__ __volatile__("stwcix %0,0,%1" 377 : : "r" (val), "r" (paddr) : "memory"); 378 } 379 380 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 381 { 382 __asm__ __volatile__("stdcix %0,0,%1" 383 : : "r" (val), "r" (paddr) : "memory"); 384 } 385 386 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr) 387 { 388 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr); 389 } 390 391 static inline u8 __raw_rm_readb(volatile void __iomem *paddr) 392 { 393 u8 ret; 394 __asm__ __volatile__("lbzcix %0,0, %1" 395 : "=r" (ret) : "r" (paddr) : "memory"); 396 return ret; 397 } 398 399 static inline u16 __raw_rm_readw(volatile void __iomem *paddr) 400 { 401 u16 ret; 402 __asm__ __volatile__("lhzcix %0,0, %1" 403 : "=r" (ret) : "r" (paddr) : "memory"); 404 return ret; 405 } 406 407 static inline u32 __raw_rm_readl(volatile void __iomem *paddr) 408 { 409 u32 ret; 410 __asm__ __volatile__("lwzcix %0,0, %1" 411 : "=r" (ret) : "r" (paddr) : "memory"); 412 return ret; 413 } 414 415 static inline u64 __raw_rm_readq(volatile void __iomem *paddr) 416 { 417 u64 ret; 418 __asm__ __volatile__("ldcix %0,0, %1" 419 : "=r" (ret) : "r" (paddr) : "memory"); 420 return ret; 421 } 422 #endif /* __powerpc64__ */ 423 424 /* 425 * 426 * PCI PIO and MMIO accessors. 427 * 428 * 429 * On 32 bits, PIO operations have a recovery mechanism in case they trigger 430 * machine checks (which they occasionally do when probing non existing 431 * IO ports on some platforms, like PowerMac and 8xx). 432 * I always found it to be of dubious reliability and I am tempted to get 433 * rid of it one of these days. So if you think it's important to keep it, 434 * please voice up asap. We never had it for 64 bits and I do not intend 435 * to port it over 436 */ 437 438 #ifdef CONFIG_PPC32 439 440 #define __do_in_asm(name, op) \ 441 static inline unsigned int name(unsigned int port) \ 442 { \ 443 unsigned int x; \ 444 __asm__ __volatile__( \ 445 "sync\n" \ 446 "0:" op " %0,0,%1\n" \ 447 "1: twi 0,%0,0\n" \ 448 "2: isync\n" \ 449 "3: nop\n" \ 450 "4:\n" \ 451 ".section .fixup,\"ax\"\n" \ 452 "5: li %0,-1\n" \ 453 " b 4b\n" \ 454 ".previous\n" \ 455 EX_TABLE(0b, 5b) \ 456 EX_TABLE(1b, 5b) \ 457 EX_TABLE(2b, 5b) \ 458 EX_TABLE(3b, 5b) \ 459 : "=&r" (x) \ 460 : "r" (port + _IO_BASE) \ 461 : "memory"); \ 462 return x; \ 463 } 464 465 #define __do_out_asm(name, op) \ 466 static inline void name(unsigned int val, unsigned int port) \ 467 { \ 468 __asm__ __volatile__( \ 469 "sync\n" \ 470 "0:" op " %0,0,%1\n" \ 471 "1: sync\n" \ 472 "2:\n" \ 473 EX_TABLE(0b, 2b) \ 474 EX_TABLE(1b, 2b) \ 475 : : "r" (val), "r" (port + _IO_BASE) \ 476 : "memory"); \ 477 } 478 479 __do_in_asm(_rec_inb, "lbzx") 480 __do_in_asm(_rec_inw, "lhbrx") 481 __do_in_asm(_rec_inl, "lwbrx") 482 __do_out_asm(_rec_outb, "stbx") 483 __do_out_asm(_rec_outw, "sthbrx") 484 __do_out_asm(_rec_outl, "stwbrx") 485 486 #endif /* CONFIG_PPC32 */ 487 488 /* The "__do_*" operations below provide the actual "base" implementation 489 * for each of the defined accessors. Some of them use the out_* functions 490 * directly, some of them still use EEH, though we might change that in the 491 * future. Those macros below provide the necessary argument swapping and 492 * handling of the IO base for PIO. 493 * 494 * They are themselves used by the macros that define the actual accessors 495 * and can be used by the hooks if any. 496 * 497 * Note that PIO operations are always defined in terms of their corresonding 498 * MMIO operations. That allows platforms like iSeries who want to modify the 499 * behaviour of both to only hook on the MMIO version and get both. It's also 500 * possible to hook directly at the toplevel PIO operation if they have to 501 * be handled differently 502 */ 503 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) 504 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) 505 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) 506 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) 507 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) 508 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) 509 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) 510 511 #ifdef CONFIG_EEH 512 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) 513 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) 514 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) 515 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) 516 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) 517 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) 518 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) 519 #else /* CONFIG_EEH */ 520 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) 521 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) 522 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) 523 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) 524 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) 525 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) 526 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) 527 #endif /* !defined(CONFIG_EEH) */ 528 529 #ifdef CONFIG_PPC32 530 #define __do_outb(val, port) _rec_outb(val, port) 531 #define __do_outw(val, port) _rec_outw(val, port) 532 #define __do_outl(val, port) _rec_outl(val, port) 533 #define __do_inb(port) _rec_inb(port) 534 #define __do_inw(port) _rec_inw(port) 535 #define __do_inl(port) _rec_inl(port) 536 #else /* CONFIG_PPC32 */ 537 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); 538 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); 539 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); 540 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); 541 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); 542 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); 543 #endif /* !CONFIG_PPC32 */ 544 545 #ifdef CONFIG_EEH 546 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) 547 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) 548 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) 549 #else /* CONFIG_EEH */ 550 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) 551 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) 552 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) 553 #endif /* !CONFIG_EEH */ 554 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) 555 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) 556 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) 557 558 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 559 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 560 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 561 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 562 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 563 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 564 565 #define __do_memset_io(addr, c, n) \ 566 _memset_io(PCI_FIX_ADDR(addr), c, n) 567 #define __do_memcpy_toio(dst, src, n) \ 568 _memcpy_toio(PCI_FIX_ADDR(dst), src, n) 569 570 #ifdef CONFIG_EEH 571 #define __do_memcpy_fromio(dst, src, n) \ 572 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) 573 #else /* CONFIG_EEH */ 574 #define __do_memcpy_fromio(dst, src, n) \ 575 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) 576 #endif /* !CONFIG_EEH */ 577 578 #ifdef CONFIG_PPC_INDIRECT_PIO 579 #define DEF_PCI_HOOK_pio(x) x 580 #else 581 #define DEF_PCI_HOOK_pio(x) NULL 582 #endif 583 584 #ifdef CONFIG_PPC_INDIRECT_MMIO 585 #define DEF_PCI_HOOK_mem(x) x 586 #else 587 #define DEF_PCI_HOOK_mem(x) NULL 588 #endif 589 590 /* Structure containing all the hooks */ 591 extern struct ppc_pci_io { 592 593 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at; 594 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at; 595 596 #include <asm/io-defs.h> 597 598 #undef DEF_PCI_AC_RET 599 #undef DEF_PCI_AC_NORET 600 601 } ppc_pci_io; 602 603 /* The inline wrappers */ 604 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ 605 static inline ret name at \ 606 { \ 607 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 608 return ppc_pci_io.name al; \ 609 return __do_##name al; \ 610 } 611 612 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \ 613 static inline void name at \ 614 { \ 615 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 616 ppc_pci_io.name al; \ 617 else \ 618 __do_##name al; \ 619 } 620 621 #include <asm/io-defs.h> 622 623 #undef DEF_PCI_AC_RET 624 #undef DEF_PCI_AC_NORET 625 626 /* Some drivers check for the presence of readq & writeq with 627 * a #ifdef, so we make them happy here. 628 */ 629 #ifdef __powerpc64__ 630 #define readq readq 631 #define writeq writeq 632 #endif 633 634 /* 635 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 636 * access 637 */ 638 #define xlate_dev_mem_ptr(p) __va(p) 639 640 /* 641 * Convert a virtual cached pointer to an uncached pointer 642 */ 643 #define xlate_dev_kmem_ptr(p) p 644 645 /* 646 * We don't do relaxed operations yet, at least not with this semantic 647 */ 648 #define readb_relaxed(addr) readb(addr) 649 #define readw_relaxed(addr) readw(addr) 650 #define readl_relaxed(addr) readl(addr) 651 #define readq_relaxed(addr) readq(addr) 652 #define writeb_relaxed(v, addr) writeb(v, addr) 653 #define writew_relaxed(v, addr) writew(v, addr) 654 #define writel_relaxed(v, addr) writel(v, addr) 655 #define writeq_relaxed(v, addr) writeq(v, addr) 656 657 #include <asm-generic/iomap.h> 658 659 #ifdef CONFIG_PPC32 660 #define mmiowb() 661 #else 662 /* 663 * Enforce synchronisation of stores vs. spin_unlock 664 * (this does it explicitly, though our implementation of spin_unlock 665 * does it implicitely too) 666 */ 667 static inline void mmiowb(void) 668 { 669 unsigned long tmp; 670 671 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)" 672 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) 673 : "memory"); 674 } 675 #endif /* !CONFIG_PPC32 */ 676 677 static inline void iosync(void) 678 { 679 __asm__ __volatile__ ("sync" : : : "memory"); 680 } 681 682 /* Enforce in-order execution of data I/O. 683 * No distinction between read/write on PPC; use eieio for all three. 684 * Those are fairly week though. They don't provide a barrier between 685 * MMIO and cacheable storage nor do they provide a barrier vs. locks, 686 * they only provide barriers between 2 __raw MMIO operations and 687 * possibly break write combining. 688 */ 689 #define iobarrier_rw() eieio() 690 #define iobarrier_r() eieio() 691 #define iobarrier_w() eieio() 692 693 694 /* 695 * output pause versions need a delay at least for the 696 * w83c105 ide controller in a p610. 697 */ 698 #define inb_p(port) inb(port) 699 #define outb_p(val, port) (udelay(1), outb((val), (port))) 700 #define inw_p(port) inw(port) 701 #define outw_p(val, port) (udelay(1), outw((val), (port))) 702 #define inl_p(port) inl(port) 703 #define outl_p(val, port) (udelay(1), outl((val), (port))) 704 705 706 #define IO_SPACE_LIMIT ~(0UL) 707 708 709 /** 710 * ioremap - map bus memory into CPU space 711 * @address: bus address of the memory 712 * @size: size of the resource to map 713 * 714 * ioremap performs a platform specific sequence of operations to 715 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 716 * writew/writel functions and the other mmio helpers. The returned 717 * address is not guaranteed to be usable directly as a virtual 718 * address. 719 * 720 * We provide a few variations of it: 721 * 722 * * ioremap is the standard one and provides non-cacheable guarded mappings 723 * and can be hooked by the platform via ppc_md 724 * 725 * * ioremap_prot allows to specify the page flags as an argument and can 726 * also be hooked by the platform via ppc_md. 727 * 728 * * ioremap_nocache is identical to ioremap 729 * 730 * * ioremap_wc enables write combining 731 * 732 * * ioremap_wt enables write through 733 * 734 * * ioremap_coherent maps coherent cached memory 735 * 736 * * iounmap undoes such a mapping and can be hooked 737 * 738 * * __ioremap_at (and the pending __iounmap_at) are low level functions to 739 * create hand-made mappings for use only by the PCI code and cannot 740 * currently be hooked. Must be page aligned. 741 * 742 * * __ioremap is the low level implementation used by ioremap and 743 * ioremap_prot and cannot be hooked (but can be used by a hook on one 744 * of the previous ones) 745 * 746 * * __ioremap_caller is the same as above but takes an explicit caller 747 * reference rather than using __builtin_return_address(0) 748 * 749 * * __iounmap, is the low level implementation used by iounmap and cannot 750 * be hooked (but can be used by a hook on iounmap) 751 * 752 */ 753 extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 754 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size, 755 unsigned long flags); 756 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size); 757 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size); 758 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size); 759 #define ioremap_nocache(addr, size) ioremap((addr), (size)) 760 #define ioremap_uc(addr, size) ioremap((addr), (size)) 761 #define ioremap_cache(addr, size) \ 762 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL)) 763 764 extern void iounmap(volatile void __iomem *addr); 765 766 extern void __iomem *__ioremap(phys_addr_t, unsigned long size, 767 unsigned long flags); 768 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size, 769 pgprot_t prot, void *caller); 770 771 extern void __iounmap(volatile void __iomem *addr); 772 773 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea, 774 unsigned long size, pgprot_t prot); 775 extern void __iounmap_at(void *ea, unsigned long size); 776 777 /* 778 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation 779 * which needs some additional definitions here. They basically allow PIO 780 * space overall to be 1GB. This will work as long as we never try to use 781 * iomap to map MMIO below 1GB which should be fine on ppc64 782 */ 783 #define HAVE_ARCH_PIO_SIZE 1 784 #define PIO_OFFSET 0x00000000UL 785 #define PIO_MASK (FULL_IO_SIZE - 1) 786 #define PIO_RESERVED (FULL_IO_SIZE) 787 788 #define mmio_read16be(addr) readw_be(addr) 789 #define mmio_read32be(addr) readl_be(addr) 790 #define mmio_write16be(val, addr) writew_be(val, addr) 791 #define mmio_write32be(val, addr) writel_be(val, addr) 792 #define mmio_insb(addr, dst, count) readsb(addr, dst, count) 793 #define mmio_insw(addr, dst, count) readsw(addr, dst, count) 794 #define mmio_insl(addr, dst, count) readsl(addr, dst, count) 795 #define mmio_outsb(addr, src, count) writesb(addr, src, count) 796 #define mmio_outsw(addr, src, count) writesw(addr, src, count) 797 #define mmio_outsl(addr, src, count) writesl(addr, src, count) 798 799 /** 800 * virt_to_phys - map virtual addresses to physical 801 * @address: address to remap 802 * 803 * The returned physical address is the physical (CPU) mapping for 804 * the memory address given. It is only valid to use this function on 805 * addresses directly mapped or allocated via kmalloc. 806 * 807 * This function does not give bus mappings for DMA transfers. In 808 * almost all conceivable cases a device driver should not be using 809 * this function 810 */ 811 static inline unsigned long virt_to_phys(volatile void * address) 812 { 813 return __pa((unsigned long)address); 814 } 815 816 /** 817 * phys_to_virt - map physical address to virtual 818 * @address: address to remap 819 * 820 * The returned virtual address is a current CPU mapping for 821 * the memory address given. It is only valid to use this function on 822 * addresses that have a kernel mapping 823 * 824 * This function does not handle bus mappings for DMA transfers. In 825 * almost all conceivable cases a device driver should not be using 826 * this function 827 */ 828 static inline void * phys_to_virt(unsigned long address) 829 { 830 return (void *)__va(address); 831 } 832 833 /* 834 * Change "struct page" to physical address. 835 */ 836 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT) 837 838 /* 839 * 32 bits still uses virt_to_bus() for it's implementation of DMA 840 * mappings se we have to keep it defined here. We also have some old 841 * drivers (shame shame shame) that use bus_to_virt() and haven't been 842 * fixed yet so I need to define it here. 843 */ 844 #ifdef CONFIG_PPC32 845 846 static inline unsigned long virt_to_bus(volatile void * address) 847 { 848 if (address == NULL) 849 return 0; 850 return __pa(address) + PCI_DRAM_OFFSET; 851 } 852 853 static inline void * bus_to_virt(unsigned long address) 854 { 855 if (address == 0) 856 return NULL; 857 return __va(address - PCI_DRAM_OFFSET); 858 } 859 860 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) 861 862 #endif /* CONFIG_PPC32 */ 863 864 /* access ports */ 865 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) 866 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) 867 868 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) 869 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) 870 871 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) 872 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) 873 874 /* Clear and set bits in one shot. These macros can be used to clear and 875 * set multiple bits in a register using a single read-modify-write. These 876 * macros can also be used to set a multiple-bit bit pattern using a mask, 877 * by specifying the mask in the 'clear' parameter and the new bit pattern 878 * in the 'set' parameter. 879 */ 880 881 #define clrsetbits(type, addr, clear, set) \ 882 out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) 883 884 #ifdef __powerpc64__ 885 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) 886 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) 887 #endif 888 889 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) 890 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) 891 892 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) 893 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) 894 895 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) 896 897 #endif /* __KERNEL__ */ 898 899 #endif /* _ASM_POWERPC_IO_H */ 900