1 #ifndef _ASM_POWERPC_IO_H 2 #define _ASM_POWERPC_IO_H 3 #ifdef __KERNEL__ 4 5 #define ARCH_HAS_IOREMAP_WC 6 7 /* 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 /* Check of existence of legacy devices */ 15 extern int check_legacy_ioport(unsigned long base_port); 16 #define I8042_DATA_REG 0x60 17 #define FDC_BASE 0x3f0 18 19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI) 20 extern struct pci_dev *isa_bridge_pcidev; 21 /* 22 * has legacy ISA devices ? 23 */ 24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL) 25 #endif 26 27 #include <linux/device.h> 28 #include <linux/io.h> 29 30 #include <linux/compiler.h> 31 #include <asm/page.h> 32 #include <asm/byteorder.h> 33 #include <asm/synch.h> 34 #include <asm/delay.h> 35 #include <asm/mmu.h> 36 37 #include <asm-generic/iomap.h> 38 39 #ifdef CONFIG_PPC64 40 #include <asm/paca.h> 41 #endif 42 43 #define SIO_CONFIG_RA 0x398 44 #define SIO_CONFIG_RD 0x399 45 46 #define SLOW_DOWN_IO 47 48 /* 32 bits uses slightly different variables for the various IO 49 * bases. Most of this file only uses _IO_BASE though which we 50 * define properly based on the platform 51 */ 52 #ifndef CONFIG_PCI 53 #define _IO_BASE 0 54 #define _ISA_MEM_BASE 0 55 #define PCI_DRAM_OFFSET 0 56 #elif defined(CONFIG_PPC32) 57 #define _IO_BASE isa_io_base 58 #define _ISA_MEM_BASE isa_mem_base 59 #define PCI_DRAM_OFFSET pci_dram_offset 60 #else 61 #define _IO_BASE pci_io_base 62 #define _ISA_MEM_BASE isa_mem_base 63 #define PCI_DRAM_OFFSET 0 64 #endif 65 66 extern unsigned long isa_io_base; 67 extern unsigned long pci_io_base; 68 extern unsigned long pci_dram_offset; 69 70 extern resource_size_t isa_mem_base; 71 72 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE 73 * is not set or addresses cannot be translated to MMIO. This is typically 74 * set when the platform supports "special" PIO accesses via a non memory 75 * mapped mechanism, and allows things like the early udbg UART code to 76 * function. 77 */ 78 extern bool isa_io_special; 79 80 #ifdef CONFIG_PPC32 81 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 82 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits 83 #endif 84 #endif 85 86 /* 87 * 88 * Low level MMIO accessors 89 * 90 * This provides the non-bus specific accessors to MMIO. Those are PowerPC 91 * specific and thus shouldn't be used in generic code. The accessors 92 * provided here are: 93 * 94 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 95 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 96 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns 97 * 98 * Those operate directly on a kernel virtual address. Note that the prototype 99 * for the out_* accessors has the arguments in opposite order from the usual 100 * linux PCI accessors. Unlike those, they take the address first and the value 101 * next. 102 * 103 * Note: I might drop the _ns suffix on the stream operations soon as it is 104 * simply normal for stream operations to not swap in the first place. 105 * 106 */ 107 108 #ifdef CONFIG_PPC64 109 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0) 110 #else 111 #define IO_SET_SYNC_FLAG() 112 #endif 113 114 /* gcc 4.0 and older doesn't have 'Z' constraint */ 115 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0) 116 #define DEF_MMIO_IN_LE(name, size, insn) \ 117 static inline u##size name(const volatile u##size __iomem *addr) \ 118 { \ 119 u##size ret; \ 120 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \ 121 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \ 122 return ret; \ 123 } 124 125 #define DEF_MMIO_OUT_LE(name, size, insn) \ 126 static inline void name(volatile u##size __iomem *addr, u##size val) \ 127 { \ 128 __asm__ __volatile__("sync;"#insn" %1,0,%2" \ 129 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \ 130 IO_SET_SYNC_FLAG(); \ 131 } 132 #else /* newer gcc */ 133 #define DEF_MMIO_IN_LE(name, size, insn) \ 134 static inline u##size name(const volatile u##size __iomem *addr) \ 135 { \ 136 u##size ret; \ 137 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ 138 : "=r" (ret) : "Z" (*addr) : "memory"); \ 139 return ret; \ 140 } 141 142 #define DEF_MMIO_OUT_LE(name, size, insn) \ 143 static inline void name(volatile u##size __iomem *addr, u##size val) \ 144 { \ 145 __asm__ __volatile__("sync;"#insn" %1,%y0" \ 146 : "=Z" (*addr) : "r" (val) : "memory"); \ 147 IO_SET_SYNC_FLAG(); \ 148 } 149 #endif 150 151 #define DEF_MMIO_IN_BE(name, size, insn) \ 152 static inline u##size name(const volatile u##size __iomem *addr) \ 153 { \ 154 u##size ret; \ 155 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ 156 : "=r" (ret) : "m" (*addr) : "memory"); \ 157 return ret; \ 158 } 159 160 #define DEF_MMIO_OUT_BE(name, size, insn) \ 161 static inline void name(volatile u##size __iomem *addr, u##size val) \ 162 { \ 163 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ 164 : "=m" (*addr) : "r" (val) : "memory"); \ 165 IO_SET_SYNC_FLAG(); \ 166 } 167 168 169 DEF_MMIO_IN_BE(in_8, 8, lbz); 170 DEF_MMIO_IN_BE(in_be16, 16, lhz); 171 DEF_MMIO_IN_BE(in_be32, 32, lwz); 172 DEF_MMIO_IN_LE(in_le16, 16, lhbrx); 173 DEF_MMIO_IN_LE(in_le32, 32, lwbrx); 174 175 DEF_MMIO_OUT_BE(out_8, 8, stb); 176 DEF_MMIO_OUT_BE(out_be16, 16, sth); 177 DEF_MMIO_OUT_BE(out_be32, 32, stw); 178 DEF_MMIO_OUT_LE(out_le16, 16, sthbrx); 179 DEF_MMIO_OUT_LE(out_le32, 32, stwbrx); 180 181 #ifdef __powerpc64__ 182 DEF_MMIO_OUT_BE(out_be64, 64, std); 183 DEF_MMIO_IN_BE(in_be64, 64, ld); 184 185 /* There is no asm instructions for 64 bits reverse loads and stores */ 186 static inline u64 in_le64(const volatile u64 __iomem *addr) 187 { 188 return swab64(in_be64(addr)); 189 } 190 191 static inline void out_le64(volatile u64 __iomem *addr, u64 val) 192 { 193 out_be64(addr, swab64(val)); 194 } 195 #endif /* __powerpc64__ */ 196 197 /* 198 * Low level IO stream instructions are defined out of line for now 199 */ 200 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); 201 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); 202 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); 203 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); 204 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); 205 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); 206 207 /* The _ns naming is historical and will be removed. For now, just #define 208 * the non _ns equivalent names 209 */ 210 #define _insw _insw_ns 211 #define _insl _insl_ns 212 #define _outsw _outsw_ns 213 #define _outsl _outsl_ns 214 215 216 /* 217 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line 218 */ 219 220 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); 221 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, 222 unsigned long n); 223 extern void _memcpy_toio(volatile void __iomem *dest, const void *src, 224 unsigned long n); 225 226 /* 227 * 228 * PCI and standard ISA accessors 229 * 230 * Those are globally defined linux accessors for devices on PCI or ISA 231 * busses. They follow the Linux defined semantics. The current implementation 232 * for PowerPC is as close as possible to the x86 version of these, and thus 233 * provides fairly heavy weight barriers for the non-raw versions 234 * 235 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO 236 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its 237 * own implementation of some or all of the accessors. 238 */ 239 240 /* 241 * Include the EEH definitions when EEH is enabled only so they don't get 242 * in the way when building for 32 bits 243 */ 244 #ifdef CONFIG_EEH 245 #include <asm/eeh.h> 246 #endif 247 248 /* Shortcut to the MMIO argument pointer */ 249 #define PCI_IO_ADDR volatile void __iomem * 250 251 /* Indirect IO address tokens: 252 * 253 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks 254 * on all MMIOs. (Note that this is all 64 bits only for now) 255 * 256 * To help platforms who may need to differenciate MMIO addresses in 257 * their hooks, a bitfield is reserved for use by the platform near the 258 * top of MMIO addresses (not PIO, those have to cope the hard way). 259 * 260 * This bit field is 12 bits and is at the top of the IO virtual 261 * addresses PCI_IO_INDIRECT_TOKEN_MASK. 262 * 263 * The kernel virtual space is thus: 264 * 265 * 0xD000000000000000 : vmalloc 266 * 0xD000080000000000 : PCI PHB IO space 267 * 0xD000080080000000 : ioremap 268 * 0xD0000fffffffffff : end of ioremap region 269 * 270 * Since the top 4 bits are reserved as the region ID, we use thus 271 * the next 12 bits and keep 4 bits available for the future if the 272 * virtual address space is ever to be extended. 273 * 274 * The direct IO mapping operations will then mask off those bits 275 * before doing the actual access, though that only happen when 276 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that 277 * mechanism 278 * 279 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes 280 * all PIO functions call through a hook. 281 */ 282 283 #ifdef CONFIG_PPC_INDIRECT_MMIO 284 #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul 285 #define PCI_IO_IND_TOKEN_SHIFT 48 286 #define PCI_FIX_ADDR(addr) \ 287 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) 288 #define PCI_GET_ADDR_TOKEN(addr) \ 289 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ 290 PCI_IO_IND_TOKEN_SHIFT) 291 #define PCI_SET_ADDR_TOKEN(addr, token) \ 292 do { \ 293 unsigned long __a = (unsigned long)(addr); \ 294 __a &= ~PCI_IO_IND_TOKEN_MASK; \ 295 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ 296 (addr) = (void __iomem *)__a; \ 297 } while(0) 298 #else 299 #define PCI_FIX_ADDR(addr) (addr) 300 #endif 301 302 303 /* 304 * Non ordered and non-swapping "raw" accessors 305 */ 306 307 static inline unsigned char __raw_readb(const volatile void __iomem *addr) 308 { 309 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); 310 } 311 static inline unsigned short __raw_readw(const volatile void __iomem *addr) 312 { 313 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); 314 } 315 static inline unsigned int __raw_readl(const volatile void __iomem *addr) 316 { 317 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); 318 } 319 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 320 { 321 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; 322 } 323 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 324 { 325 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; 326 } 327 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 328 { 329 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; 330 } 331 332 #ifdef __powerpc64__ 333 static inline unsigned long __raw_readq(const volatile void __iomem *addr) 334 { 335 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); 336 } 337 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 338 { 339 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; 340 } 341 #endif /* __powerpc64__ */ 342 343 /* 344 * 345 * PCI PIO and MMIO accessors. 346 * 347 * 348 * On 32 bits, PIO operations have a recovery mechanism in case they trigger 349 * machine checks (which they occasionally do when probing non existing 350 * IO ports on some platforms, like PowerMac and 8xx). 351 * I always found it to be of dubious reliability and I am tempted to get 352 * rid of it one of these days. So if you think it's important to keep it, 353 * please voice up asap. We never had it for 64 bits and I do not intend 354 * to port it over 355 */ 356 357 #ifdef CONFIG_PPC32 358 359 #define __do_in_asm(name, op) \ 360 static inline unsigned int name(unsigned int port) \ 361 { \ 362 unsigned int x; \ 363 __asm__ __volatile__( \ 364 "sync\n" \ 365 "0:" op " %0,0,%1\n" \ 366 "1: twi 0,%0,0\n" \ 367 "2: isync\n" \ 368 "3: nop\n" \ 369 "4:\n" \ 370 ".section .fixup,\"ax\"\n" \ 371 "5: li %0,-1\n" \ 372 " b 4b\n" \ 373 ".previous\n" \ 374 ".section __ex_table,\"a\"\n" \ 375 " .align 2\n" \ 376 " .long 0b,5b\n" \ 377 " .long 1b,5b\n" \ 378 " .long 2b,5b\n" \ 379 " .long 3b,5b\n" \ 380 ".previous" \ 381 : "=&r" (x) \ 382 : "r" (port + _IO_BASE) \ 383 : "memory"); \ 384 return x; \ 385 } 386 387 #define __do_out_asm(name, op) \ 388 static inline void name(unsigned int val, unsigned int port) \ 389 { \ 390 __asm__ __volatile__( \ 391 "sync\n" \ 392 "0:" op " %0,0,%1\n" \ 393 "1: sync\n" \ 394 "2:\n" \ 395 ".section __ex_table,\"a\"\n" \ 396 " .align 2\n" \ 397 " .long 0b,2b\n" \ 398 " .long 1b,2b\n" \ 399 ".previous" \ 400 : : "r" (val), "r" (port + _IO_BASE) \ 401 : "memory"); \ 402 } 403 404 __do_in_asm(_rec_inb, "lbzx") 405 __do_in_asm(_rec_inw, "lhbrx") 406 __do_in_asm(_rec_inl, "lwbrx") 407 __do_out_asm(_rec_outb, "stbx") 408 __do_out_asm(_rec_outw, "sthbrx") 409 __do_out_asm(_rec_outl, "stwbrx") 410 411 #endif /* CONFIG_PPC32 */ 412 413 /* The "__do_*" operations below provide the actual "base" implementation 414 * for each of the defined accessors. Some of them use the out_* functions 415 * directly, some of them still use EEH, though we might change that in the 416 * future. Those macros below provide the necessary argument swapping and 417 * handling of the IO base for PIO. 418 * 419 * They are themselves used by the macros that define the actual accessors 420 * and can be used by the hooks if any. 421 * 422 * Note that PIO operations are always defined in terms of their corresonding 423 * MMIO operations. That allows platforms like iSeries who want to modify the 424 * behaviour of both to only hook on the MMIO version and get both. It's also 425 * possible to hook directly at the toplevel PIO operation if they have to 426 * be handled differently 427 */ 428 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) 429 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) 430 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) 431 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) 432 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) 433 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) 434 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) 435 436 #ifdef CONFIG_EEH 437 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) 438 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) 439 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) 440 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) 441 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) 442 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) 443 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) 444 #else /* CONFIG_EEH */ 445 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) 446 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) 447 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) 448 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) 449 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) 450 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) 451 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) 452 #endif /* !defined(CONFIG_EEH) */ 453 454 #ifdef CONFIG_PPC32 455 #define __do_outb(val, port) _rec_outb(val, port) 456 #define __do_outw(val, port) _rec_outw(val, port) 457 #define __do_outl(val, port) _rec_outl(val, port) 458 #define __do_inb(port) _rec_inb(port) 459 #define __do_inw(port) _rec_inw(port) 460 #define __do_inl(port) _rec_inl(port) 461 #else /* CONFIG_PPC32 */ 462 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); 463 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); 464 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); 465 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); 466 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); 467 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); 468 #endif /* !CONFIG_PPC32 */ 469 470 #ifdef CONFIG_EEH 471 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) 472 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) 473 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) 474 #else /* CONFIG_EEH */ 475 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) 476 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) 477 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) 478 #endif /* !CONFIG_EEH */ 479 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) 480 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) 481 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) 482 483 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 484 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 485 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 486 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 487 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 488 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 489 490 #define __do_memset_io(addr, c, n) \ 491 _memset_io(PCI_FIX_ADDR(addr), c, n) 492 #define __do_memcpy_toio(dst, src, n) \ 493 _memcpy_toio(PCI_FIX_ADDR(dst), src, n) 494 495 #ifdef CONFIG_EEH 496 #define __do_memcpy_fromio(dst, src, n) \ 497 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) 498 #else /* CONFIG_EEH */ 499 #define __do_memcpy_fromio(dst, src, n) \ 500 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) 501 #endif /* !CONFIG_EEH */ 502 503 #ifdef CONFIG_PPC_INDIRECT_PIO 504 #define DEF_PCI_HOOK_pio(x) x 505 #else 506 #define DEF_PCI_HOOK_pio(x) NULL 507 #endif 508 509 #ifdef CONFIG_PPC_INDIRECT_MMIO 510 #define DEF_PCI_HOOK_mem(x) x 511 #else 512 #define DEF_PCI_HOOK_mem(x) NULL 513 #endif 514 515 /* Structure containing all the hooks */ 516 extern struct ppc_pci_io { 517 518 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at; 519 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at; 520 521 #include <asm/io-defs.h> 522 523 #undef DEF_PCI_AC_RET 524 #undef DEF_PCI_AC_NORET 525 526 } ppc_pci_io; 527 528 /* The inline wrappers */ 529 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ 530 static inline ret name at \ 531 { \ 532 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 533 return ppc_pci_io.name al; \ 534 return __do_##name al; \ 535 } 536 537 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \ 538 static inline void name at \ 539 { \ 540 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 541 ppc_pci_io.name al; \ 542 else \ 543 __do_##name al; \ 544 } 545 546 #include <asm/io-defs.h> 547 548 #undef DEF_PCI_AC_RET 549 #undef DEF_PCI_AC_NORET 550 551 /* Some drivers check for the presence of readq & writeq with 552 * a #ifdef, so we make them happy here. 553 */ 554 #ifdef __powerpc64__ 555 #define readq readq 556 #define writeq writeq 557 #endif 558 559 /* 560 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 561 * access 562 */ 563 #define xlate_dev_mem_ptr(p) __va(p) 564 565 /* 566 * Convert a virtual cached pointer to an uncached pointer 567 */ 568 #define xlate_dev_kmem_ptr(p) p 569 570 /* 571 * We don't do relaxed operations yet, at least not with this semantic 572 */ 573 #define readb_relaxed(addr) readb(addr) 574 #define readw_relaxed(addr) readw(addr) 575 #define readl_relaxed(addr) readl(addr) 576 #define readq_relaxed(addr) readq(addr) 577 578 #ifdef CONFIG_PPC32 579 #define mmiowb() 580 #else 581 /* 582 * Enforce synchronisation of stores vs. spin_unlock 583 * (this does it explicitly, though our implementation of spin_unlock 584 * does it implicitely too) 585 */ 586 static inline void mmiowb(void) 587 { 588 unsigned long tmp; 589 590 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)" 591 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) 592 : "memory"); 593 } 594 #endif /* !CONFIG_PPC32 */ 595 596 static inline void iosync(void) 597 { 598 __asm__ __volatile__ ("sync" : : : "memory"); 599 } 600 601 /* Enforce in-order execution of data I/O. 602 * No distinction between read/write on PPC; use eieio for all three. 603 * Those are fairly week though. They don't provide a barrier between 604 * MMIO and cacheable storage nor do they provide a barrier vs. locks, 605 * they only provide barriers between 2 __raw MMIO operations and 606 * possibly break write combining. 607 */ 608 #define iobarrier_rw() eieio() 609 #define iobarrier_r() eieio() 610 #define iobarrier_w() eieio() 611 612 613 /* 614 * output pause versions need a delay at least for the 615 * w83c105 ide controller in a p610. 616 */ 617 #define inb_p(port) inb(port) 618 #define outb_p(val, port) (udelay(1), outb((val), (port))) 619 #define inw_p(port) inw(port) 620 #define outw_p(val, port) (udelay(1), outw((val), (port))) 621 #define inl_p(port) inl(port) 622 #define outl_p(val, port) (udelay(1), outl((val), (port))) 623 624 625 #define IO_SPACE_LIMIT ~(0UL) 626 627 628 /** 629 * ioremap - map bus memory into CPU space 630 * @address: bus address of the memory 631 * @size: size of the resource to map 632 * 633 * ioremap performs a platform specific sequence of operations to 634 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 635 * writew/writel functions and the other mmio helpers. The returned 636 * address is not guaranteed to be usable directly as a virtual 637 * address. 638 * 639 * We provide a few variations of it: 640 * 641 * * ioremap is the standard one and provides non-cacheable guarded mappings 642 * and can be hooked by the platform via ppc_md 643 * 644 * * ioremap_prot allows to specify the page flags as an argument and can 645 * also be hooked by the platform via ppc_md. 646 * 647 * * ioremap_nocache is identical to ioremap 648 * 649 * * ioremap_wc enables write combining 650 * 651 * * iounmap undoes such a mapping and can be hooked 652 * 653 * * __ioremap_at (and the pending __iounmap_at) are low level functions to 654 * create hand-made mappings for use only by the PCI code and cannot 655 * currently be hooked. Must be page aligned. 656 * 657 * * __ioremap is the low level implementation used by ioremap and 658 * ioremap_prot and cannot be hooked (but can be used by a hook on one 659 * of the previous ones) 660 * 661 * * __ioremap_caller is the same as above but takes an explicit caller 662 * reference rather than using __builtin_return_address(0) 663 * 664 * * __iounmap, is the low level implementation used by iounmap and cannot 665 * be hooked (but can be used by a hook on iounmap) 666 * 667 */ 668 extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 669 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size, 670 unsigned long flags); 671 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size); 672 #define ioremap_nocache(addr, size) ioremap((addr), (size)) 673 674 extern void iounmap(volatile void __iomem *addr); 675 676 extern void __iomem *__ioremap(phys_addr_t, unsigned long size, 677 unsigned long flags); 678 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size, 679 unsigned long flags, void *caller); 680 681 extern void __iounmap(volatile void __iomem *addr); 682 683 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea, 684 unsigned long size, unsigned long flags); 685 extern void __iounmap_at(void *ea, unsigned long size); 686 687 /* 688 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation 689 * which needs some additional definitions here. They basically allow PIO 690 * space overall to be 1GB. This will work as long as we never try to use 691 * iomap to map MMIO below 1GB which should be fine on ppc64 692 */ 693 #define HAVE_ARCH_PIO_SIZE 1 694 #define PIO_OFFSET 0x00000000UL 695 #define PIO_MASK (FULL_IO_SIZE - 1) 696 #define PIO_RESERVED (FULL_IO_SIZE) 697 698 #define mmio_read16be(addr) readw_be(addr) 699 #define mmio_read32be(addr) readl_be(addr) 700 #define mmio_write16be(val, addr) writew_be(val, addr) 701 #define mmio_write32be(val, addr) writel_be(val, addr) 702 #define mmio_insb(addr, dst, count) readsb(addr, dst, count) 703 #define mmio_insw(addr, dst, count) readsw(addr, dst, count) 704 #define mmio_insl(addr, dst, count) readsl(addr, dst, count) 705 #define mmio_outsb(addr, src, count) writesb(addr, src, count) 706 #define mmio_outsw(addr, src, count) writesw(addr, src, count) 707 #define mmio_outsl(addr, src, count) writesl(addr, src, count) 708 709 /** 710 * virt_to_phys - map virtual addresses to physical 711 * @address: address to remap 712 * 713 * The returned physical address is the physical (CPU) mapping for 714 * the memory address given. It is only valid to use this function on 715 * addresses directly mapped or allocated via kmalloc. 716 * 717 * This function does not give bus mappings for DMA transfers. In 718 * almost all conceivable cases a device driver should not be using 719 * this function 720 */ 721 static inline unsigned long virt_to_phys(volatile void * address) 722 { 723 return __pa((unsigned long)address); 724 } 725 726 /** 727 * phys_to_virt - map physical address to virtual 728 * @address: address to remap 729 * 730 * The returned virtual address is a current CPU mapping for 731 * the memory address given. It is only valid to use this function on 732 * addresses that have a kernel mapping 733 * 734 * This function does not handle bus mappings for DMA transfers. In 735 * almost all conceivable cases a device driver should not be using 736 * this function 737 */ 738 static inline void * phys_to_virt(unsigned long address) 739 { 740 return (void *)__va(address); 741 } 742 743 /* 744 * Change "struct page" to physical address. 745 */ 746 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT) 747 748 /* 749 * 32 bits still uses virt_to_bus() for it's implementation of DMA 750 * mappings se we have to keep it defined here. We also have some old 751 * drivers (shame shame shame) that use bus_to_virt() and haven't been 752 * fixed yet so I need to define it here. 753 */ 754 #ifdef CONFIG_PPC32 755 756 static inline unsigned long virt_to_bus(volatile void * address) 757 { 758 if (address == NULL) 759 return 0; 760 return __pa(address) + PCI_DRAM_OFFSET; 761 } 762 763 static inline void * bus_to_virt(unsigned long address) 764 { 765 if (address == 0) 766 return NULL; 767 return __va(address - PCI_DRAM_OFFSET); 768 } 769 770 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) 771 772 #endif /* CONFIG_PPC32 */ 773 774 /* access ports */ 775 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) 776 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) 777 778 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) 779 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) 780 781 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) 782 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) 783 784 /* Clear and set bits in one shot. These macros can be used to clear and 785 * set multiple bits in a register using a single read-modify-write. These 786 * macros can also be used to set a multiple-bit bit pattern using a mask, 787 * by specifying the mask in the 'clear' parameter and the new bit pattern 788 * in the 'set' parameter. 789 */ 790 791 #define clrsetbits(type, addr, clear, set) \ 792 out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) 793 794 #ifdef __powerpc64__ 795 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) 796 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) 797 #endif 798 799 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) 800 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) 801 802 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) 803 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) 804 805 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) 806 807 void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset, 808 size_t size, unsigned long flags); 809 810 #endif /* __KERNEL__ */ 811 812 #endif /* _ASM_POWERPC_IO_H */ 813