1 #ifndef __ASM_POWERPC_IMC_PMU_H 2 #define __ASM_POWERPC_IMC_PMU_H 3 4 /* 5 * IMC Nest Performance Monitor counter support. 6 * 7 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation. 8 * (C) 2017 Anju T Sudhakar, IBM Corporation. 9 * (C) 2017 Hemant K Shaw, IBM Corporation. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or later version. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/slab.h> 19 #include <linux/of.h> 20 #include <linux/io.h> 21 #include <asm/opal.h> 22 23 /* 24 * Compatibility macros for IMC devices 25 */ 26 #define IMC_DTB_COMPAT "ibm,opal-in-memory-counters" 27 #define IMC_DTB_UNIT_COMPAT "ibm,imc-counters" 28 29 30 /* 31 * LDBAR: Counter address and Enable/Disable macro. 32 * perf/imc-pmu.c has the LDBAR layout information. 33 */ 34 #define THREAD_IMC_LDBAR_MASK 0x0003ffffffffe000ULL 35 #define THREAD_IMC_ENABLE 0x8000000000000000ULL 36 37 /* 38 * Structure to hold memory address information for imc units. 39 */ 40 struct imc_mem_info { 41 u64 *vbase; 42 u32 id; 43 }; 44 45 /* 46 * Place holder for nest pmu events and values. 47 */ 48 struct imc_events { 49 u32 value; 50 char *name; 51 char *unit; 52 char *scale; 53 }; 54 55 /* Event attribute array index */ 56 #define IMC_FORMAT_ATTR 0 57 #define IMC_EVENT_ATTR 1 58 #define IMC_CPUMASK_ATTR 2 59 #define IMC_NULL_ATTR 3 60 61 /* PMU Format attribute macros */ 62 #define IMC_EVENT_OFFSET_MASK 0xffffffffULL 63 64 /* 65 * Device tree parser code detects IMC pmu support and 66 * registers new IMC pmus. This structure will hold the 67 * pmu functions, events, counter memory information 68 * and attrs for each imc pmu and will be referenced at 69 * the time of pmu registration. 70 */ 71 struct imc_pmu { 72 struct pmu pmu; 73 struct imc_mem_info *mem_info; 74 struct imc_events **events; 75 /* 76 * Attribute groups for the PMU. Slot 0 used for 77 * format attribute, slot 1 used for cpusmask attribute, 78 * slot 2 used for event attribute. Slot 3 keep as 79 * NULL. 80 */ 81 const struct attribute_group *attr_groups[4]; 82 u32 counter_mem_size; 83 int domain; 84 /* 85 * flag to notify whether the memory is mmaped 86 * or allocated by kernel. 87 */ 88 bool imc_counter_mmaped; 89 }; 90 91 /* 92 * Structure to hold id, lock and reference count for the imc events which 93 * are inited. 94 */ 95 struct imc_pmu_ref { 96 struct mutex lock; 97 unsigned int id; 98 int refc; 99 }; 100 101 /* 102 * In-Memory Collection Counters type. 103 * Data comes from Device tree. 104 * Three device type are supported. 105 */ 106 107 enum { 108 IMC_TYPE_THREAD = 0x1, 109 IMC_TYPE_CORE = 0x4, 110 IMC_TYPE_CHIP = 0x10, 111 }; 112 113 /* 114 * Domains for IMC PMUs 115 */ 116 #define IMC_DOMAIN_NEST 1 117 #define IMC_DOMAIN_CORE 2 118 #define IMC_DOMAIN_THREAD 3 119 120 extern int init_imc_pmu(struct device_node *parent, 121 struct imc_pmu *pmu_ptr, int pmu_id); 122 extern void thread_imc_disable(void); 123 extern int get_max_nest_dev(void); 124 #endif /* __ASM_POWERPC_IMC_PMU_H */ 125