1 /* 2 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation. 3 * Copyright 2001-2012 IBM Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #ifndef _POWERPC_EEH_H 21 #define _POWERPC_EEH_H 22 #ifdef __KERNEL__ 23 24 #include <linux/init.h> 25 #include <linux/list.h> 26 #include <linux/string.h> 27 #include <linux/time.h> 28 #include <linux/atomic.h> 29 30 struct pci_dev; 31 struct pci_bus; 32 struct device_node; 33 34 #ifdef CONFIG_EEH 35 36 /* EEH subsystem flags */ 37 #define EEH_ENABLED 0x01 /* EEH enabled */ 38 #define EEH_FORCE_DISABLED 0x02 /* EEH disabled */ 39 #define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */ 40 #define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */ 41 #define EEH_ENABLE_IO_FOR_LOG 0x10 /* Enable IO for log */ 42 #define EEH_EARLY_DUMP_LOG 0x20 /* Dump log immediately */ 43 44 /* 45 * Delay for PE reset, all in ms 46 * 47 * PCI specification has reset hold time of 100 milliseconds. 48 * We have 250 milliseconds here. The PCI bus settlement time 49 * is specified as 1.5 seconds and we have 1.8 seconds. 50 */ 51 #define EEH_PE_RST_HOLD_TIME 250 52 #define EEH_PE_RST_SETTLE_TIME 1800 53 54 /* 55 * The struct is used to trace PE related EEH functionality. 56 * In theory, there will have one instance of the struct to 57 * be created against particular PE. In nature, PEs corelate 58 * to each other. the struct has to reflect that hierarchy in 59 * order to easily pick up those affected PEs when one particular 60 * PE has EEH errors. 61 * 62 * Also, one particular PE might be composed of PCI device, PCI 63 * bus and its subordinate components. The struct also need ship 64 * the information. Further more, one particular PE is only meaingful 65 * in the corresponding PHB. Therefore, the root PEs should be created 66 * against existing PHBs in on-to-one fashion. 67 */ 68 #define EEH_PE_INVALID (1 << 0) /* Invalid */ 69 #define EEH_PE_PHB (1 << 1) /* PHB PE */ 70 #define EEH_PE_DEVICE (1 << 2) /* Device PE */ 71 #define EEH_PE_BUS (1 << 3) /* Bus PE */ 72 73 #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */ 74 #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */ 75 #define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */ 76 #define EEH_PE_RESET (1 << 3) /* PE reset in progress */ 77 78 #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ 79 #define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */ 80 81 struct eeh_pe { 82 int type; /* PE type: PHB/Bus/Device */ 83 int state; /* PE EEH dependent mode */ 84 int config_addr; /* Traditional PCI address */ 85 int addr; /* PE configuration address */ 86 struct pci_controller *phb; /* Associated PHB */ 87 struct pci_bus *bus; /* Top PCI bus for bus PE */ 88 int check_count; /* Times of ignored error */ 89 int freeze_count; /* Times of froze up */ 90 struct timeval tstamp; /* Time on first-time freeze */ 91 int false_positives; /* Times of reported #ff's */ 92 atomic_t pass_dev_cnt; /* Count of passed through devs */ 93 struct eeh_pe *parent; /* Parent PE */ 94 void *data; /* PE auxillary data */ 95 struct list_head child_list; /* Link PE to the child list */ 96 struct list_head edevs; /* Link list of EEH devices */ 97 struct list_head child; /* Child PEs */ 98 }; 99 100 #define eeh_pe_for_each_dev(pe, edev, tmp) \ 101 list_for_each_entry_safe(edev, tmp, &pe->edevs, list) 102 103 static inline bool eeh_pe_passed(struct eeh_pe *pe) 104 { 105 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false; 106 } 107 108 /* 109 * The struct is used to trace EEH state for the associated 110 * PCI device node or PCI device. In future, it might 111 * represent PE as well so that the EEH device to form 112 * another tree except the currently existing tree of PCI 113 * buses and PCI devices 114 */ 115 #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */ 116 #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */ 117 #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */ 118 #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */ 119 #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */ 120 121 #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */ 122 #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */ 123 #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */ 124 125 struct eeh_dev { 126 int mode; /* EEH mode */ 127 int class_code; /* Class code of the device */ 128 int config_addr; /* Config address */ 129 int pe_config_addr; /* PE config address */ 130 u32 config_space[16]; /* Saved PCI config space */ 131 int pcix_cap; /* Saved PCIx capability */ 132 int pcie_cap; /* Saved PCIe capability */ 133 int aer_cap; /* Saved AER capability */ 134 struct eeh_pe *pe; /* Associated PE */ 135 struct list_head list; /* Form link list in the PE */ 136 struct pci_controller *phb; /* Associated PHB */ 137 struct device_node *dn; /* Associated device node */ 138 struct pci_dev *pdev; /* Associated PCI device */ 139 struct pci_bus *bus; /* PCI bus for partial hotplug */ 140 }; 141 142 static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev) 143 { 144 return edev ? edev->dn : NULL; 145 } 146 147 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev) 148 { 149 return edev ? edev->pdev : NULL; 150 } 151 152 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev) 153 { 154 return edev ? edev->pe : NULL; 155 } 156 157 /* Return values from eeh_ops::next_error */ 158 enum { 159 EEH_NEXT_ERR_NONE = 0, 160 EEH_NEXT_ERR_INF, 161 EEH_NEXT_ERR_FROZEN_PE, 162 EEH_NEXT_ERR_FENCED_PHB, 163 EEH_NEXT_ERR_DEAD_PHB, 164 EEH_NEXT_ERR_DEAD_IOC 165 }; 166 167 /* 168 * The struct is used to trace the registered EEH operation 169 * callback functions. Actually, those operation callback 170 * functions are heavily platform dependent. That means the 171 * platform should register its own EEH operation callback 172 * functions before any EEH further operations. 173 */ 174 #define EEH_OPT_DISABLE 0 /* EEH disable */ 175 #define EEH_OPT_ENABLE 1 /* EEH enable */ 176 #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */ 177 #define EEH_OPT_THAW_DMA 3 /* DMA enable */ 178 #define EEH_OPT_FREEZE_PE 4 /* Freeze PE */ 179 #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */ 180 #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */ 181 #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */ 182 #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */ 183 #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */ 184 #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */ 185 #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */ 186 #define EEH_PE_STATE_NORMAL 0 /* Normal state */ 187 #define EEH_PE_STATE_RESET 1 /* PE reset asserted */ 188 #define EEH_PE_STATE_STOPPED_IO_DMA 2 /* Frozen PE */ 189 #define EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA, Enabled IO */ 190 #define EEH_PE_STATE_UNAVAIL 5 /* Unavailable */ 191 #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */ 192 #define EEH_RESET_HOT 1 /* Hot reset */ 193 #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */ 194 #define EEH_LOG_TEMP 1 /* EEH temporary error log */ 195 #define EEH_LOG_PERM 2 /* EEH permanent error log */ 196 197 struct eeh_ops { 198 char *name; 199 int (*init)(void); 200 int (*post_init)(void); 201 void* (*of_probe)(struct device_node *dn, void *flag); 202 int (*dev_probe)(struct pci_dev *dev, void *flag); 203 int (*set_option)(struct eeh_pe *pe, int option); 204 int (*get_pe_addr)(struct eeh_pe *pe); 205 int (*get_state)(struct eeh_pe *pe, int *state); 206 int (*reset)(struct eeh_pe *pe, int option); 207 int (*wait_state)(struct eeh_pe *pe, int max_wait); 208 int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len); 209 int (*configure_bridge)(struct eeh_pe *pe); 210 int (*err_inject)(struct eeh_pe *pe, int type, int func, 211 unsigned long addr, unsigned long mask); 212 int (*read_config)(struct device_node *dn, int where, int size, u32 *val); 213 int (*write_config)(struct device_node *dn, int where, int size, u32 val); 214 int (*next_error)(struct eeh_pe **pe); 215 int (*restore_config)(struct device_node *dn); 216 }; 217 218 extern int eeh_subsystem_flags; 219 extern struct eeh_ops *eeh_ops; 220 extern raw_spinlock_t confirm_error_lock; 221 222 static inline void eeh_add_flag(int flag) 223 { 224 eeh_subsystem_flags |= flag; 225 } 226 227 static inline void eeh_clear_flag(int flag) 228 { 229 eeh_subsystem_flags &= ~flag; 230 } 231 232 static inline bool eeh_has_flag(int flag) 233 { 234 return !!(eeh_subsystem_flags & flag); 235 } 236 237 static inline bool eeh_enabled(void) 238 { 239 if (eeh_has_flag(EEH_FORCE_DISABLED) || 240 !eeh_has_flag(EEH_ENABLED)) 241 return false; 242 243 return true; 244 } 245 246 static inline void eeh_serialize_lock(unsigned long *flags) 247 { 248 raw_spin_lock_irqsave(&confirm_error_lock, *flags); 249 } 250 251 static inline void eeh_serialize_unlock(unsigned long flags) 252 { 253 raw_spin_unlock_irqrestore(&confirm_error_lock, flags); 254 } 255 256 /* 257 * Max number of EEH freezes allowed before we consider the device 258 * to be permanently disabled. 259 */ 260 #define EEH_MAX_ALLOWED_FREEZES 5 261 262 typedef void *(*eeh_traverse_func)(void *data, void *flag); 263 void eeh_set_pe_aux_size(int size); 264 int eeh_phb_pe_create(struct pci_controller *phb); 265 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb); 266 struct eeh_pe *eeh_pe_get(struct eeh_dev *edev); 267 int eeh_add_to_parent_pe(struct eeh_dev *edev); 268 int eeh_rmv_from_parent_pe(struct eeh_dev *edev); 269 void eeh_pe_update_time_stamp(struct eeh_pe *pe); 270 void *eeh_pe_traverse(struct eeh_pe *root, 271 eeh_traverse_func fn, void *flag); 272 void *eeh_pe_dev_traverse(struct eeh_pe *root, 273 eeh_traverse_func fn, void *flag); 274 void eeh_pe_restore_bars(struct eeh_pe *pe); 275 const char *eeh_pe_loc_get(struct eeh_pe *pe); 276 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe); 277 278 void *eeh_dev_init(struct device_node *dn, void *data); 279 void eeh_dev_phb_init_dynamic(struct pci_controller *phb); 280 int eeh_init(void); 281 int __init eeh_ops_register(struct eeh_ops *ops); 282 int __exit eeh_ops_unregister(const char *name); 283 int eeh_check_failure(const volatile void __iomem *token); 284 int eeh_dev_check_failure(struct eeh_dev *edev); 285 void eeh_addr_cache_build(void); 286 void eeh_add_device_early(struct device_node *); 287 void eeh_add_device_tree_early(struct device_node *); 288 void eeh_add_device_late(struct pci_dev *); 289 void eeh_add_device_tree_late(struct pci_bus *); 290 void eeh_add_sysfs_files(struct pci_bus *); 291 void eeh_remove_device(struct pci_dev *); 292 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state); 293 int eeh_pe_reset_and_recover(struct eeh_pe *pe); 294 int eeh_dev_open(struct pci_dev *pdev); 295 void eeh_dev_release(struct pci_dev *pdev); 296 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group); 297 int eeh_pe_set_option(struct eeh_pe *pe, int option); 298 int eeh_pe_get_state(struct eeh_pe *pe); 299 int eeh_pe_reset(struct eeh_pe *pe, int option); 300 int eeh_pe_configure(struct eeh_pe *pe); 301 302 /** 303 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure. 304 * 305 * If this macro yields TRUE, the caller relays to eeh_check_failure() 306 * which does further tests out of line. 307 */ 308 #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled()) 309 310 /* 311 * Reads from a device which has been isolated by EEH will return 312 * all 1s. This macro gives an all-1s value of the given size (in 313 * bytes: 1, 2, or 4) for comparing with the result of a read. 314 */ 315 #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8)) 316 317 #else /* !CONFIG_EEH */ 318 319 static inline bool eeh_enabled(void) 320 { 321 return false; 322 } 323 324 static inline int eeh_init(void) 325 { 326 return 0; 327 } 328 329 static inline void *eeh_dev_init(struct device_node *dn, void *data) 330 { 331 return NULL; 332 } 333 334 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { } 335 336 static inline int eeh_check_failure(const volatile void __iomem *token) 337 { 338 return 0; 339 } 340 341 #define eeh_dev_check_failure(x) (0) 342 343 static inline void eeh_addr_cache_build(void) { } 344 345 static inline void eeh_add_device_early(struct device_node *dn) { } 346 347 static inline void eeh_add_device_tree_early(struct device_node *dn) { } 348 349 static inline void eeh_add_device_late(struct pci_dev *dev) { } 350 351 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { } 352 353 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { } 354 355 static inline void eeh_remove_device(struct pci_dev *dev) { } 356 357 #define EEH_POSSIBLE_ERROR(val, type) (0) 358 #define EEH_IO_ERROR_VALUE(size) (-1UL) 359 #endif /* CONFIG_EEH */ 360 361 #ifdef CONFIG_PPC64 362 /* 363 * MMIO read/write operations with EEH support. 364 */ 365 static inline u8 eeh_readb(const volatile void __iomem *addr) 366 { 367 u8 val = in_8(addr); 368 if (EEH_POSSIBLE_ERROR(val, u8)) 369 eeh_check_failure(addr); 370 return val; 371 } 372 373 static inline u16 eeh_readw(const volatile void __iomem *addr) 374 { 375 u16 val = in_le16(addr); 376 if (EEH_POSSIBLE_ERROR(val, u16)) 377 eeh_check_failure(addr); 378 return val; 379 } 380 381 static inline u32 eeh_readl(const volatile void __iomem *addr) 382 { 383 u32 val = in_le32(addr); 384 if (EEH_POSSIBLE_ERROR(val, u32)) 385 eeh_check_failure(addr); 386 return val; 387 } 388 389 static inline u64 eeh_readq(const volatile void __iomem *addr) 390 { 391 u64 val = in_le64(addr); 392 if (EEH_POSSIBLE_ERROR(val, u64)) 393 eeh_check_failure(addr); 394 return val; 395 } 396 397 static inline u16 eeh_readw_be(const volatile void __iomem *addr) 398 { 399 u16 val = in_be16(addr); 400 if (EEH_POSSIBLE_ERROR(val, u16)) 401 eeh_check_failure(addr); 402 return val; 403 } 404 405 static inline u32 eeh_readl_be(const volatile void __iomem *addr) 406 { 407 u32 val = in_be32(addr); 408 if (EEH_POSSIBLE_ERROR(val, u32)) 409 eeh_check_failure(addr); 410 return val; 411 } 412 413 static inline u64 eeh_readq_be(const volatile void __iomem *addr) 414 { 415 u64 val = in_be64(addr); 416 if (EEH_POSSIBLE_ERROR(val, u64)) 417 eeh_check_failure(addr); 418 return val; 419 } 420 421 static inline void eeh_memcpy_fromio(void *dest, const 422 volatile void __iomem *src, 423 unsigned long n) 424 { 425 _memcpy_fromio(dest, src, n); 426 427 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes 428 * were copied. Check all four bytes. 429 */ 430 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32)) 431 eeh_check_failure(src); 432 } 433 434 /* in-string eeh macros */ 435 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf, 436 int ns) 437 { 438 _insb(addr, buf, ns); 439 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8)) 440 eeh_check_failure(addr); 441 } 442 443 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf, 444 int ns) 445 { 446 _insw(addr, buf, ns); 447 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16)) 448 eeh_check_failure(addr); 449 } 450 451 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf, 452 int nl) 453 { 454 _insl(addr, buf, nl); 455 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32)) 456 eeh_check_failure(addr); 457 } 458 459 #endif /* CONFIG_PPC64 */ 460 #endif /* __KERNEL__ */ 461 #endif /* _POWERPC_EEH_H */ 462