1 /* 2 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation. 3 * Copyright 2001-2012 IBM Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #ifndef _POWERPC_EEH_H 21 #define _POWERPC_EEH_H 22 #ifdef __KERNEL__ 23 24 #include <linux/init.h> 25 #include <linux/list.h> 26 #include <linux/string.h> 27 #include <linux/time.h> 28 #include <linux/atomic.h> 29 30 struct pci_dev; 31 struct pci_bus; 32 struct device_node; 33 34 #ifdef CONFIG_EEH 35 36 /* EEH subsystem flags */ 37 #define EEH_ENABLED 0x01 /* EEH enabled */ 38 #define EEH_FORCE_DISABLED 0x02 /* EEH disabled */ 39 #define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */ 40 #define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */ 41 #define EEH_ENABLE_IO_FOR_LOG 0x10 /* Enable IO for log */ 42 43 /* 44 * Delay for PE reset, all in ms 45 * 46 * PCI specification has reset hold time of 100 milliseconds. 47 * We have 250 milliseconds here. The PCI bus settlement time 48 * is specified as 1.5 seconds and we have 1.8 seconds. 49 */ 50 #define EEH_PE_RST_HOLD_TIME 250 51 #define EEH_PE_RST_SETTLE_TIME 1800 52 53 /* 54 * The struct is used to trace PE related EEH functionality. 55 * In theory, there will have one instance of the struct to 56 * be created against particular PE. In nature, PEs corelate 57 * to each other. the struct has to reflect that hierarchy in 58 * order to easily pick up those affected PEs when one particular 59 * PE has EEH errors. 60 * 61 * Also, one particular PE might be composed of PCI device, PCI 62 * bus and its subordinate components. The struct also need ship 63 * the information. Further more, one particular PE is only meaingful 64 * in the corresponding PHB. Therefore, the root PEs should be created 65 * against existing PHBs in on-to-one fashion. 66 */ 67 #define EEH_PE_INVALID (1 << 0) /* Invalid */ 68 #define EEH_PE_PHB (1 << 1) /* PHB PE */ 69 #define EEH_PE_DEVICE (1 << 2) /* Device PE */ 70 #define EEH_PE_BUS (1 << 3) /* Bus PE */ 71 72 #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */ 73 #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */ 74 #define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */ 75 76 #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ 77 #define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */ 78 79 struct eeh_pe { 80 int type; /* PE type: PHB/Bus/Device */ 81 int state; /* PE EEH dependent mode */ 82 int config_addr; /* Traditional PCI address */ 83 int addr; /* PE configuration address */ 84 struct pci_controller *phb; /* Associated PHB */ 85 struct pci_bus *bus; /* Top PCI bus for bus PE */ 86 int check_count; /* Times of ignored error */ 87 int freeze_count; /* Times of froze up */ 88 struct timeval tstamp; /* Time on first-time freeze */ 89 int false_positives; /* Times of reported #ff's */ 90 atomic_t pass_dev_cnt; /* Count of passed through devs */ 91 struct eeh_pe *parent; /* Parent PE */ 92 void *data; /* PE auxillary data */ 93 struct list_head child_list; /* Link PE to the child list */ 94 struct list_head edevs; /* Link list of EEH devices */ 95 struct list_head child; /* Child PEs */ 96 }; 97 98 #define eeh_pe_for_each_dev(pe, edev, tmp) \ 99 list_for_each_entry_safe(edev, tmp, &pe->edevs, list) 100 101 static inline bool eeh_pe_passed(struct eeh_pe *pe) 102 { 103 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false; 104 } 105 106 /* 107 * The struct is used to trace EEH state for the associated 108 * PCI device node or PCI device. In future, it might 109 * represent PE as well so that the EEH device to form 110 * another tree except the currently existing tree of PCI 111 * buses and PCI devices 112 */ 113 #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */ 114 #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */ 115 #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */ 116 #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */ 117 #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */ 118 119 #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */ 120 #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */ 121 #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */ 122 123 struct eeh_dev { 124 int mode; /* EEH mode */ 125 int class_code; /* Class code of the device */ 126 int config_addr; /* Config address */ 127 int pe_config_addr; /* PE config address */ 128 u32 config_space[16]; /* Saved PCI config space */ 129 int pcix_cap; /* Saved PCIx capability */ 130 int pcie_cap; /* Saved PCIe capability */ 131 int aer_cap; /* Saved AER capability */ 132 struct eeh_pe *pe; /* Associated PE */ 133 struct list_head list; /* Form link list in the PE */ 134 struct pci_controller *phb; /* Associated PHB */ 135 struct device_node *dn; /* Associated device node */ 136 struct pci_dev *pdev; /* Associated PCI device */ 137 struct pci_bus *bus; /* PCI bus for partial hotplug */ 138 }; 139 140 static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev) 141 { 142 return edev ? edev->dn : NULL; 143 } 144 145 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev) 146 { 147 return edev ? edev->pdev : NULL; 148 } 149 150 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev) 151 { 152 return edev ? edev->pe : NULL; 153 } 154 155 /* Return values from eeh_ops::next_error */ 156 enum { 157 EEH_NEXT_ERR_NONE = 0, 158 EEH_NEXT_ERR_INF, 159 EEH_NEXT_ERR_FROZEN_PE, 160 EEH_NEXT_ERR_FENCED_PHB, 161 EEH_NEXT_ERR_DEAD_PHB, 162 EEH_NEXT_ERR_DEAD_IOC 163 }; 164 165 /* 166 * The struct is used to trace the registered EEH operation 167 * callback functions. Actually, those operation callback 168 * functions are heavily platform dependent. That means the 169 * platform should register its own EEH operation callback 170 * functions before any EEH further operations. 171 */ 172 #define EEH_OPT_DISABLE 0 /* EEH disable */ 173 #define EEH_OPT_ENABLE 1 /* EEH enable */ 174 #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */ 175 #define EEH_OPT_THAW_DMA 3 /* DMA enable */ 176 #define EEH_OPT_FREEZE_PE 4 /* Freeze PE */ 177 #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */ 178 #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */ 179 #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */ 180 #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */ 181 #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */ 182 #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */ 183 #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */ 184 #define EEH_PE_STATE_NORMAL 0 /* Normal state */ 185 #define EEH_PE_STATE_RESET 1 /* PE reset asserted */ 186 #define EEH_PE_STATE_STOPPED_IO_DMA 2 /* Frozen PE */ 187 #define EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA, Enabled IO */ 188 #define EEH_PE_STATE_UNAVAIL 5 /* Unavailable */ 189 #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */ 190 #define EEH_RESET_HOT 1 /* Hot reset */ 191 #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */ 192 #define EEH_LOG_TEMP 1 /* EEH temporary error log */ 193 #define EEH_LOG_PERM 2 /* EEH permanent error log */ 194 195 struct eeh_ops { 196 char *name; 197 int (*init)(void); 198 int (*post_init)(void); 199 void* (*of_probe)(struct device_node *dn, void *flag); 200 int (*dev_probe)(struct pci_dev *dev, void *flag); 201 int (*set_option)(struct eeh_pe *pe, int option); 202 int (*get_pe_addr)(struct eeh_pe *pe); 203 int (*get_state)(struct eeh_pe *pe, int *state); 204 int (*reset)(struct eeh_pe *pe, int option); 205 int (*wait_state)(struct eeh_pe *pe, int max_wait); 206 int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len); 207 int (*configure_bridge)(struct eeh_pe *pe); 208 int (*err_inject)(struct eeh_pe *pe, int type, int func, 209 unsigned long addr, unsigned long mask); 210 int (*read_config)(struct device_node *dn, int where, int size, u32 *val); 211 int (*write_config)(struct device_node *dn, int where, int size, u32 val); 212 int (*next_error)(struct eeh_pe **pe); 213 int (*restore_config)(struct device_node *dn); 214 }; 215 216 extern int eeh_subsystem_flags; 217 extern struct eeh_ops *eeh_ops; 218 extern raw_spinlock_t confirm_error_lock; 219 220 static inline void eeh_add_flag(int flag) 221 { 222 eeh_subsystem_flags |= flag; 223 } 224 225 static inline void eeh_clear_flag(int flag) 226 { 227 eeh_subsystem_flags &= ~flag; 228 } 229 230 static inline bool eeh_has_flag(int flag) 231 { 232 return !!(eeh_subsystem_flags & flag); 233 } 234 235 static inline bool eeh_enabled(void) 236 { 237 if (eeh_has_flag(EEH_FORCE_DISABLED) || 238 !eeh_has_flag(EEH_ENABLED)) 239 return false; 240 241 return true; 242 } 243 244 static inline void eeh_serialize_lock(unsigned long *flags) 245 { 246 raw_spin_lock_irqsave(&confirm_error_lock, *flags); 247 } 248 249 static inline void eeh_serialize_unlock(unsigned long flags) 250 { 251 raw_spin_unlock_irqrestore(&confirm_error_lock, flags); 252 } 253 254 /* 255 * Max number of EEH freezes allowed before we consider the device 256 * to be permanently disabled. 257 */ 258 #define EEH_MAX_ALLOWED_FREEZES 5 259 260 typedef void *(*eeh_traverse_func)(void *data, void *flag); 261 void eeh_set_pe_aux_size(int size); 262 int eeh_phb_pe_create(struct pci_controller *phb); 263 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb); 264 struct eeh_pe *eeh_pe_get(struct eeh_dev *edev); 265 int eeh_add_to_parent_pe(struct eeh_dev *edev); 266 int eeh_rmv_from_parent_pe(struct eeh_dev *edev); 267 void eeh_pe_update_time_stamp(struct eeh_pe *pe); 268 void *eeh_pe_traverse(struct eeh_pe *root, 269 eeh_traverse_func fn, void *flag); 270 void *eeh_pe_dev_traverse(struct eeh_pe *root, 271 eeh_traverse_func fn, void *flag); 272 void eeh_pe_restore_bars(struct eeh_pe *pe); 273 const char *eeh_pe_loc_get(struct eeh_pe *pe); 274 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe); 275 276 void *eeh_dev_init(struct device_node *dn, void *data); 277 void eeh_dev_phb_init_dynamic(struct pci_controller *phb); 278 int eeh_init(void); 279 int __init eeh_ops_register(struct eeh_ops *ops); 280 int __exit eeh_ops_unregister(const char *name); 281 int eeh_check_failure(const volatile void __iomem *token); 282 int eeh_dev_check_failure(struct eeh_dev *edev); 283 void eeh_addr_cache_build(void); 284 void eeh_add_device_early(struct device_node *); 285 void eeh_add_device_tree_early(struct device_node *); 286 void eeh_add_device_late(struct pci_dev *); 287 void eeh_add_device_tree_late(struct pci_bus *); 288 void eeh_add_sysfs_files(struct pci_bus *); 289 void eeh_remove_device(struct pci_dev *); 290 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state); 291 int eeh_pe_reset_and_recover(struct eeh_pe *pe); 292 int eeh_dev_open(struct pci_dev *pdev); 293 void eeh_dev_release(struct pci_dev *pdev); 294 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group); 295 int eeh_pe_set_option(struct eeh_pe *pe, int option); 296 int eeh_pe_get_state(struct eeh_pe *pe); 297 int eeh_pe_reset(struct eeh_pe *pe, int option); 298 int eeh_pe_configure(struct eeh_pe *pe); 299 300 /** 301 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure. 302 * 303 * If this macro yields TRUE, the caller relays to eeh_check_failure() 304 * which does further tests out of line. 305 */ 306 #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled()) 307 308 /* 309 * Reads from a device which has been isolated by EEH will return 310 * all 1s. This macro gives an all-1s value of the given size (in 311 * bytes: 1, 2, or 4) for comparing with the result of a read. 312 */ 313 #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8)) 314 315 #else /* !CONFIG_EEH */ 316 317 static inline bool eeh_enabled(void) 318 { 319 return false; 320 } 321 322 static inline int eeh_init(void) 323 { 324 return 0; 325 } 326 327 static inline void *eeh_dev_init(struct device_node *dn, void *data) 328 { 329 return NULL; 330 } 331 332 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { } 333 334 static inline int eeh_check_failure(const volatile void __iomem *token) 335 { 336 return 0; 337 } 338 339 #define eeh_dev_check_failure(x) (0) 340 341 static inline void eeh_addr_cache_build(void) { } 342 343 static inline void eeh_add_device_early(struct device_node *dn) { } 344 345 static inline void eeh_add_device_tree_early(struct device_node *dn) { } 346 347 static inline void eeh_add_device_late(struct pci_dev *dev) { } 348 349 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { } 350 351 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { } 352 353 static inline void eeh_remove_device(struct pci_dev *dev) { } 354 355 #define EEH_POSSIBLE_ERROR(val, type) (0) 356 #define EEH_IO_ERROR_VALUE(size) (-1UL) 357 #endif /* CONFIG_EEH */ 358 359 #ifdef CONFIG_PPC64 360 /* 361 * MMIO read/write operations with EEH support. 362 */ 363 static inline u8 eeh_readb(const volatile void __iomem *addr) 364 { 365 u8 val = in_8(addr); 366 if (EEH_POSSIBLE_ERROR(val, u8)) 367 eeh_check_failure(addr); 368 return val; 369 } 370 371 static inline u16 eeh_readw(const volatile void __iomem *addr) 372 { 373 u16 val = in_le16(addr); 374 if (EEH_POSSIBLE_ERROR(val, u16)) 375 eeh_check_failure(addr); 376 return val; 377 } 378 379 static inline u32 eeh_readl(const volatile void __iomem *addr) 380 { 381 u32 val = in_le32(addr); 382 if (EEH_POSSIBLE_ERROR(val, u32)) 383 eeh_check_failure(addr); 384 return val; 385 } 386 387 static inline u64 eeh_readq(const volatile void __iomem *addr) 388 { 389 u64 val = in_le64(addr); 390 if (EEH_POSSIBLE_ERROR(val, u64)) 391 eeh_check_failure(addr); 392 return val; 393 } 394 395 static inline u16 eeh_readw_be(const volatile void __iomem *addr) 396 { 397 u16 val = in_be16(addr); 398 if (EEH_POSSIBLE_ERROR(val, u16)) 399 eeh_check_failure(addr); 400 return val; 401 } 402 403 static inline u32 eeh_readl_be(const volatile void __iomem *addr) 404 { 405 u32 val = in_be32(addr); 406 if (EEH_POSSIBLE_ERROR(val, u32)) 407 eeh_check_failure(addr); 408 return val; 409 } 410 411 static inline u64 eeh_readq_be(const volatile void __iomem *addr) 412 { 413 u64 val = in_be64(addr); 414 if (EEH_POSSIBLE_ERROR(val, u64)) 415 eeh_check_failure(addr); 416 return val; 417 } 418 419 static inline void eeh_memcpy_fromio(void *dest, const 420 volatile void __iomem *src, 421 unsigned long n) 422 { 423 _memcpy_fromio(dest, src, n); 424 425 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes 426 * were copied. Check all four bytes. 427 */ 428 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32)) 429 eeh_check_failure(src); 430 } 431 432 /* in-string eeh macros */ 433 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf, 434 int ns) 435 { 436 _insb(addr, buf, ns); 437 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8)) 438 eeh_check_failure(addr); 439 } 440 441 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf, 442 int ns) 443 { 444 _insw(addr, buf, ns); 445 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16)) 446 eeh_check_failure(addr); 447 } 448 449 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf, 450 int nl) 451 { 452 _insl(addr, buf, nl); 453 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32)) 454 eeh_check_failure(addr); 455 } 456 457 #endif /* CONFIG_PPC64 */ 458 #endif /* __KERNEL__ */ 459 #endif /* _POWERPC_EEH_H */ 460