1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation. 4 * Copyright 2001-2012 IBM Corporation. 5 */ 6 7 #ifndef _POWERPC_EEH_H 8 #define _POWERPC_EEH_H 9 #ifdef __KERNEL__ 10 11 #include <linux/init.h> 12 #include <linux/list.h> 13 #include <linux/string.h> 14 #include <linux/time.h> 15 #include <linux/atomic.h> 16 17 #include <uapi/asm/eeh.h> 18 19 struct pci_dev; 20 struct pci_bus; 21 struct pci_dn; 22 23 #ifdef CONFIG_EEH 24 25 /* EEH subsystem flags */ 26 #define EEH_ENABLED 0x01 /* EEH enabled */ 27 #define EEH_FORCE_DISABLED 0x02 /* EEH disabled */ 28 #define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */ 29 #define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */ 30 #define EEH_VALID_PE_ZERO 0x10 /* PE#0 is valid */ 31 #define EEH_ENABLE_IO_FOR_LOG 0x20 /* Enable IO for log */ 32 #define EEH_EARLY_DUMP_LOG 0x40 /* Dump log immediately */ 33 34 /* 35 * Delay for PE reset, all in ms 36 * 37 * PCI specification has reset hold time of 100 milliseconds. 38 * We have 250 milliseconds here. The PCI bus settlement time 39 * is specified as 1.5 seconds and we have 1.8 seconds. 40 */ 41 #define EEH_PE_RST_HOLD_TIME 250 42 #define EEH_PE_RST_SETTLE_TIME 1800 43 44 /* 45 * The struct is used to trace PE related EEH functionality. 46 * In theory, there will have one instance of the struct to 47 * be created against particular PE. In nature, PEs correlate 48 * to each other. the struct has to reflect that hierarchy in 49 * order to easily pick up those affected PEs when one particular 50 * PE has EEH errors. 51 * 52 * Also, one particular PE might be composed of PCI device, PCI 53 * bus and its subordinate components. The struct also need ship 54 * the information. Further more, one particular PE is only meaingful 55 * in the corresponding PHB. Therefore, the root PEs should be created 56 * against existing PHBs in on-to-one fashion. 57 */ 58 #define EEH_PE_INVALID (1 << 0) /* Invalid */ 59 #define EEH_PE_PHB (1 << 1) /* PHB PE */ 60 #define EEH_PE_DEVICE (1 << 2) /* Device PE */ 61 #define EEH_PE_BUS (1 << 3) /* Bus PE */ 62 #define EEH_PE_VF (1 << 4) /* VF PE */ 63 64 #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */ 65 #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */ 66 #define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */ 67 #define EEH_PE_RESET (1 << 3) /* PE reset in progress */ 68 69 #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ 70 #define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */ 71 #define EEH_PE_REMOVED (1 << 10) /* Removed permanently */ 72 #define EEH_PE_PRI_BUS (1 << 11) /* Cached primary bus */ 73 74 struct eeh_pe { 75 int type; /* PE type: PHB/Bus/Device */ 76 int state; /* PE EEH dependent mode */ 77 int config_addr; /* Traditional PCI address */ 78 int addr; /* PE configuration address */ 79 struct pci_controller *phb; /* Associated PHB */ 80 struct pci_bus *bus; /* Top PCI bus for bus PE */ 81 int check_count; /* Times of ignored error */ 82 int freeze_count; /* Times of froze up */ 83 time64_t tstamp; /* Time on first-time freeze */ 84 int false_positives; /* Times of reported #ff's */ 85 atomic_t pass_dev_cnt; /* Count of passed through devs */ 86 struct eeh_pe *parent; /* Parent PE */ 87 void *data; /* PE auxillary data */ 88 struct list_head child_list; /* List of PEs below this PE */ 89 struct list_head child; /* Memb. child_list/eeh_phb_pe */ 90 struct list_head edevs; /* List of eeh_dev in this PE */ 91 92 #ifdef CONFIG_STACKTRACE 93 /* 94 * Saved stack trace. When we find a PE freeze in eeh_dev_check_failure 95 * the stack trace is saved here so we can print it in the recovery 96 * thread if it turns out to due to a real problem rather than 97 * a hot-remove. 98 * 99 * A max of 64 entries might be overkill, but it also might not be. 100 */ 101 unsigned long stack_trace[64]; 102 int trace_entries; 103 #endif /* CONFIG_STACKTRACE */ 104 }; 105 106 #define eeh_pe_for_each_dev(pe, edev, tmp) \ 107 list_for_each_entry_safe(edev, tmp, &pe->edevs, entry) 108 109 #define eeh_for_each_pe(root, pe) \ 110 for (pe = root; pe; pe = eeh_pe_next(pe, root)) 111 112 static inline bool eeh_pe_passed(struct eeh_pe *pe) 113 { 114 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false; 115 } 116 117 /* 118 * The struct is used to trace EEH state for the associated 119 * PCI device node or PCI device. In future, it might 120 * represent PE as well so that the EEH device to form 121 * another tree except the currently existing tree of PCI 122 * buses and PCI devices 123 */ 124 #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */ 125 #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */ 126 #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */ 127 #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */ 128 #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */ 129 130 #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */ 131 #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */ 132 #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */ 133 134 struct eeh_dev { 135 int mode; /* EEH mode */ 136 int bdfn; /* bdfn of device (for cfg ops) */ 137 struct pci_controller *controller; 138 int pe_config_addr; /* PE config address */ 139 u32 config_space[16]; /* Saved PCI config space */ 140 int pcix_cap; /* Saved PCIx capability */ 141 int pcie_cap; /* Saved PCIe capability */ 142 int aer_cap; /* Saved AER capability */ 143 int af_cap; /* Saved AF capability */ 144 struct eeh_pe *pe; /* Associated PE */ 145 struct list_head entry; /* Membership in eeh_pe.edevs */ 146 struct list_head rmv_entry; /* Membership in rmv_list */ 147 struct pci_dn *pdn; /* Associated PCI device node */ 148 struct pci_dev *pdev; /* Associated PCI device */ 149 bool in_error; /* Error flag for edev */ 150 151 /* VF specific properties */ 152 struct pci_dev *physfn; /* Associated SRIOV PF */ 153 int vf_index; /* Index of this VF */ 154 }; 155 156 /* "fmt" must be a simple literal string */ 157 #define EEH_EDEV_PRINT(level, edev, fmt, ...) \ 158 pr_##level("PCI %04x:%02x:%02x.%x#%04x: EEH: " fmt, \ 159 (edev)->controller->global_number, PCI_BUSNO((edev)->bdfn), \ 160 PCI_SLOT((edev)->bdfn), PCI_FUNC((edev)->bdfn), \ 161 ((edev)->pe ? (edev)->pe_config_addr : 0xffff), ##__VA_ARGS__) 162 #define eeh_edev_dbg(edev, fmt, ...) EEH_EDEV_PRINT(debug, (edev), fmt, ##__VA_ARGS__) 163 #define eeh_edev_info(edev, fmt, ...) EEH_EDEV_PRINT(info, (edev), fmt, ##__VA_ARGS__) 164 #define eeh_edev_warn(edev, fmt, ...) EEH_EDEV_PRINT(warn, (edev), fmt, ##__VA_ARGS__) 165 #define eeh_edev_err(edev, fmt, ...) EEH_EDEV_PRINT(err, (edev), fmt, ##__VA_ARGS__) 166 167 static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev) 168 { 169 return edev ? edev->pdn : NULL; 170 } 171 172 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev) 173 { 174 return edev ? edev->pdev : NULL; 175 } 176 177 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev) 178 { 179 return edev ? edev->pe : NULL; 180 } 181 182 /* Return values from eeh_ops::next_error */ 183 enum { 184 EEH_NEXT_ERR_NONE = 0, 185 EEH_NEXT_ERR_INF, 186 EEH_NEXT_ERR_FROZEN_PE, 187 EEH_NEXT_ERR_FENCED_PHB, 188 EEH_NEXT_ERR_DEAD_PHB, 189 EEH_NEXT_ERR_DEAD_IOC 190 }; 191 192 /* 193 * The struct is used to trace the registered EEH operation 194 * callback functions. Actually, those operation callback 195 * functions are heavily platform dependent. That means the 196 * platform should register its own EEH operation callback 197 * functions before any EEH further operations. 198 */ 199 #define EEH_OPT_DISABLE 0 /* EEH disable */ 200 #define EEH_OPT_ENABLE 1 /* EEH enable */ 201 #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */ 202 #define EEH_OPT_THAW_DMA 3 /* DMA enable */ 203 #define EEH_OPT_FREEZE_PE 4 /* Freeze PE */ 204 #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */ 205 #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */ 206 #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */ 207 #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */ 208 #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */ 209 #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */ 210 #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */ 211 #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */ 212 #define EEH_RESET_HOT 1 /* Hot reset */ 213 #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */ 214 #define EEH_LOG_TEMP 1 /* EEH temporary error log */ 215 #define EEH_LOG_PERM 2 /* EEH permanent error log */ 216 217 struct eeh_ops { 218 char *name; 219 int (*init)(void); 220 struct eeh_dev *(*probe)(struct pci_dev *pdev); 221 int (*set_option)(struct eeh_pe *pe, int option); 222 int (*get_state)(struct eeh_pe *pe, int *delay); 223 int (*reset)(struct eeh_pe *pe, int option); 224 int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len); 225 int (*configure_bridge)(struct eeh_pe *pe); 226 int (*err_inject)(struct eeh_pe *pe, int type, int func, 227 unsigned long addr, unsigned long mask); 228 int (*read_config)(struct eeh_dev *edev, int where, int size, u32 *val); 229 int (*write_config)(struct eeh_dev *edev, int where, int size, u32 val); 230 int (*next_error)(struct eeh_pe **pe); 231 int (*restore_config)(struct eeh_dev *edev); 232 int (*notify_resume)(struct eeh_dev *edev); 233 }; 234 235 extern int eeh_subsystem_flags; 236 extern u32 eeh_max_freezes; 237 extern bool eeh_debugfs_no_recover; 238 extern struct eeh_ops *eeh_ops; 239 extern raw_spinlock_t confirm_error_lock; 240 241 static inline void eeh_add_flag(int flag) 242 { 243 eeh_subsystem_flags |= flag; 244 } 245 246 static inline void eeh_clear_flag(int flag) 247 { 248 eeh_subsystem_flags &= ~flag; 249 } 250 251 static inline bool eeh_has_flag(int flag) 252 { 253 return !!(eeh_subsystem_flags & flag); 254 } 255 256 static inline bool eeh_enabled(void) 257 { 258 return eeh_has_flag(EEH_ENABLED) && !eeh_has_flag(EEH_FORCE_DISABLED); 259 } 260 261 static inline void eeh_serialize_lock(unsigned long *flags) 262 { 263 raw_spin_lock_irqsave(&confirm_error_lock, *flags); 264 } 265 266 static inline void eeh_serialize_unlock(unsigned long flags) 267 { 268 raw_spin_unlock_irqrestore(&confirm_error_lock, flags); 269 } 270 271 static inline bool eeh_state_active(int state) 272 { 273 return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) 274 == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 275 } 276 277 typedef void (*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag); 278 typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag); 279 void eeh_set_pe_aux_size(int size); 280 int eeh_phb_pe_create(struct pci_controller *phb); 281 int eeh_wait_state(struct eeh_pe *pe, int max_wait); 282 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb); 283 struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root); 284 struct eeh_pe *eeh_pe_get(struct pci_controller *phb, 285 int pe_no, int config_addr); 286 int eeh_pe_tree_insert(struct eeh_dev *edev, struct eeh_pe *new_pe_parent); 287 int eeh_pe_tree_remove(struct eeh_dev *edev); 288 void eeh_pe_update_time_stamp(struct eeh_pe *pe); 289 void *eeh_pe_traverse(struct eeh_pe *root, 290 eeh_pe_traverse_func fn, void *flag); 291 void eeh_pe_dev_traverse(struct eeh_pe *root, 292 eeh_edev_traverse_func fn, void *flag); 293 void eeh_pe_restore_bars(struct eeh_pe *pe); 294 const char *eeh_pe_loc_get(struct eeh_pe *pe); 295 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe); 296 297 void eeh_show_enabled(void); 298 int __init eeh_ops_register(struct eeh_ops *ops); 299 int __exit eeh_ops_unregister(const char *name); 300 int eeh_check_failure(const volatile void __iomem *token); 301 int eeh_dev_check_failure(struct eeh_dev *edev); 302 void eeh_addr_cache_init(void); 303 void eeh_probe_device(struct pci_dev *pdev); 304 void eeh_remove_device(struct pci_dev *); 305 int eeh_unfreeze_pe(struct eeh_pe *pe); 306 int eeh_pe_reset_and_recover(struct eeh_pe *pe); 307 int eeh_dev_open(struct pci_dev *pdev); 308 void eeh_dev_release(struct pci_dev *pdev); 309 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group); 310 int eeh_pe_set_option(struct eeh_pe *pe, int option); 311 int eeh_pe_get_state(struct eeh_pe *pe); 312 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed); 313 int eeh_pe_configure(struct eeh_pe *pe); 314 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func, 315 unsigned long addr, unsigned long mask); 316 317 /** 318 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure. 319 * 320 * If this macro yields TRUE, the caller relays to eeh_check_failure() 321 * which does further tests out of line. 322 */ 323 #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled()) 324 325 /* 326 * Reads from a device which has been isolated by EEH will return 327 * all 1s. This macro gives an all-1s value of the given size (in 328 * bytes: 1, 2, or 4) for comparing with the result of a read. 329 */ 330 #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8)) 331 332 #else /* !CONFIG_EEH */ 333 334 static inline bool eeh_enabled(void) 335 { 336 return false; 337 } 338 339 static inline void eeh_show_enabled(void) { } 340 341 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { } 342 343 static inline int eeh_check_failure(const volatile void __iomem *token) 344 { 345 return 0; 346 } 347 348 #define eeh_dev_check_failure(x) (0) 349 350 static inline void eeh_addr_cache_init(void) { } 351 352 static inline void eeh_probe_device(struct pci_dev *dev) { } 353 354 static inline void eeh_remove_device(struct pci_dev *dev) { } 355 356 #define EEH_POSSIBLE_ERROR(val, type) (0) 357 #define EEH_IO_ERROR_VALUE(size) (-1UL) 358 static inline int eeh_phb_pe_create(struct pci_controller *phb) { return 0; } 359 #endif /* CONFIG_EEH */ 360 361 #if defined(CONFIG_PPC_PSERIES) && defined(CONFIG_EEH) 362 void pseries_eeh_init_edev(struct pci_dn *pdn); 363 void pseries_eeh_init_edev_recursive(struct pci_dn *pdn); 364 #else 365 static inline void pseries_eeh_add_device_early(struct pci_dn *pdn) { } 366 static inline void pseries_eeh_add_device_tree_early(struct pci_dn *pdn) { } 367 #endif 368 369 #ifdef CONFIG_PPC64 370 /* 371 * MMIO read/write operations with EEH support. 372 */ 373 static inline u8 eeh_readb(const volatile void __iomem *addr) 374 { 375 u8 val = in_8(addr); 376 if (EEH_POSSIBLE_ERROR(val, u8)) 377 eeh_check_failure(addr); 378 return val; 379 } 380 381 static inline u16 eeh_readw(const volatile void __iomem *addr) 382 { 383 u16 val = in_le16(addr); 384 if (EEH_POSSIBLE_ERROR(val, u16)) 385 eeh_check_failure(addr); 386 return val; 387 } 388 389 static inline u32 eeh_readl(const volatile void __iomem *addr) 390 { 391 u32 val = in_le32(addr); 392 if (EEH_POSSIBLE_ERROR(val, u32)) 393 eeh_check_failure(addr); 394 return val; 395 } 396 397 static inline u64 eeh_readq(const volatile void __iomem *addr) 398 { 399 u64 val = in_le64(addr); 400 if (EEH_POSSIBLE_ERROR(val, u64)) 401 eeh_check_failure(addr); 402 return val; 403 } 404 405 static inline u16 eeh_readw_be(const volatile void __iomem *addr) 406 { 407 u16 val = in_be16(addr); 408 if (EEH_POSSIBLE_ERROR(val, u16)) 409 eeh_check_failure(addr); 410 return val; 411 } 412 413 static inline u32 eeh_readl_be(const volatile void __iomem *addr) 414 { 415 u32 val = in_be32(addr); 416 if (EEH_POSSIBLE_ERROR(val, u32)) 417 eeh_check_failure(addr); 418 return val; 419 } 420 421 static inline u64 eeh_readq_be(const volatile void __iomem *addr) 422 { 423 u64 val = in_be64(addr); 424 if (EEH_POSSIBLE_ERROR(val, u64)) 425 eeh_check_failure(addr); 426 return val; 427 } 428 429 static inline void eeh_memcpy_fromio(void *dest, const 430 volatile void __iomem *src, 431 unsigned long n) 432 { 433 _memcpy_fromio(dest, src, n); 434 435 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes 436 * were copied. Check all four bytes. 437 */ 438 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32)) 439 eeh_check_failure(src); 440 } 441 442 /* in-string eeh macros */ 443 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf, 444 int ns) 445 { 446 _insb(addr, buf, ns); 447 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8)) 448 eeh_check_failure(addr); 449 } 450 451 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf, 452 int ns) 453 { 454 _insw(addr, buf, ns); 455 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16)) 456 eeh_check_failure(addr); 457 } 458 459 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf, 460 int nl) 461 { 462 _insl(addr, buf, nl); 463 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32)) 464 eeh_check_failure(addr); 465 } 466 467 468 void eeh_cache_debugfs_init(void); 469 470 #endif /* CONFIG_PPC64 */ 471 #endif /* __KERNEL__ */ 472 #endif /* _POWERPC_EEH_H */ 473