1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation. 4 * Copyright 2001-2012 IBM Corporation. 5 */ 6 7 #ifndef _POWERPC_EEH_H 8 #define _POWERPC_EEH_H 9 #ifdef __KERNEL__ 10 11 #include <linux/init.h> 12 #include <linux/list.h> 13 #include <linux/string.h> 14 #include <linux/time.h> 15 #include <linux/atomic.h> 16 17 #include <uapi/asm/eeh.h> 18 19 struct pci_dev; 20 struct pci_bus; 21 struct pci_dn; 22 23 #ifdef CONFIG_EEH 24 25 /* EEH subsystem flags */ 26 #define EEH_ENABLED 0x01 /* EEH enabled */ 27 #define EEH_FORCE_DISABLED 0x02 /* EEH disabled */ 28 #define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */ 29 #define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */ 30 #define EEH_ENABLE_IO_FOR_LOG 0x20 /* Enable IO for log */ 31 #define EEH_EARLY_DUMP_LOG 0x40 /* Dump log immediately */ 32 33 /* 34 * Delay for PE reset, all in ms 35 * 36 * PCI specification has reset hold time of 100 milliseconds. 37 * We have 250 milliseconds here. The PCI bus settlement time 38 * is specified as 1.5 seconds and we have 1.8 seconds. 39 */ 40 #define EEH_PE_RST_HOLD_TIME 250 41 #define EEH_PE_RST_SETTLE_TIME 1800 42 43 /* 44 * The struct is used to trace PE related EEH functionality. 45 * In theory, there will have one instance of the struct to 46 * be created against particular PE. In nature, PEs correlate 47 * to each other. the struct has to reflect that hierarchy in 48 * order to easily pick up those affected PEs when one particular 49 * PE has EEH errors. 50 * 51 * Also, one particular PE might be composed of PCI device, PCI 52 * bus and its subordinate components. The struct also need ship 53 * the information. Further more, one particular PE is only meaingful 54 * in the corresponding PHB. Therefore, the root PEs should be created 55 * against existing PHBs in on-to-one fashion. 56 */ 57 #define EEH_PE_INVALID (1 << 0) /* Invalid */ 58 #define EEH_PE_PHB (1 << 1) /* PHB PE */ 59 #define EEH_PE_DEVICE (1 << 2) /* Device PE */ 60 #define EEH_PE_BUS (1 << 3) /* Bus PE */ 61 #define EEH_PE_VF (1 << 4) /* VF PE */ 62 63 #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */ 64 #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */ 65 #define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */ 66 #define EEH_PE_RESET (1 << 3) /* PE reset in progress */ 67 68 #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ 69 #define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */ 70 #define EEH_PE_REMOVED (1 << 10) /* Removed permanently */ 71 #define EEH_PE_PRI_BUS (1 << 11) /* Cached primary bus */ 72 73 struct eeh_pe { 74 int type; /* PE type: PHB/Bus/Device */ 75 int state; /* PE EEH dependent mode */ 76 int addr; /* PE configuration address */ 77 struct pci_controller *phb; /* Associated PHB */ 78 struct pci_bus *bus; /* Top PCI bus for bus PE */ 79 int check_count; /* Times of ignored error */ 80 int freeze_count; /* Times of froze up */ 81 time64_t tstamp; /* Time on first-time freeze */ 82 int false_positives; /* Times of reported #ff's */ 83 atomic_t pass_dev_cnt; /* Count of passed through devs */ 84 struct eeh_pe *parent; /* Parent PE */ 85 void *data; /* PE auxillary data */ 86 struct list_head child_list; /* List of PEs below this PE */ 87 struct list_head child; /* Memb. child_list/eeh_phb_pe */ 88 struct list_head edevs; /* List of eeh_dev in this PE */ 89 90 #ifdef CONFIG_STACKTRACE 91 /* 92 * Saved stack trace. When we find a PE freeze in eeh_dev_check_failure 93 * the stack trace is saved here so we can print it in the recovery 94 * thread if it turns out to due to a real problem rather than 95 * a hot-remove. 96 * 97 * A max of 64 entries might be overkill, but it also might not be. 98 */ 99 unsigned long stack_trace[64]; 100 int trace_entries; 101 #endif /* CONFIG_STACKTRACE */ 102 }; 103 104 #define eeh_pe_for_each_dev(pe, edev, tmp) \ 105 list_for_each_entry_safe(edev, tmp, &pe->edevs, entry) 106 107 #define eeh_for_each_pe(root, pe) \ 108 for (pe = root; pe; pe = eeh_pe_next(pe, root)) 109 110 static inline bool eeh_pe_passed(struct eeh_pe *pe) 111 { 112 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false; 113 } 114 115 /* 116 * The struct is used to trace EEH state for the associated 117 * PCI device node or PCI device. In future, it might 118 * represent PE as well so that the EEH device to form 119 * another tree except the currently existing tree of PCI 120 * buses and PCI devices 121 */ 122 #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */ 123 #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */ 124 #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */ 125 #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */ 126 #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */ 127 128 #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */ 129 #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */ 130 #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */ 131 132 struct eeh_dev { 133 int mode; /* EEH mode */ 134 int bdfn; /* bdfn of device (for cfg ops) */ 135 struct pci_controller *controller; 136 int pe_config_addr; /* PE config address */ 137 u32 config_space[16]; /* Saved PCI config space */ 138 int pcix_cap; /* Saved PCIx capability */ 139 int pcie_cap; /* Saved PCIe capability */ 140 int aer_cap; /* Saved AER capability */ 141 int af_cap; /* Saved AF capability */ 142 struct eeh_pe *pe; /* Associated PE */ 143 struct list_head entry; /* Membership in eeh_pe.edevs */ 144 struct list_head rmv_entry; /* Membership in rmv_list */ 145 struct pci_dn *pdn; /* Associated PCI device node */ 146 struct pci_dev *pdev; /* Associated PCI device */ 147 bool in_error; /* Error flag for edev */ 148 149 /* VF specific properties */ 150 struct pci_dev *physfn; /* Associated SRIOV PF */ 151 int vf_index; /* Index of this VF */ 152 }; 153 154 /* "fmt" must be a simple literal string */ 155 #define EEH_EDEV_PRINT(level, edev, fmt, ...) \ 156 pr_##level("PCI %04x:%02x:%02x.%x#%04x: EEH: " fmt, \ 157 (edev)->controller->global_number, PCI_BUSNO((edev)->bdfn), \ 158 PCI_SLOT((edev)->bdfn), PCI_FUNC((edev)->bdfn), \ 159 ((edev)->pe ? (edev)->pe_config_addr : 0xffff), ##__VA_ARGS__) 160 #define eeh_edev_dbg(edev, fmt, ...) EEH_EDEV_PRINT(debug, (edev), fmt, ##__VA_ARGS__) 161 #define eeh_edev_info(edev, fmt, ...) EEH_EDEV_PRINT(info, (edev), fmt, ##__VA_ARGS__) 162 #define eeh_edev_warn(edev, fmt, ...) EEH_EDEV_PRINT(warn, (edev), fmt, ##__VA_ARGS__) 163 #define eeh_edev_err(edev, fmt, ...) EEH_EDEV_PRINT(err, (edev), fmt, ##__VA_ARGS__) 164 165 static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev) 166 { 167 return edev ? edev->pdn : NULL; 168 } 169 170 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev) 171 { 172 return edev ? edev->pdev : NULL; 173 } 174 175 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev) 176 { 177 return edev ? edev->pe : NULL; 178 } 179 180 /* Return values from eeh_ops::next_error */ 181 enum { 182 EEH_NEXT_ERR_NONE = 0, 183 EEH_NEXT_ERR_INF, 184 EEH_NEXT_ERR_FROZEN_PE, 185 EEH_NEXT_ERR_FENCED_PHB, 186 EEH_NEXT_ERR_DEAD_PHB, 187 EEH_NEXT_ERR_DEAD_IOC 188 }; 189 190 /* 191 * The struct is used to trace the registered EEH operation 192 * callback functions. Actually, those operation callback 193 * functions are heavily platform dependent. That means the 194 * platform should register its own EEH operation callback 195 * functions before any EEH further operations. 196 */ 197 #define EEH_OPT_DISABLE 0 /* EEH disable */ 198 #define EEH_OPT_ENABLE 1 /* EEH enable */ 199 #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */ 200 #define EEH_OPT_THAW_DMA 3 /* DMA enable */ 201 #define EEH_OPT_FREEZE_PE 4 /* Freeze PE */ 202 #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */ 203 #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */ 204 #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */ 205 #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */ 206 #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */ 207 #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */ 208 #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */ 209 #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */ 210 #define EEH_RESET_HOT 1 /* Hot reset */ 211 #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */ 212 #define EEH_LOG_TEMP 1 /* EEH temporary error log */ 213 #define EEH_LOG_PERM 2 /* EEH permanent error log */ 214 215 struct eeh_ops { 216 char *name; 217 struct eeh_dev *(*probe)(struct pci_dev *pdev); 218 int (*set_option)(struct eeh_pe *pe, int option); 219 int (*get_state)(struct eeh_pe *pe, int *delay); 220 int (*reset)(struct eeh_pe *pe, int option); 221 int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len); 222 int (*configure_bridge)(struct eeh_pe *pe); 223 int (*err_inject)(struct eeh_pe *pe, int type, int func, 224 unsigned long addr, unsigned long mask); 225 int (*read_config)(struct eeh_dev *edev, int where, int size, u32 *val); 226 int (*write_config)(struct eeh_dev *edev, int where, int size, u32 val); 227 int (*next_error)(struct eeh_pe **pe); 228 int (*restore_config)(struct eeh_dev *edev); 229 int (*notify_resume)(struct eeh_dev *edev); 230 }; 231 232 extern int eeh_subsystem_flags; 233 extern u32 eeh_max_freezes; 234 extern bool eeh_debugfs_no_recover; 235 extern struct eeh_ops *eeh_ops; 236 extern raw_spinlock_t confirm_error_lock; 237 238 static inline void eeh_add_flag(int flag) 239 { 240 eeh_subsystem_flags |= flag; 241 } 242 243 static inline void eeh_clear_flag(int flag) 244 { 245 eeh_subsystem_flags &= ~flag; 246 } 247 248 static inline bool eeh_has_flag(int flag) 249 { 250 return !!(eeh_subsystem_flags & flag); 251 } 252 253 static inline bool eeh_enabled(void) 254 { 255 return eeh_has_flag(EEH_ENABLED) && !eeh_has_flag(EEH_FORCE_DISABLED); 256 } 257 258 static inline void eeh_serialize_lock(unsigned long *flags) 259 { 260 raw_spin_lock_irqsave(&confirm_error_lock, *flags); 261 } 262 263 static inline void eeh_serialize_unlock(unsigned long flags) 264 { 265 raw_spin_unlock_irqrestore(&confirm_error_lock, flags); 266 } 267 268 static inline bool eeh_state_active(int state) 269 { 270 return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) 271 == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 272 } 273 274 typedef void (*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag); 275 typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag); 276 void eeh_set_pe_aux_size(int size); 277 int eeh_phb_pe_create(struct pci_controller *phb); 278 int eeh_wait_state(struct eeh_pe *pe, int max_wait); 279 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb); 280 struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root); 281 struct eeh_pe *eeh_pe_get(struct pci_controller *phb, int pe_no); 282 int eeh_pe_tree_insert(struct eeh_dev *edev, struct eeh_pe *new_pe_parent); 283 int eeh_pe_tree_remove(struct eeh_dev *edev); 284 void eeh_pe_update_time_stamp(struct eeh_pe *pe); 285 void *eeh_pe_traverse(struct eeh_pe *root, 286 eeh_pe_traverse_func fn, void *flag); 287 void eeh_pe_dev_traverse(struct eeh_pe *root, 288 eeh_edev_traverse_func fn, void *flag); 289 void eeh_pe_restore_bars(struct eeh_pe *pe); 290 const char *eeh_pe_loc_get(struct eeh_pe *pe); 291 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe); 292 293 void eeh_show_enabled(void); 294 int __init eeh_init(struct eeh_ops *ops); 295 int eeh_check_failure(const volatile void __iomem *token); 296 int eeh_dev_check_failure(struct eeh_dev *edev); 297 void eeh_addr_cache_init(void); 298 void eeh_probe_device(struct pci_dev *pdev); 299 void eeh_remove_device(struct pci_dev *); 300 int eeh_unfreeze_pe(struct eeh_pe *pe); 301 int eeh_pe_reset_and_recover(struct eeh_pe *pe); 302 int eeh_dev_open(struct pci_dev *pdev); 303 void eeh_dev_release(struct pci_dev *pdev); 304 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group); 305 int eeh_pe_set_option(struct eeh_pe *pe, int option); 306 int eeh_pe_get_state(struct eeh_pe *pe); 307 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed); 308 int eeh_pe_configure(struct eeh_pe *pe); 309 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func, 310 unsigned long addr, unsigned long mask); 311 312 /** 313 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure. 314 * 315 * If this macro yields TRUE, the caller relays to eeh_check_failure() 316 * which does further tests out of line. 317 */ 318 #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled()) 319 320 /* 321 * Reads from a device which has been isolated by EEH will return 322 * all 1s. This macro gives an all-1s value of the given size (in 323 * bytes: 1, 2, or 4) for comparing with the result of a read. 324 */ 325 #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8)) 326 327 #else /* !CONFIG_EEH */ 328 329 static inline bool eeh_enabled(void) 330 { 331 return false; 332 } 333 334 static inline void eeh_show_enabled(void) { } 335 336 static inline int eeh_check_failure(const volatile void __iomem *token) 337 { 338 return 0; 339 } 340 341 #define eeh_dev_check_failure(x) (0) 342 343 static inline void eeh_addr_cache_init(void) { } 344 345 static inline void eeh_probe_device(struct pci_dev *dev) { } 346 347 static inline void eeh_remove_device(struct pci_dev *dev) { } 348 349 #define EEH_POSSIBLE_ERROR(val, type) (0) 350 #define EEH_IO_ERROR_VALUE(size) (-1UL) 351 static inline int eeh_phb_pe_create(struct pci_controller *phb) { return 0; } 352 #endif /* CONFIG_EEH */ 353 354 #if defined(CONFIG_PPC_PSERIES) && defined(CONFIG_EEH) 355 void pseries_eeh_init_edev_recursive(struct pci_dn *pdn); 356 #endif 357 358 #ifdef CONFIG_PPC64 359 /* 360 * MMIO read/write operations with EEH support. 361 */ 362 static inline u8 eeh_readb(const volatile void __iomem *addr) 363 { 364 u8 val = in_8(addr); 365 if (EEH_POSSIBLE_ERROR(val, u8)) 366 eeh_check_failure(addr); 367 return val; 368 } 369 370 static inline u16 eeh_readw(const volatile void __iomem *addr) 371 { 372 u16 val = in_le16(addr); 373 if (EEH_POSSIBLE_ERROR(val, u16)) 374 eeh_check_failure(addr); 375 return val; 376 } 377 378 static inline u32 eeh_readl(const volatile void __iomem *addr) 379 { 380 u32 val = in_le32(addr); 381 if (EEH_POSSIBLE_ERROR(val, u32)) 382 eeh_check_failure(addr); 383 return val; 384 } 385 386 static inline u64 eeh_readq(const volatile void __iomem *addr) 387 { 388 u64 val = in_le64(addr); 389 if (EEH_POSSIBLE_ERROR(val, u64)) 390 eeh_check_failure(addr); 391 return val; 392 } 393 394 static inline u16 eeh_readw_be(const volatile void __iomem *addr) 395 { 396 u16 val = in_be16(addr); 397 if (EEH_POSSIBLE_ERROR(val, u16)) 398 eeh_check_failure(addr); 399 return val; 400 } 401 402 static inline u32 eeh_readl_be(const volatile void __iomem *addr) 403 { 404 u32 val = in_be32(addr); 405 if (EEH_POSSIBLE_ERROR(val, u32)) 406 eeh_check_failure(addr); 407 return val; 408 } 409 410 static inline u64 eeh_readq_be(const volatile void __iomem *addr) 411 { 412 u64 val = in_be64(addr); 413 if (EEH_POSSIBLE_ERROR(val, u64)) 414 eeh_check_failure(addr); 415 return val; 416 } 417 418 static inline void eeh_memcpy_fromio(void *dest, const 419 volatile void __iomem *src, 420 unsigned long n) 421 { 422 _memcpy_fromio(dest, src, n); 423 424 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes 425 * were copied. Check all four bytes. 426 */ 427 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32)) 428 eeh_check_failure(src); 429 } 430 431 /* in-string eeh macros */ 432 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf, 433 int ns) 434 { 435 _insb(addr, buf, ns); 436 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8)) 437 eeh_check_failure(addr); 438 } 439 440 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf, 441 int ns) 442 { 443 _insw(addr, buf, ns); 444 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16)) 445 eeh_check_failure(addr); 446 } 447 448 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf, 449 int nl) 450 { 451 _insl(addr, buf, nl); 452 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32)) 453 eeh_check_failure(addr); 454 } 455 456 457 void __init eeh_cache_debugfs_init(void); 458 459 #endif /* CONFIG_PPC64 */ 460 #endif /* __KERNEL__ */ 461 #endif /* _POWERPC_EEH_H */ 462