11a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2b8b572e1SStephen Rothwell /*
3b8b572e1SStephen Rothwell * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
4cb3bc9d0SGavin Shan * Copyright 2001-2012 IBM Corporation.
5b8b572e1SStephen Rothwell */
6b8b572e1SStephen Rothwell
78b8da358SBenjamin Herrenschmidt #ifndef _POWERPC_EEH_H
88b8da358SBenjamin Herrenschmidt #define _POWERPC_EEH_H
9b8b572e1SStephen Rothwell #ifdef __KERNEL__
10b8b572e1SStephen Rothwell
11b8b572e1SStephen Rothwell #include <linux/init.h>
12b8b572e1SStephen Rothwell #include <linux/list.h>
13b8b572e1SStephen Rothwell #include <linux/string.h>
145a71978eSGavin Shan #include <linux/time.h>
1505ec424eSGavin Shan #include <linux/atomic.h>
16b8b572e1SStephen Rothwell
17ed3e81ffSGavin Shan #include <uapi/asm/eeh.h>
18ed3e81ffSGavin Shan
19b8b572e1SStephen Rothwell struct pci_dev;
20b8b572e1SStephen Rothwell struct pci_bus;
21e8e9b34cSGavin Shan struct pci_dn;
22b8b572e1SStephen Rothwell
23b8b572e1SStephen Rothwell #ifdef CONFIG_EEH
24b8b572e1SStephen Rothwell
258a5ad356SGavin Shan /* EEH subsystem flags */
26dc561fb9SGavin Shan #define EEH_ENABLED 0x01 /* EEH enabled */
27dc561fb9SGavin Shan #define EEH_FORCE_DISABLED 0x02 /* EEH disabled */
28dc561fb9SGavin Shan #define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */
29dc561fb9SGavin Shan #define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */
302aa5cf9eSGavin Shan #define EEH_ENABLE_IO_FOR_LOG 0x20 /* Enable IO for log */
312aa5cf9eSGavin Shan #define EEH_EARLY_DUMP_LOG 0x40 /* Dump log immediately */
328a5ad356SGavin Shan
33aa1e6374SGavin Shan /*
3426833a50SGavin Shan * Delay for PE reset, all in ms
3526833a50SGavin Shan *
3626833a50SGavin Shan * PCI specification has reset hold time of 100 milliseconds.
3726833a50SGavin Shan * We have 250 milliseconds here. The PCI bus settlement time
3826833a50SGavin Shan * is specified as 1.5 seconds and we have 1.8 seconds.
3926833a50SGavin Shan */
4026833a50SGavin Shan #define EEH_PE_RST_HOLD_TIME 250
4126833a50SGavin Shan #define EEH_PE_RST_SETTLE_TIME 1800
4226833a50SGavin Shan
4326833a50SGavin Shan /*
44968f968fSGavin Shan * The struct is used to trace PE related EEH functionality.
45968f968fSGavin Shan * In theory, there will have one instance of the struct to
46027dfac6SMichael Ellerman * be created against particular PE. In nature, PEs correlate
47968f968fSGavin Shan * to each other. the struct has to reflect that hierarchy in
48968f968fSGavin Shan * order to easily pick up those affected PEs when one particular
49968f968fSGavin Shan * PE has EEH errors.
50968f968fSGavin Shan *
51968f968fSGavin Shan * Also, one particular PE might be composed of PCI device, PCI
52968f968fSGavin Shan * bus and its subordinate components. The struct also need ship
53968f968fSGavin Shan * the information. Further more, one particular PE is only meaingful
54968f968fSGavin Shan * in the corresponding PHB. Therefore, the root PEs should be created
55968f968fSGavin Shan * against existing PHBs in on-to-one fashion.
56968f968fSGavin Shan */
575efc3ad7SGavin Shan #define EEH_PE_INVALID (1 << 0) /* Invalid */
585efc3ad7SGavin Shan #define EEH_PE_PHB (1 << 1) /* PHB PE */
595efc3ad7SGavin Shan #define EEH_PE_DEVICE (1 << 2) /* Device PE */
605efc3ad7SGavin Shan #define EEH_PE_BUS (1 << 3) /* Bus PE */
61c29fa27dSWei Yang #define EEH_PE_VF (1 << 4) /* VF PE */
62968f968fSGavin Shan
63968f968fSGavin Shan #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
64968f968fSGavin Shan #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
658a6b3710SGavin Shan #define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */
6628bf36f9SGavin Shan #define EEH_PE_RESET (1 << 3) /* PE reset in progress */
67968f968fSGavin Shan
68807a827dSGavin Shan #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
69b6541db1SGavin Shan #define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */
70432227e9SGavin Shan #define EEH_PE_REMOVED (1 << 10) /* Removed permanently */
7105ba75f8SGavin Shan #define EEH_PE_PRI_BUS (1 << 11) /* Cached primary bus */
72807a827dSGavin Shan
73968f968fSGavin Shan struct eeh_pe {
74968f968fSGavin Shan int type; /* PE type: PHB/Bus/Device */
75968f968fSGavin Shan int state; /* PE EEH dependent mode */
76968f968fSGavin Shan int addr; /* PE configuration address */
77968f968fSGavin Shan struct pci_controller *phb; /* Associated PHB */
788cdb2833SGavin Shan struct pci_bus *bus; /* Top PCI bus for bus PE */
79968f968fSGavin Shan int check_count; /* Times of ignored error */
80968f968fSGavin Shan int freeze_count; /* Times of froze up */
81edfd17ffSArnd Bergmann time64_t tstamp; /* Time on first-time freeze */
82968f968fSGavin Shan int false_positives; /* Times of reported #ff's */
8305ec424eSGavin Shan atomic_t pass_dev_cnt; /* Count of passed through devs */
84968f968fSGavin Shan struct eeh_pe *parent; /* Parent PE */
85bb593c00SGavin Shan void *data; /* PE auxillary data */
8680e65b00SSam Bobroff struct list_head child_list; /* List of PEs below this PE */
8780e65b00SSam Bobroff struct list_head child; /* Memb. child_list/eeh_phb_pe */
8880e65b00SSam Bobroff struct list_head edevs; /* List of eeh_dev in this PE */
8925baf3d8SOliver O'Halloran
901b7f3b6cSMichael Ellerman #ifdef CONFIG_STACKTRACE
9125baf3d8SOliver O'Halloran /*
9225baf3d8SOliver O'Halloran * Saved stack trace. When we find a PE freeze in eeh_dev_check_failure
9325baf3d8SOliver O'Halloran * the stack trace is saved here so we can print it in the recovery
9425baf3d8SOliver O'Halloran * thread if it turns out to due to a real problem rather than
9525baf3d8SOliver O'Halloran * a hot-remove.
9625baf3d8SOliver O'Halloran *
9725baf3d8SOliver O'Halloran * A max of 64 entries might be overkill, but it also might not be.
9825baf3d8SOliver O'Halloran */
9925baf3d8SOliver O'Halloran unsigned long stack_trace[64];
10025baf3d8SOliver O'Halloran int trace_entries;
1011b7f3b6cSMichael Ellerman #endif /* CONFIG_STACKTRACE */
102968f968fSGavin Shan };
103968f968fSGavin Shan
1049feed42eSGavin Shan #define eeh_pe_for_each_dev(pe, edev, tmp) \
10580e65b00SSam Bobroff list_for_each_entry_safe(edev, tmp, &pe->edevs, entry)
1065b663529SGavin Shan
107309ed3a7SSam Bobroff #define eeh_for_each_pe(root, pe) \
108309ed3a7SSam Bobroff for (pe = root; pe; pe = eeh_pe_next(pe, root))
109309ed3a7SSam Bobroff
eeh_pe_passed(struct eeh_pe * pe)11005ec424eSGavin Shan static inline bool eeh_pe_passed(struct eeh_pe *pe)
11105ec424eSGavin Shan {
11205ec424eSGavin Shan return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
11305ec424eSGavin Shan }
11405ec424eSGavin Shan
115968f968fSGavin Shan /*
116eb740b5fSGavin Shan * The struct is used to trace EEH state for the associated
117eb740b5fSGavin Shan * PCI device node or PCI device. In future, it might
118eb740b5fSGavin Shan * represent PE as well so that the EEH device to form
119eb740b5fSGavin Shan * another tree except the currently existing tree of PCI
120eb740b5fSGavin Shan * buses and PCI devices
121eb740b5fSGavin Shan */
1224b83bd45SGavin Shan #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
1234b83bd45SGavin Shan #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
1244b83bd45SGavin Shan #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
1254b83bd45SGavin Shan #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
1264b83bd45SGavin Shan #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
127eb740b5fSGavin Shan
128f26c7a03SGavin Shan #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */
129f26c7a03SGavin Shan #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */
130d2b0f6f7SGavin Shan #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */
131ab55d218SGavin Shan
132eb740b5fSGavin Shan struct eeh_dev {
133eb740b5fSGavin Shan int mode; /* EEH mode */
1347c33a994SOliver O'Halloran int bdfn; /* bdfn of device (for cfg ops) */
1357c33a994SOliver O'Halloran struct pci_controller *controller;
136eb740b5fSGavin Shan int pe_config_addr; /* PE config address */
137eb740b5fSGavin Shan u32 config_space[16]; /* Saved PCI config space */
1382a18dfc6SGavin Shan int pcix_cap; /* Saved PCIx capability */
1392a18dfc6SGavin Shan int pcie_cap; /* Saved PCIe capability */
1402a18dfc6SGavin Shan int aer_cap; /* Saved AER capability */
1419312bc5bSWei Yang int af_cap; /* Saved AF capability */
142968f968fSGavin Shan struct eeh_pe *pe; /* Associated PE */
14380e65b00SSam Bobroff struct list_head entry; /* Membership in eeh_pe.edevs */
14480e65b00SSam Bobroff struct list_head rmv_entry; /* Membership in rmv_list */
145e8e9b34cSGavin Shan struct pci_dn *pdn; /* Associated PCI device node */
146eb740b5fSGavin Shan struct pci_dev *pdev; /* Associated PCI device */
14767086e32SWei Yang bool in_error; /* Error flag for edev */
148dffa9153SOliver O'Halloran
149dffa9153SOliver O'Halloran /* VF specific properties */
15039218cd0SWei Yang struct pci_dev *physfn; /* Associated SRIOV PF */
151dffa9153SOliver O'Halloran int vf_index; /* Index of this VF */
152eb740b5fSGavin Shan };
153eb740b5fSGavin Shan
154b093f2cbSSam Bobroff /* "fmt" must be a simple literal string */
155b093f2cbSSam Bobroff #define EEH_EDEV_PRINT(level, edev, fmt, ...) \
156b093f2cbSSam Bobroff pr_##level("PCI %04x:%02x:%02x.%x#%04x: EEH: " fmt, \
157b093f2cbSSam Bobroff (edev)->controller->global_number, PCI_BUSNO((edev)->bdfn), \
158b093f2cbSSam Bobroff PCI_SLOT((edev)->bdfn), PCI_FUNC((edev)->bdfn), \
159b093f2cbSSam Bobroff ((edev)->pe ? (edev)->pe_config_addr : 0xffff), ##__VA_ARGS__)
160b093f2cbSSam Bobroff #define eeh_edev_dbg(edev, fmt, ...) EEH_EDEV_PRINT(debug, (edev), fmt, ##__VA_ARGS__)
161b093f2cbSSam Bobroff #define eeh_edev_info(edev, fmt, ...) EEH_EDEV_PRINT(info, (edev), fmt, ##__VA_ARGS__)
162b093f2cbSSam Bobroff #define eeh_edev_warn(edev, fmt, ...) EEH_EDEV_PRINT(warn, (edev), fmt, ##__VA_ARGS__)
163b093f2cbSSam Bobroff #define eeh_edev_err(edev, fmt, ...) EEH_EDEV_PRINT(err, (edev), fmt, ##__VA_ARGS__)
164b093f2cbSSam Bobroff
eeh_dev_to_pdn(struct eeh_dev * edev)165e8e9b34cSGavin Shan static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
166e8e9b34cSGavin Shan {
167e8e9b34cSGavin Shan return edev ? edev->pdn : NULL;
168e8e9b34cSGavin Shan }
169e8e9b34cSGavin Shan
eeh_dev_to_pci_dev(struct eeh_dev * edev)170eb740b5fSGavin Shan static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
171eb740b5fSGavin Shan {
1722d5c1216SGavin Shan return edev ? edev->pdev : NULL;
173eb740b5fSGavin Shan }
174eb740b5fSGavin Shan
eeh_dev_to_pe(struct eeh_dev * edev)1752a58222fSWei Yang static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
1762a58222fSWei Yang {
1772a58222fSWei Yang return edev ? edev->pe : NULL;
1782a58222fSWei Yang }
1792a58222fSWei Yang
1807e4e7867SGavin Shan /* Return values from eeh_ops::next_error */
1817e4e7867SGavin Shan enum {
1827e4e7867SGavin Shan EEH_NEXT_ERR_NONE = 0,
1837e4e7867SGavin Shan EEH_NEXT_ERR_INF,
1847e4e7867SGavin Shan EEH_NEXT_ERR_FROZEN_PE,
1857e4e7867SGavin Shan EEH_NEXT_ERR_FENCED_PHB,
1867e4e7867SGavin Shan EEH_NEXT_ERR_DEAD_PHB,
1877e4e7867SGavin Shan EEH_NEXT_ERR_DEAD_IOC
1887e4e7867SGavin Shan };
1897e4e7867SGavin Shan
190eb740b5fSGavin Shan /*
191aa1e6374SGavin Shan * The struct is used to trace the registered EEH operation
192aa1e6374SGavin Shan * callback functions. Actually, those operation callback
193aa1e6374SGavin Shan * functions are heavily platform dependent. That means the
194aa1e6374SGavin Shan * platform should register its own EEH operation callback
195aa1e6374SGavin Shan * functions before any EEH further operations.
196aa1e6374SGavin Shan */
1978fb8f709SGavin Shan #define EEH_OPT_DISABLE 0 /* EEH disable */
1988fb8f709SGavin Shan #define EEH_OPT_ENABLE 1 /* EEH enable */
1998fb8f709SGavin Shan #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
2008fb8f709SGavin Shan #define EEH_OPT_THAW_DMA 3 /* DMA enable */
2010d5ee520SGavin Shan #define EEH_OPT_FREEZE_PE 4 /* Freeze PE */
202eb594a47SGavin Shan #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
203eb594a47SGavin Shan #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
204eb594a47SGavin Shan #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
205eb594a47SGavin Shan #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
206eb594a47SGavin Shan #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
207eb594a47SGavin Shan #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
208eb594a47SGavin Shan #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
2092652481fSGavin Shan #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
2102652481fSGavin Shan #define EEH_RESET_HOT 1 /* Hot reset */
2112652481fSGavin Shan #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
2128d633291SGavin Shan #define EEH_LOG_TEMP 1 /* EEH temporary error log */
2138d633291SGavin Shan #define EEH_LOG_PERM 2 /* EEH permanent error log */
214eb594a47SGavin Shan
215aa1e6374SGavin Shan struct eeh_ops {
216aa1e6374SGavin Shan char *name;
217e86350f7SOliver O'Halloran struct eeh_dev *(*probe)(struct pci_dev *pdev);
218371a395dSGavin Shan int (*set_option)(struct eeh_pe *pe, int option);
219fef7f905SSam Bobroff int (*get_state)(struct eeh_pe *pe, int *delay);
220371a395dSGavin Shan int (*reset)(struct eeh_pe *pe, int option);
221371a395dSGavin Shan int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
222371a395dSGavin Shan int (*configure_bridge)(struct eeh_pe *pe);
223131c123aSGavin Shan int (*err_inject)(struct eeh_pe *pe, int type, int func,
224131c123aSGavin Shan unsigned long addr, unsigned long mask);
22517d2a487SOliver O'Halloran int (*read_config)(struct eeh_dev *edev, int where, int size, u32 *val);
22617d2a487SOliver O'Halloran int (*write_config)(struct eeh_dev *edev, int where, int size, u32 val);
2278a6b1bc7SGavin Shan int (*next_error)(struct eeh_pe **pe);
2280c2c7652SOliver O'Halloran int (*restore_config)(struct eeh_dev *edev);
2298225d543SOliver O'Halloran int (*notify_resume)(struct eeh_dev *edev);
230aa1e6374SGavin Shan };
231aa1e6374SGavin Shan
2328a5ad356SGavin Shan extern int eeh_subsystem_flags;
23346ee7c3cSOliver O'Halloran extern u32 eeh_max_freezes;
2346b493f60SOliver O'Halloran extern bool eeh_debugfs_no_recover;
235aa1e6374SGavin Shan extern struct eeh_ops *eeh_ops;
2364907581dSGavin Shan extern raw_spinlock_t confirm_error_lock;
237d7bb8862SGavin Shan
eeh_add_flag(int flag)23805b1721dSGavin Shan static inline void eeh_add_flag(int flag)
239d7bb8862SGavin Shan {
2408a5ad356SGavin Shan eeh_subsystem_flags |= flag;
241d7bb8862SGavin Shan }
242d7bb8862SGavin Shan
eeh_clear_flag(int flag)24305b1721dSGavin Shan static inline void eeh_clear_flag(int flag)
244d7bb8862SGavin Shan {
24505b1721dSGavin Shan eeh_subsystem_flags &= ~flag;
246d7bb8862SGavin Shan }
247d7bb8862SGavin Shan
eeh_has_flag(int flag)24805b1721dSGavin Shan static inline bool eeh_has_flag(int flag)
249d7bb8862SGavin Shan {
25005b1721dSGavin Shan return !!(eeh_subsystem_flags & flag);
25105b1721dSGavin Shan }
25205b1721dSGavin Shan
eeh_enabled(void)25305b1721dSGavin Shan static inline bool eeh_enabled(void)
25405b1721dSGavin Shan {
25554644927SSam Bobroff return eeh_has_flag(EEH_ENABLED) && !eeh_has_flag(EEH_FORCE_DISABLED);
256d7bb8862SGavin Shan }
257646a8499SGavin Shan
eeh_serialize_lock(unsigned long * flags)2584907581dSGavin Shan static inline void eeh_serialize_lock(unsigned long *flags)
2594907581dSGavin Shan {
2604907581dSGavin Shan raw_spin_lock_irqsave(&confirm_error_lock, *flags);
2614907581dSGavin Shan }
2624907581dSGavin Shan
eeh_serialize_unlock(unsigned long flags)2634907581dSGavin Shan static inline void eeh_serialize_unlock(unsigned long flags)
2644907581dSGavin Shan {
2654907581dSGavin Shan raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
2664907581dSGavin Shan }
2674907581dSGavin Shan
eeh_state_active(int state)26834a286a4SSam Bobroff static inline bool eeh_state_active(int state)
26934a286a4SSam Bobroff {
27034a286a4SSam Bobroff return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
27134a286a4SSam Bobroff == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
27234a286a4SSam Bobroff }
27334a286a4SSam Bobroff
274cef50c67SSam Bobroff typedef void (*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag);
275d6c4932fSSam Bobroff typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag);
276bb593c00SGavin Shan void eeh_set_pe_aux_size(int size);
277cad5cef6SGreg Kroah-Hartman int eeh_phb_pe_create(struct pci_controller *phb);
278fef7f905SSam Bobroff int eeh_wait_state(struct eeh_pe *pe, int max_wait);
2799ff67433SGavin Shan struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
280309ed3a7SSam Bobroff struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root);
28135d64734SOliver O'Halloran struct eeh_pe *eeh_pe_get(struct pci_controller *phb, int pe_no);
282a131bfc6SOliver O'Halloran int eeh_pe_tree_insert(struct eeh_dev *edev, struct eeh_pe *new_pe_parent);
283d923ab7aSOliver O'Halloran int eeh_pe_tree_remove(struct eeh_dev *edev);
2845a71978eSGavin Shan void eeh_pe_update_time_stamp(struct eeh_pe *pe);
285f5c57710SGavin Shan void *eeh_pe_traverse(struct eeh_pe *root,
286d6c4932fSSam Bobroff eeh_pe_traverse_func fn, void *flag);
287cef50c67SSam Bobroff void eeh_pe_dev_traverse(struct eeh_pe *root,
288d6c4932fSSam Bobroff eeh_edev_traverse_func fn, void *flag);
2899e6d2cf6SGavin Shan void eeh_pe_restore_bars(struct eeh_pe *pe);
290357b2f3dSGavin Shan const char *eeh_pe_loc_get(struct eeh_pe *pe);
2919b3c76f0SGavin Shan struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
29255037d17SGavin Shan
293c44e4ccaSSam Bobroff void eeh_show_enabled(void);
294d125aedbSOliver O'Halloran int __init eeh_init(struct eeh_ops *ops);
2953e938052SGavin Shan int eeh_check_failure(const volatile void __iomem *token);
296f8f7d63fSGavin Shan int eeh_dev_check_failure(struct eeh_dev *edev);
297685a0bc0SSam Bobroff void eeh_addr_cache_init(void);
298e86350f7SOliver O'Halloran void eeh_probe_device(struct pci_dev *pdev);
299807a827dSGavin Shan void eeh_remove_device(struct pci_dev *);
300188fdea6SSam Bobroff int eeh_unfreeze_pe(struct eeh_pe *pe);
3015cfb20b9SGavin Shan int eeh_pe_reset_and_recover(struct eeh_pe *pe);
302212d16cdSGavin Shan int eeh_dev_open(struct pci_dev *pdev);
303212d16cdSGavin Shan void eeh_dev_release(struct pci_dev *pdev);
304212d16cdSGavin Shan struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
305212d16cdSGavin Shan int eeh_pe_set_option(struct eeh_pe *pe, int option);
306212d16cdSGavin Shan int eeh_pe_get_state(struct eeh_pe *pe);
3071ef52073SSam Bobroff int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed);
308212d16cdSGavin Shan int eeh_pe_configure(struct eeh_pe *pe);
309ec33d36eSGavin Shan int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
310ec33d36eSGavin Shan unsigned long addr, unsigned long mask);
311b8b572e1SStephen Rothwell
312b8b572e1SStephen Rothwell /**
313b8b572e1SStephen Rothwell * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
314b8b572e1SStephen Rothwell *
315b8b572e1SStephen Rothwell * If this macro yields TRUE, the caller relays to eeh_check_failure()
316b8b572e1SStephen Rothwell * which does further tests out of line.
317b8b572e1SStephen Rothwell */
3182ec5a0adSGavin Shan #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
319b8b572e1SStephen Rothwell
320b8b572e1SStephen Rothwell /*
321b8b572e1SStephen Rothwell * Reads from a device which has been isolated by EEH will return
322b8b572e1SStephen Rothwell * all 1s. This macro gives an all-1s value of the given size (in
323b8b572e1SStephen Rothwell * bytes: 1, 2, or 4) for comparing with the result of a read.
324b8b572e1SStephen Rothwell */
325b8b572e1SStephen Rothwell #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
326b8b572e1SStephen Rothwell
327b8b572e1SStephen Rothwell #else /* !CONFIG_EEH */
328eb740b5fSGavin Shan
eeh_enabled(void)3292ec5a0adSGavin Shan static inline bool eeh_enabled(void)
3302ec5a0adSGavin Shan {
3312ec5a0adSGavin Shan return false;
3322ec5a0adSGavin Shan }
3332ec5a0adSGavin Shan
eeh_show_enabled(void)334c44e4ccaSSam Bobroff static inline void eeh_show_enabled(void) { }
33551fb5f56SGavin Shan
eeh_check_failure(const volatile void __iomem * token)3363e938052SGavin Shan static inline int eeh_check_failure(const volatile void __iomem *token)
337b8b572e1SStephen Rothwell {
3383e938052SGavin Shan return 0;
339b8b572e1SStephen Rothwell }
340b8b572e1SStephen Rothwell
341f8f7d63fSGavin Shan #define eeh_dev_check_failure(x) (0)
342b8b572e1SStephen Rothwell
eeh_addr_cache_init(void)343685a0bc0SSam Bobroff static inline void eeh_addr_cache_init(void) { }
344685a0bc0SSam Bobroff
eeh_probe_device(struct pci_dev * dev)345e86350f7SOliver O'Halloran static inline void eeh_probe_device(struct pci_dev *dev) { }
346f2856491SGavin Shan
eeh_remove_device(struct pci_dev * dev)347807a827dSGavin Shan static inline void eeh_remove_device(struct pci_dev *dev) { }
348646a8499SGavin Shan
349b8b572e1SStephen Rothwell #define EEH_POSSIBLE_ERROR(val, type) (0)
350b8b572e1SStephen Rothwell #define EEH_IO_ERROR_VALUE(size) (-1UL)
eeh_phb_pe_create(struct pci_controller * phb)351475028efSOliver O'Halloran static inline int eeh_phb_pe_create(struct pci_controller *phb) { return 0; }
352b8b572e1SStephen Rothwell #endif /* CONFIG_EEH */
353b8b572e1SStephen Rothwell
354b6eebb09SOliver O'Halloran #if defined(CONFIG_PPC_PSERIES) && defined(CONFIG_EEH)
355b6eebb09SOliver O'Halloran void pseries_eeh_init_edev_recursive(struct pci_dn *pdn);
356b6eebb09SOliver O'Halloran #endif
357b6eebb09SOliver O'Halloran
3588b8da358SBenjamin Herrenschmidt #ifdef CONFIG_PPC64
359b8b572e1SStephen Rothwell /*
360b8b572e1SStephen Rothwell * MMIO read/write operations with EEH support.
361b8b572e1SStephen Rothwell */
eeh_readb(const volatile void __iomem * addr)362b8b572e1SStephen Rothwell static inline u8 eeh_readb(const volatile void __iomem *addr)
363b8b572e1SStephen Rothwell {
364b8b572e1SStephen Rothwell u8 val = in_8(addr);
365b8b572e1SStephen Rothwell if (EEH_POSSIBLE_ERROR(val, u8))
3663e938052SGavin Shan eeh_check_failure(addr);
367b8b572e1SStephen Rothwell return val;
368b8b572e1SStephen Rothwell }
369b8b572e1SStephen Rothwell
eeh_readw(const volatile void __iomem * addr)370b8b572e1SStephen Rothwell static inline u16 eeh_readw(const volatile void __iomem *addr)
371b8b572e1SStephen Rothwell {
372b8b572e1SStephen Rothwell u16 val = in_le16(addr);
373b8b572e1SStephen Rothwell if (EEH_POSSIBLE_ERROR(val, u16))
3743e938052SGavin Shan eeh_check_failure(addr);
375b8b572e1SStephen Rothwell return val;
376b8b572e1SStephen Rothwell }
377b8b572e1SStephen Rothwell
eeh_readl(const volatile void __iomem * addr)378b8b572e1SStephen Rothwell static inline u32 eeh_readl(const volatile void __iomem *addr)
379b8b572e1SStephen Rothwell {
380b8b572e1SStephen Rothwell u32 val = in_le32(addr);
381b8b572e1SStephen Rothwell if (EEH_POSSIBLE_ERROR(val, u32))
3823e938052SGavin Shan eeh_check_failure(addr);
383b8b572e1SStephen Rothwell return val;
384b8b572e1SStephen Rothwell }
385b8b572e1SStephen Rothwell
eeh_readq(const volatile void __iomem * addr)386b8b572e1SStephen Rothwell static inline u64 eeh_readq(const volatile void __iomem *addr)
387b8b572e1SStephen Rothwell {
388b8b572e1SStephen Rothwell u64 val = in_le64(addr);
389b8b572e1SStephen Rothwell if (EEH_POSSIBLE_ERROR(val, u64))
3903e938052SGavin Shan eeh_check_failure(addr);
391b8b572e1SStephen Rothwell return val;
392b8b572e1SStephen Rothwell }
393b8b572e1SStephen Rothwell
eeh_readw_be(const volatile void __iomem * addr)394b8b572e1SStephen Rothwell static inline u16 eeh_readw_be(const volatile void __iomem *addr)
395b8b572e1SStephen Rothwell {
396b8b572e1SStephen Rothwell u16 val = in_be16(addr);
397b8b572e1SStephen Rothwell if (EEH_POSSIBLE_ERROR(val, u16))
3983e938052SGavin Shan eeh_check_failure(addr);
399b8b572e1SStephen Rothwell return val;
400b8b572e1SStephen Rothwell }
401b8b572e1SStephen Rothwell
eeh_readl_be(const volatile void __iomem * addr)402b8b572e1SStephen Rothwell static inline u32 eeh_readl_be(const volatile void __iomem *addr)
403b8b572e1SStephen Rothwell {
404b8b572e1SStephen Rothwell u32 val = in_be32(addr);
405b8b572e1SStephen Rothwell if (EEH_POSSIBLE_ERROR(val, u32))
4063e938052SGavin Shan eeh_check_failure(addr);
407b8b572e1SStephen Rothwell return val;
408b8b572e1SStephen Rothwell }
409b8b572e1SStephen Rothwell
eeh_readq_be(const volatile void __iomem * addr)410b8b572e1SStephen Rothwell static inline u64 eeh_readq_be(const volatile void __iomem *addr)
411b8b572e1SStephen Rothwell {
412b8b572e1SStephen Rothwell u64 val = in_be64(addr);
413b8b572e1SStephen Rothwell if (EEH_POSSIBLE_ERROR(val, u64))
4143e938052SGavin Shan eeh_check_failure(addr);
415b8b572e1SStephen Rothwell return val;
416b8b572e1SStephen Rothwell }
417b8b572e1SStephen Rothwell
eeh_memcpy_fromio(void * dest,const volatile void __iomem * src,unsigned long n)418b8b572e1SStephen Rothwell static inline void eeh_memcpy_fromio(void *dest, const
419b8b572e1SStephen Rothwell volatile void __iomem *src,
420b8b572e1SStephen Rothwell unsigned long n)
421b8b572e1SStephen Rothwell {
422b8b572e1SStephen Rothwell _memcpy_fromio(dest, src, n);
423b8b572e1SStephen Rothwell
424b8b572e1SStephen Rothwell /* Look for ffff's here at dest[n]. Assume that at least 4 bytes
425b8b572e1SStephen Rothwell * were copied. Check all four bytes.
426b8b572e1SStephen Rothwell */
427b8b572e1SStephen Rothwell if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
4283e938052SGavin Shan eeh_check_failure(src);
429b8b572e1SStephen Rothwell }
430b8b572e1SStephen Rothwell
431b8b572e1SStephen Rothwell /* in-string eeh macros */
eeh_readsb(const volatile void __iomem * addr,void * buf,int ns)432b8b572e1SStephen Rothwell static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
433b8b572e1SStephen Rothwell int ns)
434b8b572e1SStephen Rothwell {
435b8b572e1SStephen Rothwell _insb(addr, buf, ns);
436b8b572e1SStephen Rothwell if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
4373e938052SGavin Shan eeh_check_failure(addr);
438b8b572e1SStephen Rothwell }
439b8b572e1SStephen Rothwell
eeh_readsw(const volatile void __iomem * addr,void * buf,int ns)440b8b572e1SStephen Rothwell static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
441b8b572e1SStephen Rothwell int ns)
442b8b572e1SStephen Rothwell {
443b8b572e1SStephen Rothwell _insw(addr, buf, ns);
444b8b572e1SStephen Rothwell if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
4453e938052SGavin Shan eeh_check_failure(addr);
446b8b572e1SStephen Rothwell }
447b8b572e1SStephen Rothwell
eeh_readsl(const volatile void __iomem * addr,void * buf,int nl)448b8b572e1SStephen Rothwell static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
449b8b572e1SStephen Rothwell int nl)
450b8b572e1SStephen Rothwell {
451b8b572e1SStephen Rothwell _insl(addr, buf, nl);
452b8b572e1SStephen Rothwell if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
4533e938052SGavin Shan eeh_check_failure(addr);
454b8b572e1SStephen Rothwell }
455b8b572e1SStephen Rothwell
4565ca85ae6SOliver O'Halloran
457*d276960dSNick Child void __init eeh_cache_debugfs_init(void);
4585ca85ae6SOliver O'Halloran
4598b8da358SBenjamin Herrenschmidt #endif /* CONFIG_PPC64 */
460b8b572e1SStephen Rothwell #endif /* __KERNEL__ */
4618b8da358SBenjamin Herrenschmidt #endif /* _POWERPC_EEH_H */
462