1 #ifndef _ASM_POWERPC_DMA_H 2 #define _ASM_POWERPC_DMA_H 3 #ifdef __KERNEL__ 4 5 /* 6 * Defines for using and allocating dma channels. 7 * Written by Hennus Bergman, 1992. 8 * High DMA channel support & info by Hannu Savolainen 9 * and John Boyd, Nov. 1992. 10 * Changes for ppc sound by Christoph Nadig 11 */ 12 13 /* 14 * Note: Adapted for PowerPC by Gary Thomas 15 * Modified by Cort Dougan <cort@cs.nmt.edu> 16 * 17 * None of this really applies for Power Macintoshes. There is 18 * basically just enough here to get kernel/dma.c to compile. 19 * 20 * There may be some comments or restrictions made here which are 21 * not valid for the PReP platform. Take what you read 22 * with a grain of salt. 23 */ 24 25 #include <asm/io.h> 26 #include <linux/spinlock.h> 27 28 #ifndef MAX_DMA_CHANNELS 29 #define MAX_DMA_CHANNELS 8 30 #endif 31 32 /* The maximum address that we can perform a DMA transfer to on this platform */ 33 /* Doesn't really apply... */ 34 #define MAX_DMA_ADDRESS (~0UL) 35 36 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER 37 #define dma_outb outb_p 38 #else 39 #define dma_outb outb 40 #endif 41 42 #define dma_inb inb 43 44 /* 45 * NOTES about DMA transfers: 46 * 47 * controller 1: channels 0-3, byte operations, ports 00-1F 48 * controller 2: channels 4-7, word operations, ports C0-DF 49 * 50 * - ALL registers are 8 bits only, regardless of transfer size 51 * - channel 4 is not used - cascades 1 into 2. 52 * - channels 0-3 are byte - addresses/counts are for physical bytes 53 * - channels 5-7 are word - addresses/counts are for physical words 54 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries 55 * - transfer count loaded to registers is 1 less than actual count 56 * - controller 2 offsets are all even (2x offsets for controller 1) 57 * - page registers for 5-7 don't use data bit 0, represent 128K pages 58 * - page registers for 0-3 use bit 0, represent 64K pages 59 * 60 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory. 61 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing. 62 * Note that addresses loaded into registers must be _physical_ addresses, 63 * not logical addresses (which may differ if paging is active). 64 * 65 * Address mapping for channels 0-3: 66 * 67 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) 68 * | ... | | ... | | ... | 69 * | ... | | ... | | ... | 70 * | ... | | ... | | ... | 71 * P7 ... P0 A7 ... A0 A7 ... A0 72 * | Page | Addr MSB | Addr LSB | (DMA registers) 73 * 74 * Address mapping for channels 5-7: 75 * 76 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) 77 * | ... | \ \ ... \ \ \ ... \ \ 78 * | ... | \ \ ... \ \ \ ... \ (not used) 79 * | ... | \ \ ... \ \ \ ... \ 80 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 81 * | Page | Addr MSB | Addr LSB | (DMA registers) 82 * 83 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses 84 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at 85 * the hardware level, so odd-byte transfers aren't possible). 86 * 87 * Transfer count (_not # bytes_) is limited to 64K, represented as actual 88 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, 89 * and up to 128K bytes may be transferred on channels 5-7 in one operation. 90 * 91 */ 92 93 /* 8237 DMA controllers */ 94 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 95 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ 96 97 /* DMA controller registers */ 98 #define DMA1_CMD_REG 0x08 /* command register (w) */ 99 #define DMA1_STAT_REG 0x08 /* status register (r) */ 100 #define DMA1_REQ_REG 0x09 /* request register (w) */ 101 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ 102 #define DMA1_MODE_REG 0x0B /* mode register (w) */ 103 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ 104 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ 105 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ 106 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ 107 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ 108 109 #define DMA2_CMD_REG 0xD0 /* command register (w) */ 110 #define DMA2_STAT_REG 0xD0 /* status register (r) */ 111 #define DMA2_REQ_REG 0xD2 /* request register (w) */ 112 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ 113 #define DMA2_MODE_REG 0xD6 /* mode register (w) */ 114 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ 115 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ 116 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ 117 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ 118 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 119 120 #define DMA_ADDR_0 0x00 /* DMA address registers */ 121 #define DMA_ADDR_1 0x02 122 #define DMA_ADDR_2 0x04 123 #define DMA_ADDR_3 0x06 124 #define DMA_ADDR_4 0xC0 125 #define DMA_ADDR_5 0xC4 126 #define DMA_ADDR_6 0xC8 127 #define DMA_ADDR_7 0xCC 128 129 #define DMA_CNT_0 0x01 /* DMA count registers */ 130 #define DMA_CNT_1 0x03 131 #define DMA_CNT_2 0x05 132 #define DMA_CNT_3 0x07 133 #define DMA_CNT_4 0xC2 134 #define DMA_CNT_5 0xC6 135 #define DMA_CNT_6 0xCA 136 #define DMA_CNT_7 0xCE 137 138 #define DMA_LO_PAGE_0 0x87 /* DMA page registers */ 139 #define DMA_LO_PAGE_1 0x83 140 #define DMA_LO_PAGE_2 0x81 141 #define DMA_LO_PAGE_3 0x82 142 #define DMA_LO_PAGE_5 0x8B 143 #define DMA_LO_PAGE_6 0x89 144 #define DMA_LO_PAGE_7 0x8A 145 146 #define DMA_HI_PAGE_0 0x487 /* DMA page registers */ 147 #define DMA_HI_PAGE_1 0x483 148 #define DMA_HI_PAGE_2 0x481 149 #define DMA_HI_PAGE_3 0x482 150 #define DMA_HI_PAGE_5 0x48B 151 #define DMA_HI_PAGE_6 0x489 152 #define DMA_HI_PAGE_7 0x48A 153 154 #define DMA1_EXT_REG 0x40B 155 #define DMA2_EXT_REG 0x4D6 156 157 #ifndef __powerpc64__ 158 /* in arch/ppc/kernel/setup.c -- Cort */ 159 extern unsigned int DMA_MODE_WRITE; 160 extern unsigned int DMA_MODE_READ; 161 extern unsigned long ISA_DMA_THRESHOLD; 162 #else 163 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ 164 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ 165 #endif 166 167 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ 168 169 #define DMA_AUTOINIT 0x10 170 171 extern spinlock_t dma_spin_lock; 172 173 static __inline__ unsigned long claim_dma_lock(void) 174 { 175 unsigned long flags; 176 spin_lock_irqsave(&dma_spin_lock, flags); 177 return flags; 178 } 179 180 static __inline__ void release_dma_lock(unsigned long flags) 181 { 182 spin_unlock_irqrestore(&dma_spin_lock, flags); 183 } 184 185 /* enable/disable a specific DMA channel */ 186 static __inline__ void enable_dma(unsigned int dmanr) 187 { 188 unsigned char ucDmaCmd = 0x00; 189 190 if (dmanr != 4) { 191 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */ 192 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */ 193 } 194 if (dmanr <= 3) { 195 dma_outb(dmanr, DMA1_MASK_REG); 196 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */ 197 } else { 198 dma_outb(dmanr & 3, DMA2_MASK_REG); 199 } 200 } 201 202 static __inline__ void disable_dma(unsigned int dmanr) 203 { 204 if (dmanr <= 3) 205 dma_outb(dmanr | 4, DMA1_MASK_REG); 206 else 207 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); 208 } 209 210 /* Clear the 'DMA Pointer Flip Flop'. 211 * Write 0 for LSB/MSB, 1 for MSB/LSB access. 212 * Use this once to initialize the FF to a known state. 213 * After that, keep track of it. :-) 214 * --- In order to do that, the DMA routines below should --- 215 * --- only be used while interrupts are disabled! --- 216 */ 217 static __inline__ void clear_dma_ff(unsigned int dmanr) 218 { 219 if (dmanr <= 3) 220 dma_outb(0, DMA1_CLEAR_FF_REG); 221 else 222 dma_outb(0, DMA2_CLEAR_FF_REG); 223 } 224 225 /* set mode (above) for a specific DMA channel */ 226 static __inline__ void set_dma_mode(unsigned int dmanr, char mode) 227 { 228 if (dmanr <= 3) 229 dma_outb(mode | dmanr, DMA1_MODE_REG); 230 else 231 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG); 232 } 233 234 /* Set only the page register bits of the transfer address. 235 * This is used for successive transfers when we know the contents of 236 * the lower 16 bits of the DMA current address register, but a 64k boundary 237 * may have been crossed. 238 */ 239 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr) 240 { 241 switch (dmanr) { 242 case 0: 243 dma_outb(pagenr, DMA_LO_PAGE_0); 244 dma_outb(pagenr >> 8, DMA_HI_PAGE_0); 245 break; 246 case 1: 247 dma_outb(pagenr, DMA_LO_PAGE_1); 248 dma_outb(pagenr >> 8, DMA_HI_PAGE_1); 249 break; 250 case 2: 251 dma_outb(pagenr, DMA_LO_PAGE_2); 252 dma_outb(pagenr >> 8, DMA_HI_PAGE_2); 253 break; 254 case 3: 255 dma_outb(pagenr, DMA_LO_PAGE_3); 256 dma_outb(pagenr >> 8, DMA_HI_PAGE_3); 257 break; 258 case 5: 259 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5); 260 dma_outb(pagenr >> 8, DMA_HI_PAGE_5); 261 break; 262 case 6: 263 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6); 264 dma_outb(pagenr >> 8, DMA_HI_PAGE_6); 265 break; 266 case 7: 267 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7); 268 dma_outb(pagenr >> 8, DMA_HI_PAGE_7); 269 break; 270 } 271 } 272 273 /* Set transfer address & page bits for specific DMA channel. 274 * Assumes dma flipflop is clear. 275 */ 276 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys) 277 { 278 if (dmanr <= 3) { 279 dma_outb(phys & 0xff, 280 ((dmanr & 3) << 1) + IO_DMA1_BASE); 281 dma_outb((phys >> 8) & 0xff, 282 ((dmanr & 3) << 1) + IO_DMA1_BASE); 283 } else { 284 dma_outb((phys >> 1) & 0xff, 285 ((dmanr & 3) << 2) + IO_DMA2_BASE); 286 dma_outb((phys >> 9) & 0xff, 287 ((dmanr & 3) << 2) + IO_DMA2_BASE); 288 } 289 set_dma_page(dmanr, phys >> 16); 290 } 291 292 293 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for 294 * a specific DMA channel. 295 * You must ensure the parameters are valid. 296 * NOTE: from a manual: "the number of transfers is one more 297 * than the initial word count"! This is taken into account. 298 * Assumes dma flip-flop is clear. 299 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. 300 */ 301 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) 302 { 303 count--; 304 if (dmanr <= 3) { 305 dma_outb(count & 0xff, 306 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE); 307 dma_outb((count >> 8) & 0xff, 308 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE); 309 } else { 310 dma_outb((count >> 1) & 0xff, 311 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE); 312 dma_outb((count >> 9) & 0xff, 313 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE); 314 } 315 } 316 317 318 /* Get DMA residue count. After a DMA transfer, this 319 * should return zero. Reading this while a DMA transfer is 320 * still in progress will return unpredictable results. 321 * If called before the channel has been used, it may return 1. 322 * Otherwise, it returns the number of _bytes_ left to transfer. 323 * 324 * Assumes DMA flip-flop is clear. 325 */ 326 static __inline__ int get_dma_residue(unsigned int dmanr) 327 { 328 unsigned int io_port = (dmanr <= 3) 329 ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE 330 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE; 331 332 /* using short to get 16-bit wrap around */ 333 unsigned short count; 334 335 count = 1 + dma_inb(io_port); 336 count += dma_inb(io_port) << 8; 337 338 return (dmanr <= 3) ? count : (count << 1); 339 } 340 341 /* These are in kernel/dma.c: */ 342 343 /* reserve a DMA channel */ 344 extern int request_dma(unsigned int dmanr, const char *device_id); 345 /* release it again */ 346 extern void free_dma(unsigned int dmanr); 347 348 #ifdef CONFIG_PCI 349 extern int isa_dma_bridge_buggy; 350 #else 351 #define isa_dma_bridge_buggy (0) 352 #endif 353 354 #endif /* __KERNEL__ */ 355 #endif /* _ASM_POWERPC_DMA_H */ 356