1 #ifndef __ASM_POWERPC_CPUTABLE_H 2 #define __ASM_POWERPC_CPUTABLE_H 3 4 5 #include <asm/asm-compat.h> 6 #include <asm/feature-fixups.h> 7 #include <uapi/asm/cputable.h> 8 9 #ifndef __ASSEMBLY__ 10 11 /* This structure can grow, it's real size is used by head.S code 12 * via the mkdefs mechanism. 13 */ 14 struct cpu_spec; 15 16 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 17 typedef void (*cpu_restore_t)(void); 18 19 enum powerpc_oprofile_type { 20 PPC_OPROFILE_INVALID = 0, 21 PPC_OPROFILE_RS64 = 1, 22 PPC_OPROFILE_POWER4 = 2, 23 PPC_OPROFILE_G4 = 3, 24 PPC_OPROFILE_FSL_EMB = 4, 25 PPC_OPROFILE_CELL = 5, 26 PPC_OPROFILE_PA6T = 6, 27 }; 28 29 enum powerpc_pmc_type { 30 PPC_PMC_DEFAULT = 0, 31 PPC_PMC_IBM = 1, 32 PPC_PMC_PA6T = 2, 33 PPC_PMC_G4 = 3, 34 }; 35 36 struct pt_regs; 37 38 extern int machine_check_generic(struct pt_regs *regs); 39 extern int machine_check_4xx(struct pt_regs *regs); 40 extern int machine_check_440A(struct pt_regs *regs); 41 extern int machine_check_e500mc(struct pt_regs *regs); 42 extern int machine_check_e500(struct pt_regs *regs); 43 extern int machine_check_e200(struct pt_regs *regs); 44 extern int machine_check_47x(struct pt_regs *regs); 45 46 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 47 struct cpu_spec { 48 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 49 unsigned int pvr_mask; 50 unsigned int pvr_value; 51 52 char *cpu_name; 53 unsigned long cpu_features; /* Kernel features */ 54 unsigned int cpu_user_features; /* Userland features */ 55 unsigned int cpu_user_features2; /* Userland features v2 */ 56 unsigned int mmu_features; /* MMU features */ 57 58 /* cache line sizes */ 59 unsigned int icache_bsize; 60 unsigned int dcache_bsize; 61 62 /* number of performance monitor counters */ 63 unsigned int num_pmcs; 64 enum powerpc_pmc_type pmc_type; 65 66 /* this is called to initialize various CPU bits like L1 cache, 67 * BHT, SPD, etc... from head.S before branching to identify_machine 68 */ 69 cpu_setup_t cpu_setup; 70 /* Used to restore cpu setup on secondary processors and at resume */ 71 cpu_restore_t cpu_restore; 72 73 /* Used by oprofile userspace to select the right counters */ 74 char *oprofile_cpu_type; 75 76 /* Processor specific oprofile operations */ 77 enum powerpc_oprofile_type oprofile_type; 78 79 /* Bit locations inside the mmcra change */ 80 unsigned long oprofile_mmcra_sihv; 81 unsigned long oprofile_mmcra_sipr; 82 83 /* Bits to clear during an oprofile exception */ 84 unsigned long oprofile_mmcra_clear; 85 86 /* Name of processor class, for the ELF AT_PLATFORM entry */ 87 char *platform; 88 89 /* Processor specific machine check handling. Return negative 90 * if the error is fatal, 1 if it was fully recovered and 0 to 91 * pass up (not CPU originated) */ 92 int (*machine_check)(struct pt_regs *regs); 93 94 /* 95 * Processor specific early machine check handler which is 96 * called in real mode to handle SLB and TLB errors. 97 */ 98 long (*machine_check_early)(struct pt_regs *regs); 99 100 /* 101 * Processor specific routine to flush tlbs. 102 */ 103 void (*flush_tlb)(unsigned long inval_selector); 104 105 }; 106 107 extern struct cpu_spec *cur_cpu_spec; 108 109 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 110 111 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 112 extern void do_feature_fixups(unsigned long value, void *fixup_start, 113 void *fixup_end); 114 115 extern const char *powerpc_base_platform; 116 117 #endif /* __ASSEMBLY__ */ 118 119 /* CPU kernel features */ 120 121 /* Retain the 32b definitions all use bottom half of word */ 122 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) 123 #define CPU_FTR_L2CR ASM_CONST(0x00000002) 124 #define CPU_FTR_SPEC7450 ASM_CONST(0x00000004) 125 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000008) 126 #define CPU_FTR_TAU ASM_CONST(0x00000010) 127 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020) 128 #define CPU_FTR_USE_TB ASM_CONST(0x00000040) 129 #define CPU_FTR_L2CSR ASM_CONST(0x00000080) 130 #define CPU_FTR_601 ASM_CONST(0x00000100) 131 #define CPU_FTR_DBELL ASM_CONST(0x00000200) 132 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400) 133 #define CPU_FTR_L3CR ASM_CONST(0x00000800) 134 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000) 135 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000) 136 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000) 137 #define CPU_FTR_NO_DPM ASM_CONST(0x00008000) 138 #define CPU_FTR_476_DD2 ASM_CONST(0x00010000) 139 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000) 140 #define CPU_FTR_NO_BTIC ASM_CONST(0x00040000) 141 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000) 142 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000) 143 #define CPU_FTR_PPC_LE ASM_CONST(0x00200000) 144 #define CPU_FTR_REAL_LE ASM_CONST(0x00400000) 145 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000) 146 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000) 147 #define CPU_FTR_SPE ASM_CONST(0x02000000) 148 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000) 149 #define CPU_FTR_LWSYNC ASM_CONST(0x08000000) 150 #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000) 151 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000) 152 #define CPU_FTR_EMB_HV ASM_CONST(0x40000000) 153 154 /* 155 * Add the 64-bit processor unique features in the top half of the word; 156 * on 32-bit, make the names available but defined to be 0. 157 */ 158 #ifdef __powerpc64__ 159 #define LONG_ASM_CONST(x) ASM_CONST(x) 160 #else 161 #define LONG_ASM_CONST(x) 0 162 #endif 163 164 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000) 165 #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000) 166 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000) 167 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000) 168 #define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000) 169 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000) 170 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000) 171 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000) 172 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000) 173 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000) 174 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000) 175 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000) 176 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000) 177 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000) 178 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000) 179 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000) 180 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000) 181 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000) 182 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000) 183 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000) 184 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000) 185 #define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000) 186 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000) 187 #define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000) 188 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000) 189 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) 190 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) 191 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000) 192 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000) 193 194 #ifndef __ASSEMBLY__ 195 196 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 197 198 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \ 199 MMU_FTR_16M_PAGE) 200 201 /* We only set the altivec features if the kernel was compiled with altivec 202 * support 203 */ 204 #ifdef CONFIG_ALTIVEC 205 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 206 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 207 #else 208 #define CPU_FTR_ALTIVEC_COMP 0 209 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 210 #endif 211 212 /* We only set the VSX features if the kernel was compiled with VSX 213 * support 214 */ 215 #ifdef CONFIG_VSX 216 #define CPU_FTR_VSX_COMP CPU_FTR_VSX 217 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 218 #else 219 #define CPU_FTR_VSX_COMP 0 220 #define PPC_FEATURE_HAS_VSX_COMP 0 221 #endif 222 223 /* We only set the spe features if the kernel was compiled with spe 224 * support 225 */ 226 #ifdef CONFIG_SPE 227 #define CPU_FTR_SPE_COMP CPU_FTR_SPE 228 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 229 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 230 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 231 #else 232 #define CPU_FTR_SPE_COMP 0 233 #define PPC_FEATURE_HAS_SPE_COMP 0 234 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 235 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 236 #endif 237 238 /* We only set the TM feature if the kernel was compiled with TM supprt */ 239 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 240 #define CPU_FTR_TM_COMP CPU_FTR_TM 241 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM 242 #else 243 #define CPU_FTR_TM_COMP 0 244 #define PPC_FEATURE2_HTM_COMP 0 245 #endif 246 247 /* We need to mark all pages as being coherent if we're SMP or we have a 248 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 249 * require it for PCI "streaming/prefetch" to work properly. 250 * This is also required by 52xx family. 251 */ 252 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 253 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 254 || defined(CONFIG_PPC_MPC52xx) 255 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 256 #else 257 #define CPU_FTR_COMMON 0 258 #endif 259 260 /* The powersave features NAP & DOZE seems to confuse BDI when 261 debugging. So if a BDI is used, disable theses 262 */ 263 #ifndef CONFIG_BDI_SWITCH 264 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 265 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 266 #else 267 #define CPU_FTR_MAYBE_CAN_DOZE 0 268 #define CPU_FTR_MAYBE_CAN_NAP 0 269 #endif 270 271 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ 272 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ 273 !defined(CONFIG_BOOKE)) 274 275 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \ 276 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) 277 #define CPU_FTRS_603 (CPU_FTR_COMMON | \ 278 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 279 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 280 #define CPU_FTRS_604 (CPU_FTR_COMMON | \ 281 CPU_FTR_USE_TB | CPU_FTR_PPC_LE) 282 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 283 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 284 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 285 #define CPU_FTRS_740 (CPU_FTR_COMMON | \ 286 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 287 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 288 CPU_FTR_PPC_LE) 289 #define CPU_FTRS_750 (CPU_FTR_COMMON | \ 290 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 291 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 292 CPU_FTR_PPC_LE) 293 #define CPU_FTRS_750CL (CPU_FTRS_750) 294 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 295 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 296 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 297 #define CPU_FTRS_750GX (CPU_FTRS_750FX) 298 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 299 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 300 CPU_FTR_ALTIVEC_COMP | \ 301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 302 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 303 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 304 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 305 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 306 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 307 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 308 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 309 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 310 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 311 CPU_FTR_USE_TB | \ 312 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 313 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 314 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 315 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 316 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 317 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 318 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 319 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 320 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 321 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 322 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 323 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 324 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 325 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 326 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 327 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 328 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 329 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 330 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 331 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 332 CPU_FTR_USE_TB | \ 333 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 334 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 335 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 336 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 337 CPU_FTR_USE_TB | \ 338 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 339 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 340 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 341 CPU_FTR_NEED_PAIRED_STWCX) 342 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 343 CPU_FTR_USE_TB | \ 344 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 345 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 346 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 347 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 348 CPU_FTR_USE_TB | \ 349 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 350 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 351 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 352 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 353 CPU_FTR_USE_TB | \ 354 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 355 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 356 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 357 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ 358 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 359 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 360 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) 361 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 362 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 363 CPU_FTR_COMMON) 364 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 365 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 366 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) 367 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) 368 #define CPU_FTRS_8XX (CPU_FTR_USE_TB) 369 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 370 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 371 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 372 CPU_FTR_INDEXED_DCR) 373 #define CPU_FTRS_47X (CPU_FTRS_440x6) 374 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ 375 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 376 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \ 377 CPU_FTR_DEBUG_LVL_EXC) 378 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 379 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 380 CPU_FTR_NOEXECUTE) 381 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 382 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 383 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 384 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 385 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 386 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) 387 /* 388 * e5500/e6500 erratum A-006958 is a timebase bug that can use the 389 * same workaround as CPU_FTR_CELL_TB_BUG. 390 */ 391 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 392 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 393 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 394 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) 395 #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 396 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 397 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 398 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ 399 CPU_FTR_CELL_TB_BUG) 400 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 401 402 /* 64-bit CPUs */ 403 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \ 404 CPU_FTR_IABR | CPU_FTR_PPC_LE) 405 #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \ 406 CPU_FTR_IABR | \ 407 CPU_FTR_MMCRA | CPU_FTR_CTRL) 408 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 409 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 410 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \ 411 CPU_FTR_STCX_CHECKS_ADDRESS) 412 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 413 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \ 414 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 415 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ 416 CPU_FTR_HVMODE | CPU_FTR_DABRX) 417 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 418 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 419 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 420 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 421 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) 422 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 423 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 424 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 425 CPU_FTR_COHERENT_ICACHE | \ 426 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 427 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 428 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ 429 CPU_FTR_DABRX) 430 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 431 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 432 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 433 CPU_FTR_COHERENT_ICACHE | \ 434 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 435 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 436 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 437 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \ 438 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX) 439 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 440 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 441 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 442 CPU_FTR_COHERENT_ICACHE | \ 443 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 444 CPU_FTR_DSCR | CPU_FTR_SAO | \ 445 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 446 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 447 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 448 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP) 449 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG) 450 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 451 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 452 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 453 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 454 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) 455 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 456 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 457 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) 458 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 459 460 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ 461 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \ 462 CPU_FTR_ICSWX | CPU_FTR_DABRX ) 463 464 #ifdef __powerpc64__ 465 #ifdef CONFIG_PPC_BOOK3E 466 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2) 467 #else 468 #define CPU_FTRS_POSSIBLE \ 469 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 470 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 471 CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \ 472 CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_VSX) 473 #endif 474 #else 475 enum { 476 CPU_FTRS_POSSIBLE = 477 #if CLASSIC_PPC 478 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 479 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 480 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 481 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 482 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 483 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 484 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 485 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 486 CPU_FTRS_CLASSIC32 | 487 #else 488 CPU_FTRS_GENERIC_32 | 489 #endif 490 #ifdef CONFIG_8xx 491 CPU_FTRS_8XX | 492 #endif 493 #ifdef CONFIG_40x 494 CPU_FTRS_40X | 495 #endif 496 #ifdef CONFIG_44x 497 CPU_FTRS_44X | CPU_FTRS_440x6 | 498 #endif 499 #ifdef CONFIG_PPC_47x 500 CPU_FTRS_47X | CPU_FTR_476_DD2 | 501 #endif 502 #ifdef CONFIG_E200 503 CPU_FTRS_E200 | 504 #endif 505 #ifdef CONFIG_E500 506 CPU_FTRS_E500 | CPU_FTRS_E500_2 | 507 #endif 508 #ifdef CONFIG_PPC_E500MC 509 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | 510 #endif 511 0, 512 }; 513 #endif /* __powerpc64__ */ 514 515 #ifdef __powerpc64__ 516 #ifdef CONFIG_PPC_BOOK3E 517 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2) 518 #else 519 #define CPU_FTRS_ALWAYS \ 520 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ 521 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ 522 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) 523 #endif 524 #else 525 enum { 526 CPU_FTRS_ALWAYS = 527 #if CLASSIC_PPC 528 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 529 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 530 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 531 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 532 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 533 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 534 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 535 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 536 CPU_FTRS_CLASSIC32 & 537 #else 538 CPU_FTRS_GENERIC_32 & 539 #endif 540 #ifdef CONFIG_8xx 541 CPU_FTRS_8XX & 542 #endif 543 #ifdef CONFIG_40x 544 CPU_FTRS_40X & 545 #endif 546 #ifdef CONFIG_44x 547 CPU_FTRS_44X & CPU_FTRS_440x6 & 548 #endif 549 #ifdef CONFIG_E200 550 CPU_FTRS_E200 & 551 #endif 552 #ifdef CONFIG_E500 553 CPU_FTRS_E500 & CPU_FTRS_E500_2 & 554 #endif 555 #ifdef CONFIG_PPC_E500MC 556 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & 557 #endif 558 ~CPU_FTR_EMB_HV & /* can be removed at runtime */ 559 CPU_FTRS_POSSIBLE, 560 }; 561 #endif /* __powerpc64__ */ 562 563 static inline int cpu_has_feature(unsigned long feature) 564 { 565 return (CPU_FTRS_ALWAYS & feature) || 566 (CPU_FTRS_POSSIBLE 567 & cur_cpu_spec->cpu_features 568 & feature); 569 } 570 571 #define HBP_NUM 1 572 573 #endif /* !__ASSEMBLY__ */ 574 575 #endif /* __ASM_POWERPC_CPUTABLE_H */ 576