1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_POWERPC_CPUTABLE_H 3 #define __ASM_POWERPC_CPUTABLE_H 4 5 6 #include <linux/types.h> 7 #include <uapi/asm/cputable.h> 8 #include <asm/asm-const.h> 9 10 #ifndef __ASSEMBLY__ 11 12 /* This structure can grow, it's real size is used by head.S code 13 * via the mkdefs mechanism. 14 */ 15 struct cpu_spec; 16 17 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 18 typedef void (*cpu_restore_t)(void); 19 20 enum powerpc_oprofile_type { 21 PPC_OPROFILE_INVALID = 0, 22 PPC_OPROFILE_RS64 = 1, 23 PPC_OPROFILE_POWER4 = 2, 24 PPC_OPROFILE_G4 = 3, 25 PPC_OPROFILE_FSL_EMB = 4, 26 PPC_OPROFILE_CELL = 5, 27 PPC_OPROFILE_PA6T = 6, 28 }; 29 30 enum powerpc_pmc_type { 31 PPC_PMC_DEFAULT = 0, 32 PPC_PMC_IBM = 1, 33 PPC_PMC_PA6T = 2, 34 PPC_PMC_G4 = 3, 35 }; 36 37 struct pt_regs; 38 39 extern int machine_check_generic(struct pt_regs *regs); 40 extern int machine_check_4xx(struct pt_regs *regs); 41 extern int machine_check_440A(struct pt_regs *regs); 42 extern int machine_check_e500mc(struct pt_regs *regs); 43 extern int machine_check_e500(struct pt_regs *regs); 44 extern int machine_check_47x(struct pt_regs *regs); 45 int machine_check_8xx(struct pt_regs *regs); 46 int machine_check_83xx(struct pt_regs *regs); 47 48 extern void cpu_down_flush_e500v2(void); 49 extern void cpu_down_flush_e500mc(void); 50 extern void cpu_down_flush_e5500(void); 51 extern void cpu_down_flush_e6500(void); 52 53 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 54 struct cpu_spec { 55 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 56 unsigned int pvr_mask; 57 unsigned int pvr_value; 58 59 char *cpu_name; 60 unsigned long cpu_features; /* Kernel features */ 61 unsigned int cpu_user_features; /* Userland features */ 62 unsigned int cpu_user_features2; /* Userland features v2 */ 63 unsigned int mmu_features; /* MMU features */ 64 65 /* cache line sizes */ 66 unsigned int icache_bsize; 67 unsigned int dcache_bsize; 68 69 /* flush caches inside the current cpu */ 70 void (*cpu_down_flush)(void); 71 72 /* number of performance monitor counters */ 73 unsigned int num_pmcs; 74 enum powerpc_pmc_type pmc_type; 75 76 /* this is called to initialize various CPU bits like L1 cache, 77 * BHT, SPD, etc... from head.S before branching to identify_machine 78 */ 79 cpu_setup_t cpu_setup; 80 /* Used to restore cpu setup on secondary processors and at resume */ 81 cpu_restore_t cpu_restore; 82 83 /* Used by oprofile userspace to select the right counters */ 84 char *oprofile_cpu_type; 85 86 /* Processor specific oprofile operations */ 87 enum powerpc_oprofile_type oprofile_type; 88 89 /* Bit locations inside the mmcra change */ 90 unsigned long oprofile_mmcra_sihv; 91 unsigned long oprofile_mmcra_sipr; 92 93 /* Bits to clear during an oprofile exception */ 94 unsigned long oprofile_mmcra_clear; 95 96 /* Name of processor class, for the ELF AT_PLATFORM entry */ 97 char *platform; 98 99 /* Processor specific machine check handling. Return negative 100 * if the error is fatal, 1 if it was fully recovered and 0 to 101 * pass up (not CPU originated) */ 102 int (*machine_check)(struct pt_regs *regs); 103 104 /* 105 * Processor specific early machine check handler which is 106 * called in real mode to handle SLB and TLB errors. 107 */ 108 long (*machine_check_early)(struct pt_regs *regs); 109 }; 110 111 extern struct cpu_spec *cur_cpu_spec; 112 113 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 114 115 extern void set_cur_cpu_spec(struct cpu_spec *s); 116 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 117 extern void identify_cpu_name(unsigned int pvr); 118 extern void do_feature_fixups(unsigned long value, void *fixup_start, 119 void *fixup_end); 120 121 extern const char *powerpc_base_platform; 122 123 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 124 extern void cpu_feature_keys_init(void); 125 #else 126 static inline void cpu_feature_keys_init(void) { } 127 #endif 128 129 #endif /* __ASSEMBLY__ */ 130 131 /* CPU kernel features */ 132 133 /* Definitions for features that we have on both 32-bit and 64-bit chips */ 134 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) 135 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000002) 136 #define CPU_FTR_DBELL ASM_CONST(0x00000004) 137 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000008) 138 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010) 139 // ASM_CONST(0x00000020) Free 140 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040) 141 #define CPU_FTR_LWSYNC ASM_CONST(0x00000080) 142 #define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100) 143 #define CPU_FTR_EMB_HV ASM_CONST(0x00000200) 144 145 /* Definitions for features that only exist on 32-bit chips */ 146 #ifdef CONFIG_PPC32 147 #define CPU_FTR_L2CR ASM_CONST(0x00002000) 148 #define CPU_FTR_SPEC7450 ASM_CONST(0x00004000) 149 #define CPU_FTR_TAU ASM_CONST(0x00008000) 150 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000) 151 #define CPU_FTR_L3CR ASM_CONST(0x00040000) 152 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000) 153 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000) 154 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000) 155 #define CPU_FTR_NO_DPM ASM_CONST(0x00400000) 156 #define CPU_FTR_476_DD2 ASM_CONST(0x00800000) 157 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000) 158 #define CPU_FTR_NO_BTIC ASM_CONST(0x02000000) 159 #define CPU_FTR_PPC_LE ASM_CONST(0x04000000) 160 #define CPU_FTR_SPE ASM_CONST(0x10000000) 161 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000) 162 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000) 163 164 #else /* CONFIG_PPC32 */ 165 /* Define these to 0 for the sake of tests in common code */ 166 #define CPU_FTR_PPC_LE (0) 167 #define CPU_FTR_SPE (0) 168 #endif 169 170 /* 171 * Definitions for the 64-bit processor unique features; 172 * on 32-bit, make the names available but defined to be 0. 173 */ 174 #ifdef __powerpc64__ 175 #define LONG_ASM_CONST(x) ASM_CONST(x) 176 #else 177 #define LONG_ASM_CONST(x) 0 178 #endif 179 180 #define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000) 181 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000) 182 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000) 183 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000) 184 #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000) 185 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000) 186 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000) 187 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000) 188 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000) 189 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000) 190 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000) 191 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000) 192 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000) 193 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000) 194 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000) 195 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000) 196 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000) 197 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000) 198 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000) 199 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000) 200 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000) 201 /* LONG_ASM_CONST(0x0000000400000000) Free */ 202 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000) 203 #define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000) 204 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000) 205 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000) 206 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000) 207 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000) 208 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000) 209 #define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000) 210 #define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000) 211 #define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000) 212 #define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000) 213 #define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000) 214 #define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000) 215 #define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000) 216 #define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000) 217 #define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000) 218 219 #ifndef __ASSEMBLY__ 220 221 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE) 222 223 /* We only set the altivec features if the kernel was compiled with altivec 224 * support 225 */ 226 #ifdef CONFIG_ALTIVEC 227 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 228 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 229 #else 230 #define CPU_FTR_ALTIVEC_COMP 0 231 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 232 #endif 233 234 /* We only set the VSX features if the kernel was compiled with VSX 235 * support 236 */ 237 #ifdef CONFIG_VSX 238 #define CPU_FTR_VSX_COMP CPU_FTR_VSX 239 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 240 #else 241 #define CPU_FTR_VSX_COMP 0 242 #define PPC_FEATURE_HAS_VSX_COMP 0 243 #endif 244 245 /* We only set the spe features if the kernel was compiled with spe 246 * support 247 */ 248 #ifdef CONFIG_SPE 249 #define CPU_FTR_SPE_COMP CPU_FTR_SPE 250 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 251 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 252 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 253 #else 254 #define CPU_FTR_SPE_COMP 0 255 #define PPC_FEATURE_HAS_SPE_COMP 0 256 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 257 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 258 #endif 259 260 /* We only set the TM feature if the kernel was compiled with TM supprt */ 261 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 262 #define CPU_FTR_TM_COMP CPU_FTR_TM 263 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM 264 #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC 265 #else 266 #define CPU_FTR_TM_COMP 0 267 #define PPC_FEATURE2_HTM_COMP 0 268 #define PPC_FEATURE2_HTM_NOSC_COMP 0 269 #endif 270 271 /* We need to mark all pages as being coherent if we're SMP or we have a 272 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 273 * require it for PCI "streaming/prefetch" to work properly. 274 * This is also required by 52xx family. 275 */ 276 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 277 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 278 || defined(CONFIG_PPC_MPC52xx) 279 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 280 #else 281 #define CPU_FTR_COMMON 0 282 #endif 283 284 /* The powersave features NAP & DOZE seems to confuse BDI when 285 debugging. So if a BDI is used, disable theses 286 */ 287 #ifndef CONFIG_BDI_SWITCH 288 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 289 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 290 #else 291 #define CPU_FTR_MAYBE_CAN_DOZE 0 292 #define CPU_FTR_MAYBE_CAN_NAP 0 293 #endif 294 295 #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE) 297 #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE) 298 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 299 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 301 #define CPU_FTRS_740 (CPU_FTR_COMMON | \ 302 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 303 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 304 CPU_FTR_PPC_LE) 305 #define CPU_FTRS_750 (CPU_FTR_COMMON | \ 306 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 307 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 308 CPU_FTR_PPC_LE) 309 #define CPU_FTRS_750CL (CPU_FTRS_750) 310 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 311 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 312 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 313 #define CPU_FTRS_750GX (CPU_FTRS_750FX) 314 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 315 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 316 CPU_FTR_ALTIVEC_COMP | \ 317 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 318 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 319 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 320 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 321 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 322 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 323 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 324 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 325 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 326 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 327 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 328 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 329 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 330 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 331 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 332 CPU_FTR_NEED_PAIRED_STWCX | \ 333 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 334 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 335 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 336 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 337 CPU_FTR_NEED_PAIRED_STWCX | \ 338 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 339 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 340 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 341 CPU_FTR_NEED_PAIRED_STWCX | \ 342 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 343 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 344 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 345 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 346 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 347 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 348 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 349 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 350 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 351 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 352 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 353 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 354 CPU_FTR_NEED_PAIRED_STWCX) 355 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 356 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 357 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 358 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 359 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 360 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 361 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 362 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 363 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 364 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 365 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 366 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 367 #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE) 368 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 369 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE) 370 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 371 CPU_FTR_MAYBE_CAN_NAP | \ 372 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE) 373 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 374 CPU_FTR_MAYBE_CAN_NAP | \ 375 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE) 376 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON) 377 #define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE) 378 #define CPU_FTRS_40X (CPU_FTR_NOEXECUTE) 379 #define CPU_FTRS_44X (CPU_FTR_NOEXECUTE) 380 #define CPU_FTRS_440x6 (CPU_FTR_NOEXECUTE | \ 381 CPU_FTR_INDEXED_DCR) 382 #define CPU_FTRS_47X (CPU_FTRS_440x6) 383 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \ 384 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 385 CPU_FTR_NOEXECUTE) 386 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \ 387 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 388 CPU_FTR_NOEXECUTE) 389 #define CPU_FTRS_E500MC ( \ 390 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 391 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) 392 /* 393 * e5500/e6500 erratum A-006958 is a timebase bug that can use the 394 * same workaround as CPU_FTR_CELL_TB_BUG. 395 */ 396 #define CPU_FTRS_E5500 ( \ 397 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 398 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 399 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) 400 #define CPU_FTRS_E6500 ( \ 401 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 402 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 403 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ 404 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT) 405 406 /* 64-bit CPUs */ 407 #define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \ 408 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 409 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 410 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ 411 CPU_FTR_HVMODE | CPU_FTR_DABRX) 412 #define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \ 413 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 414 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 415 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 416 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) 417 #define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \ 418 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 419 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 420 CPU_FTR_COHERENT_ICACHE | \ 421 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 422 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 423 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ 424 CPU_FTR_DABRX) 425 #define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \ 426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 427 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 428 CPU_FTR_COHERENT_ICACHE | \ 429 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 430 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 431 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 432 CPU_FTR_CFAR | CPU_FTR_HVMODE | \ 433 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX ) 434 #define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \ 435 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 436 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 437 CPU_FTR_COHERENT_ICACHE | \ 438 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 439 CPU_FTR_DSCR | CPU_FTR_SAO | \ 440 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 441 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 442 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 443 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP ) 444 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG) 445 #define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \ 446 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 447 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 448 CPU_FTR_COHERENT_ICACHE | \ 449 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 450 CPU_FTR_DSCR | CPU_FTR_SAO | \ 451 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 452 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 453 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ 454 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \ 455 CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR) 456 #define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG) 457 #define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \ 458 CPU_FTR_P9_RADIX_PREFETCH_BUG | \ 459 CPU_FTR_POWER9_DD2_1) 460 #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \ 461 CPU_FTR_P9_TM_HV_ASSIST | \ 462 CPU_FTR_P9_TM_XER_SO_BUG) 463 #define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \ 464 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 465 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 466 CPU_FTR_COHERENT_ICACHE | \ 467 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 468 CPU_FTR_DSCR | CPU_FTR_SAO | \ 469 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 470 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 471 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ 472 CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \ 473 CPU_FTR_DAWR | CPU_FTR_DAWR1) 474 #define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \ 475 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 476 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 477 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 478 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) 479 #define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \ 480 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 481 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) 482 #define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2) 483 484 #ifdef CONFIG_PPC64 485 #ifdef CONFIG_PPC_BOOK3E 486 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500) 487 #else 488 #ifdef CONFIG_CPU_LITTLE_ENDIAN 489 #define CPU_FTRS_POSSIBLE \ 490 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \ 491 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \ 492 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10) 493 #else 494 #define CPU_FTRS_POSSIBLE \ 495 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \ 496 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \ 497 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ 498 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \ 499 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10) 500 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 501 #endif 502 #else 503 enum { 504 CPU_FTRS_POSSIBLE = 505 #ifdef CONFIG_PPC_BOOK3S_604 506 CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 507 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 508 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 509 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 510 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 511 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 512 CPU_FTRS_7447 | CPU_FTRS_7447A | 513 CPU_FTRS_CLASSIC32 | 514 #endif 515 #ifdef CONFIG_PPC_BOOK3S_603 516 CPU_FTRS_603 | CPU_FTRS_82XX | 517 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 518 #endif 519 #ifdef CONFIG_PPC_8xx 520 CPU_FTRS_8XX | 521 #endif 522 #ifdef CONFIG_40x 523 CPU_FTRS_40X | 524 #endif 525 #ifdef CONFIG_PPC_47x 526 CPU_FTRS_47X | CPU_FTR_476_DD2 | 527 #elif defined(CONFIG_44x) 528 CPU_FTRS_44X | CPU_FTRS_440x6 | 529 #endif 530 #ifdef CONFIG_E500 531 CPU_FTRS_E500 | CPU_FTRS_E500_2 | 532 #endif 533 #ifdef CONFIG_PPC_E500MC 534 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | 535 #endif 536 0, 537 }; 538 #endif /* __powerpc64__ */ 539 540 #ifdef CONFIG_PPC64 541 #ifdef CONFIG_PPC_BOOK3E 542 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500) 543 #else 544 545 #ifdef CONFIG_PPC_DT_CPU_FTRS 546 #define CPU_FTRS_DT_CPU_BASE \ 547 (CPU_FTR_LWSYNC | \ 548 CPU_FTR_FPU_UNAVAILABLE | \ 549 CPU_FTR_NOEXECUTE | \ 550 CPU_FTR_COHERENT_ICACHE | \ 551 CPU_FTR_STCX_CHECKS_ADDRESS | \ 552 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 553 CPU_FTR_DAWR | \ 554 CPU_FTR_ARCH_206 | \ 555 CPU_FTR_ARCH_207S) 556 #else 557 #define CPU_FTRS_DT_CPU_BASE (~0ul) 558 #endif 559 560 #ifdef CONFIG_CPU_LITTLE_ENDIAN 561 #define CPU_FTRS_ALWAYS \ 562 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \ 563 CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \ 564 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE) 565 #else 566 #define CPU_FTRS_ALWAYS \ 567 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \ 568 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \ 569 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \ 570 ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \ 571 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE) 572 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 573 #endif 574 #else 575 enum { 576 CPU_FTRS_ALWAYS = 577 #ifdef CONFIG_PPC_BOOK3S_604 578 CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 579 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 580 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 581 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 582 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 583 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 584 CPU_FTRS_7447 & CPU_FTRS_7447A & 585 CPU_FTRS_CLASSIC32 & 586 #endif 587 #ifdef CONFIG_PPC_BOOK3S_603 588 CPU_FTRS_603 & CPU_FTRS_82XX & 589 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 590 #endif 591 #ifdef CONFIG_PPC_8xx 592 CPU_FTRS_8XX & 593 #endif 594 #ifdef CONFIG_40x 595 CPU_FTRS_40X & 596 #endif 597 #ifdef CONFIG_PPC_47x 598 CPU_FTRS_47X & 599 #elif defined(CONFIG_44x) 600 CPU_FTRS_44X & CPU_FTRS_440x6 & 601 #endif 602 #ifdef CONFIG_E500 603 CPU_FTRS_E500 & CPU_FTRS_E500_2 & 604 #endif 605 #ifdef CONFIG_PPC_E500MC 606 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & 607 #endif 608 ~CPU_FTR_EMB_HV & /* can be removed at runtime */ 609 CPU_FTRS_POSSIBLE, 610 }; 611 #endif /* __powerpc64__ */ 612 613 /* 614 * Maximum number of hw breakpoint supported on powerpc. Number of 615 * breakpoints supported by actual hw might be less than this, which 616 * is decided at run time in nr_wp_slots(). 617 */ 618 #define HBP_NUM_MAX 2 619 620 #endif /* !__ASSEMBLY__ */ 621 622 #endif /* __ASM_POWERPC_CPUTABLE_H */ 623