1 #ifndef __ASM_POWERPC_CPUTABLE_H 2 #define __ASM_POWERPC_CPUTABLE_H 3 4 5 #include <asm/asm-compat.h> 6 #include <asm/feature-fixups.h> 7 #include <uapi/asm/cputable.h> 8 9 #ifndef __ASSEMBLY__ 10 11 /* This structure can grow, it's real size is used by head.S code 12 * via the mkdefs mechanism. 13 */ 14 struct cpu_spec; 15 16 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 17 typedef void (*cpu_restore_t)(void); 18 19 enum powerpc_oprofile_type { 20 PPC_OPROFILE_INVALID = 0, 21 PPC_OPROFILE_RS64 = 1, 22 PPC_OPROFILE_POWER4 = 2, 23 PPC_OPROFILE_G4 = 3, 24 PPC_OPROFILE_FSL_EMB = 4, 25 PPC_OPROFILE_CELL = 5, 26 PPC_OPROFILE_PA6T = 6, 27 }; 28 29 enum powerpc_pmc_type { 30 PPC_PMC_DEFAULT = 0, 31 PPC_PMC_IBM = 1, 32 PPC_PMC_PA6T = 2, 33 PPC_PMC_G4 = 3, 34 }; 35 36 struct pt_regs; 37 38 extern int machine_check_generic(struct pt_regs *regs); 39 extern int machine_check_4xx(struct pt_regs *regs); 40 extern int machine_check_440A(struct pt_regs *regs); 41 extern int machine_check_e500mc(struct pt_regs *regs); 42 extern int machine_check_e500(struct pt_regs *regs); 43 extern int machine_check_e200(struct pt_regs *regs); 44 extern int machine_check_47x(struct pt_regs *regs); 45 46 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 47 struct cpu_spec { 48 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 49 unsigned int pvr_mask; 50 unsigned int pvr_value; 51 52 char *cpu_name; 53 unsigned long cpu_features; /* Kernel features */ 54 unsigned int cpu_user_features; /* Userland features */ 55 unsigned int cpu_user_features2; /* Userland features v2 */ 56 unsigned int mmu_features; /* MMU features */ 57 58 /* cache line sizes */ 59 unsigned int icache_bsize; 60 unsigned int dcache_bsize; 61 62 /* number of performance monitor counters */ 63 unsigned int num_pmcs; 64 enum powerpc_pmc_type pmc_type; 65 66 /* this is called to initialize various CPU bits like L1 cache, 67 * BHT, SPD, etc... from head.S before branching to identify_machine 68 */ 69 cpu_setup_t cpu_setup; 70 /* Used to restore cpu setup on secondary processors and at resume */ 71 cpu_restore_t cpu_restore; 72 73 /* Used by oprofile userspace to select the right counters */ 74 char *oprofile_cpu_type; 75 76 /* Processor specific oprofile operations */ 77 enum powerpc_oprofile_type oprofile_type; 78 79 /* Bit locations inside the mmcra change */ 80 unsigned long oprofile_mmcra_sihv; 81 unsigned long oprofile_mmcra_sipr; 82 83 /* Bits to clear during an oprofile exception */ 84 unsigned long oprofile_mmcra_clear; 85 86 /* Name of processor class, for the ELF AT_PLATFORM entry */ 87 char *platform; 88 89 /* Processor specific machine check handling. Return negative 90 * if the error is fatal, 1 if it was fully recovered and 0 to 91 * pass up (not CPU originated) */ 92 int (*machine_check)(struct pt_regs *regs); 93 94 /* 95 * Processor specific early machine check handler which is 96 * called in real mode to handle SLB and TLB errors. 97 */ 98 long (*machine_check_early)(struct pt_regs *regs); 99 100 /* 101 * Processor specific routine to flush tlbs. 102 */ 103 void (*flush_tlb)(unsigned long inval_selector); 104 105 }; 106 107 extern struct cpu_spec *cur_cpu_spec; 108 109 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 110 111 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 112 extern void do_feature_fixups(unsigned long value, void *fixup_start, 113 void *fixup_end); 114 115 extern const char *powerpc_base_platform; 116 117 #endif /* __ASSEMBLY__ */ 118 119 /* CPU kernel features */ 120 121 /* Retain the 32b definitions all use bottom half of word */ 122 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) 123 #define CPU_FTR_L2CR ASM_CONST(0x00000002) 124 #define CPU_FTR_SPEC7450 ASM_CONST(0x00000004) 125 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000008) 126 #define CPU_FTR_TAU ASM_CONST(0x00000010) 127 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020) 128 #define CPU_FTR_USE_TB ASM_CONST(0x00000040) 129 #define CPU_FTR_L2CSR ASM_CONST(0x00000080) 130 #define CPU_FTR_601 ASM_CONST(0x00000100) 131 #define CPU_FTR_DBELL ASM_CONST(0x00000200) 132 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400) 133 #define CPU_FTR_L3CR ASM_CONST(0x00000800) 134 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000) 135 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000) 136 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000) 137 #define CPU_FTR_NO_DPM ASM_CONST(0x00008000) 138 #define CPU_FTR_476_DD2 ASM_CONST(0x00010000) 139 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000) 140 #define CPU_FTR_NO_BTIC ASM_CONST(0x00040000) 141 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000) 142 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000) 143 #define CPU_FTR_PPC_LE ASM_CONST(0x00200000) 144 #define CPU_FTR_REAL_LE ASM_CONST(0x00400000) 145 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000) 146 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000) 147 #define CPU_FTR_SPE ASM_CONST(0x02000000) 148 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000) 149 #define CPU_FTR_LWSYNC ASM_CONST(0x08000000) 150 #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000) 151 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000) 152 #define CPU_FTR_EMB_HV ASM_CONST(0x40000000) 153 154 /* 155 * Add the 64-bit processor unique features in the top half of the word; 156 * on 32-bit, make the names available but defined to be 0. 157 */ 158 #ifdef __powerpc64__ 159 #define LONG_ASM_CONST(x) ASM_CONST(x) 160 #else 161 #define LONG_ASM_CONST(x) 0 162 #endif 163 164 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000) 165 #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000) 166 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000) 167 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000) 168 #define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000) 169 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000) 170 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000) 171 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000) 172 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000) 173 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000) 174 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000) 175 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000) 176 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000) 177 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000) 178 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000) 179 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000) 180 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000) 181 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000) 182 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000) 183 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000) 184 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000) 185 #define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000) 186 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000) 187 #define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000) 188 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000) 189 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) 190 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) 191 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000) 192 193 #ifndef __ASSEMBLY__ 194 195 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 196 197 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \ 198 MMU_FTR_16M_PAGE) 199 200 /* We only set the altivec features if the kernel was compiled with altivec 201 * support 202 */ 203 #ifdef CONFIG_ALTIVEC 204 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 205 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 206 #else 207 #define CPU_FTR_ALTIVEC_COMP 0 208 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 209 #endif 210 211 /* We only set the VSX features if the kernel was compiled with VSX 212 * support 213 */ 214 #ifdef CONFIG_VSX 215 #define CPU_FTR_VSX_COMP CPU_FTR_VSX 216 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 217 #else 218 #define CPU_FTR_VSX_COMP 0 219 #define PPC_FEATURE_HAS_VSX_COMP 0 220 #endif 221 222 /* We only set the spe features if the kernel was compiled with spe 223 * support 224 */ 225 #ifdef CONFIG_SPE 226 #define CPU_FTR_SPE_COMP CPU_FTR_SPE 227 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 228 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 229 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 230 #else 231 #define CPU_FTR_SPE_COMP 0 232 #define PPC_FEATURE_HAS_SPE_COMP 0 233 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 234 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 235 #endif 236 237 /* We only set the TM feature if the kernel was compiled with TM supprt */ 238 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 239 #define CPU_FTR_TM_COMP CPU_FTR_TM 240 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM 241 #else 242 #define CPU_FTR_TM_COMP 0 243 #define PPC_FEATURE2_HTM_COMP 0 244 #endif 245 246 /* We need to mark all pages as being coherent if we're SMP or we have a 247 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 248 * require it for PCI "streaming/prefetch" to work properly. 249 * This is also required by 52xx family. 250 */ 251 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 252 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 253 || defined(CONFIG_PPC_MPC52xx) 254 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 255 #else 256 #define CPU_FTR_COMMON 0 257 #endif 258 259 /* The powersave features NAP & DOZE seems to confuse BDI when 260 debugging. So if a BDI is used, disable theses 261 */ 262 #ifndef CONFIG_BDI_SWITCH 263 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 264 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 265 #else 266 #define CPU_FTR_MAYBE_CAN_DOZE 0 267 #define CPU_FTR_MAYBE_CAN_NAP 0 268 #endif 269 270 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ 271 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ 272 !defined(CONFIG_BOOKE)) 273 274 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \ 275 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) 276 #define CPU_FTRS_603 (CPU_FTR_COMMON | \ 277 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 278 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 279 #define CPU_FTRS_604 (CPU_FTR_COMMON | \ 280 CPU_FTR_USE_TB | CPU_FTR_PPC_LE) 281 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 282 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 283 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 284 #define CPU_FTRS_740 (CPU_FTR_COMMON | \ 285 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 286 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 287 CPU_FTR_PPC_LE) 288 #define CPU_FTRS_750 (CPU_FTR_COMMON | \ 289 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 290 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 291 CPU_FTR_PPC_LE) 292 #define CPU_FTRS_750CL (CPU_FTRS_750) 293 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 294 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 295 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 296 #define CPU_FTRS_750GX (CPU_FTRS_750FX) 297 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 298 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 299 CPU_FTR_ALTIVEC_COMP | \ 300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 301 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 302 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 303 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 304 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 305 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 306 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 307 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 308 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 309 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 310 CPU_FTR_USE_TB | \ 311 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 312 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 313 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 314 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 315 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 316 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 317 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 318 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 319 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 320 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 321 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 322 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 323 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 324 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 325 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 326 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 327 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 328 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 329 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 330 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 331 CPU_FTR_USE_TB | \ 332 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 333 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 334 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 335 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 336 CPU_FTR_USE_TB | \ 337 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 338 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 339 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 340 CPU_FTR_NEED_PAIRED_STWCX) 341 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 342 CPU_FTR_USE_TB | \ 343 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 344 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 345 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 346 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 347 CPU_FTR_USE_TB | \ 348 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 349 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 350 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 351 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 352 CPU_FTR_USE_TB | \ 353 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 354 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 355 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 356 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ 357 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 358 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 359 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) 360 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 361 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 362 CPU_FTR_COMMON) 363 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 364 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 365 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) 366 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) 367 #define CPU_FTRS_8XX (CPU_FTR_USE_TB) 368 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 369 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 370 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 371 CPU_FTR_INDEXED_DCR) 372 #define CPU_FTRS_47X (CPU_FTRS_440x6) 373 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ 374 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 375 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \ 376 CPU_FTR_DEBUG_LVL_EXC) 377 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 378 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 379 CPU_FTR_NOEXECUTE) 380 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 381 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 382 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 383 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 384 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 385 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) 386 /* 387 * e5500/e6500 erratum A-006958 is a timebase bug that can use the 388 * same workaround as CPU_FTR_CELL_TB_BUG. 389 */ 390 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 391 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 392 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 393 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) 394 #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 395 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 396 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 397 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ 398 CPU_FTR_CELL_TB_BUG) 399 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 400 401 /* 64-bit CPUs */ 402 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \ 403 CPU_FTR_IABR | CPU_FTR_PPC_LE) 404 #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \ 405 CPU_FTR_IABR | \ 406 CPU_FTR_MMCRA | CPU_FTR_CTRL) 407 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 408 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 409 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \ 410 CPU_FTR_STCX_CHECKS_ADDRESS) 411 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 412 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \ 413 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 414 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ 415 CPU_FTR_HVMODE | CPU_FTR_DABRX) 416 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 417 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 418 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 419 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 420 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) 421 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 422 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 423 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 424 CPU_FTR_COHERENT_ICACHE | \ 425 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 426 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 427 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ 428 CPU_FTR_DABRX) 429 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 430 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 431 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 432 CPU_FTR_COHERENT_ICACHE | \ 433 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 434 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 435 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 436 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \ 437 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX) 438 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 439 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 440 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 441 CPU_FTR_COHERENT_ICACHE | \ 442 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 443 CPU_FTR_DSCR | CPU_FTR_SAO | \ 444 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 445 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 446 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 447 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP) 448 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 449 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 450 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 451 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 452 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) 453 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 454 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 455 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) 456 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 457 458 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ 459 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \ 460 CPU_FTR_ICSWX | CPU_FTR_DABRX ) 461 462 #ifdef __powerpc64__ 463 #ifdef CONFIG_PPC_BOOK3E 464 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2) 465 #else 466 #define CPU_FTRS_POSSIBLE \ 467 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 468 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 469 CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL | \ 470 CPU_FTRS_PA6T | CPU_FTR_VSX) 471 #endif 472 #else 473 enum { 474 CPU_FTRS_POSSIBLE = 475 #if CLASSIC_PPC 476 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 477 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 478 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 479 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 480 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 481 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 482 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 483 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 484 CPU_FTRS_CLASSIC32 | 485 #else 486 CPU_FTRS_GENERIC_32 | 487 #endif 488 #ifdef CONFIG_8xx 489 CPU_FTRS_8XX | 490 #endif 491 #ifdef CONFIG_40x 492 CPU_FTRS_40X | 493 #endif 494 #ifdef CONFIG_44x 495 CPU_FTRS_44X | CPU_FTRS_440x6 | 496 #endif 497 #ifdef CONFIG_PPC_47x 498 CPU_FTRS_47X | CPU_FTR_476_DD2 | 499 #endif 500 #ifdef CONFIG_E200 501 CPU_FTRS_E200 | 502 #endif 503 #ifdef CONFIG_E500 504 CPU_FTRS_E500 | CPU_FTRS_E500_2 | 505 #endif 506 #ifdef CONFIG_PPC_E500MC 507 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | 508 #endif 509 0, 510 }; 511 #endif /* __powerpc64__ */ 512 513 #ifdef __powerpc64__ 514 #ifdef CONFIG_PPC_BOOK3E 515 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2) 516 #else 517 #define CPU_FTRS_ALWAYS \ 518 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ 519 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ 520 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) 521 #endif 522 #else 523 enum { 524 CPU_FTRS_ALWAYS = 525 #if CLASSIC_PPC 526 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 527 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 528 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 529 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 530 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 531 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 532 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 533 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 534 CPU_FTRS_CLASSIC32 & 535 #else 536 CPU_FTRS_GENERIC_32 & 537 #endif 538 #ifdef CONFIG_8xx 539 CPU_FTRS_8XX & 540 #endif 541 #ifdef CONFIG_40x 542 CPU_FTRS_40X & 543 #endif 544 #ifdef CONFIG_44x 545 CPU_FTRS_44X & CPU_FTRS_440x6 & 546 #endif 547 #ifdef CONFIG_E200 548 CPU_FTRS_E200 & 549 #endif 550 #ifdef CONFIG_E500 551 CPU_FTRS_E500 & CPU_FTRS_E500_2 & 552 #endif 553 #ifdef CONFIG_PPC_E500MC 554 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & 555 #endif 556 ~CPU_FTR_EMB_HV & /* can be removed at runtime */ 557 CPU_FTRS_POSSIBLE, 558 }; 559 #endif /* __powerpc64__ */ 560 561 static inline int cpu_has_feature(unsigned long feature) 562 { 563 return (CPU_FTRS_ALWAYS & feature) || 564 (CPU_FTRS_POSSIBLE 565 & cur_cpu_spec->cpu_features 566 & feature); 567 } 568 569 #define HBP_NUM 1 570 571 #endif /* !__ASSEMBLY__ */ 572 573 #endif /* __ASM_POWERPC_CPUTABLE_H */ 574