1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
3 
4 
5 #include <asm/asm-compat.h>
6 #include <asm/feature-fixups.h>
7 #include <uapi/asm/cputable.h>
8 
9 #ifndef __ASSEMBLY__
10 
11 /* This structure can grow, it's real size is used by head.S code
12  * via the mkdefs mechanism.
13  */
14 struct cpu_spec;
15 
16 typedef	void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
17 typedef	void (*cpu_restore_t)(void);
18 
19 enum powerpc_oprofile_type {
20 	PPC_OPROFILE_INVALID = 0,
21 	PPC_OPROFILE_RS64 = 1,
22 	PPC_OPROFILE_POWER4 = 2,
23 	PPC_OPROFILE_G4 = 3,
24 	PPC_OPROFILE_FSL_EMB = 4,
25 	PPC_OPROFILE_CELL = 5,
26 	PPC_OPROFILE_PA6T = 6,
27 };
28 
29 enum powerpc_pmc_type {
30 	PPC_PMC_DEFAULT = 0,
31 	PPC_PMC_IBM = 1,
32 	PPC_PMC_PA6T = 2,
33 	PPC_PMC_G4 = 3,
34 };
35 
36 struct pt_regs;
37 
38 extern int machine_check_generic(struct pt_regs *regs);
39 extern int machine_check_4xx(struct pt_regs *regs);
40 extern int machine_check_440A(struct pt_regs *regs);
41 extern int machine_check_e500mc(struct pt_regs *regs);
42 extern int machine_check_e500(struct pt_regs *regs);
43 extern int machine_check_e200(struct pt_regs *regs);
44 extern int machine_check_47x(struct pt_regs *regs);
45 
46 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
47 struct cpu_spec {
48 	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
49 	unsigned int	pvr_mask;
50 	unsigned int	pvr_value;
51 
52 	char		*cpu_name;
53 	unsigned long	cpu_features;		/* Kernel features */
54 	unsigned int	cpu_user_features;	/* Userland features */
55 	unsigned int	cpu_user_features2;	/* Userland features v2 */
56 	unsigned int	mmu_features;		/* MMU features */
57 
58 	/* cache line sizes */
59 	unsigned int	icache_bsize;
60 	unsigned int	dcache_bsize;
61 
62 	/* number of performance monitor counters */
63 	unsigned int	num_pmcs;
64 	enum powerpc_pmc_type pmc_type;
65 
66 	/* this is called to initialize various CPU bits like L1 cache,
67 	 * BHT, SPD, etc... from head.S before branching to identify_machine
68 	 */
69 	cpu_setup_t	cpu_setup;
70 	/* Used to restore cpu setup on secondary processors and at resume */
71 	cpu_restore_t	cpu_restore;
72 
73 	/* Used by oprofile userspace to select the right counters */
74 	char		*oprofile_cpu_type;
75 
76 	/* Processor specific oprofile operations */
77 	enum powerpc_oprofile_type oprofile_type;
78 
79 	/* Bit locations inside the mmcra change */
80 	unsigned long	oprofile_mmcra_sihv;
81 	unsigned long	oprofile_mmcra_sipr;
82 
83 	/* Bits to clear during an oprofile exception */
84 	unsigned long	oprofile_mmcra_clear;
85 
86 	/* Name of processor class, for the ELF AT_PLATFORM entry */
87 	char		*platform;
88 
89 	/* Processor specific machine check handling. Return negative
90 	 * if the error is fatal, 1 if it was fully recovered and 0 to
91 	 * pass up (not CPU originated) */
92 	int		(*machine_check)(struct pt_regs *regs);
93 };
94 
95 extern struct cpu_spec		*cur_cpu_spec;
96 
97 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
98 
99 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
100 extern void do_feature_fixups(unsigned long value, void *fixup_start,
101 			      void *fixup_end);
102 
103 extern const char *powerpc_base_platform;
104 
105 #endif /* __ASSEMBLY__ */
106 
107 /* CPU kernel features */
108 
109 /* Retain the 32b definitions all use bottom half of word */
110 #define CPU_FTR_COHERENT_ICACHE		ASM_CONST(0x00000001)
111 #define CPU_FTR_L2CR			ASM_CONST(0x00000002)
112 #define CPU_FTR_SPEC7450		ASM_CONST(0x00000004)
113 #define CPU_FTR_ALTIVEC			ASM_CONST(0x00000008)
114 #define CPU_FTR_TAU			ASM_CONST(0x00000010)
115 #define CPU_FTR_CAN_DOZE		ASM_CONST(0x00000020)
116 #define CPU_FTR_USE_TB			ASM_CONST(0x00000040)
117 #define CPU_FTR_L2CSR			ASM_CONST(0x00000080)
118 #define CPU_FTR_601			ASM_CONST(0x00000100)
119 #define CPU_FTR_DBELL			ASM_CONST(0x00000200)
120 #define CPU_FTR_CAN_NAP			ASM_CONST(0x00000400)
121 #define CPU_FTR_L3CR			ASM_CONST(0x00000800)
122 #define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x00001000)
123 #define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x00002000)
124 #define CPU_FTR_DUAL_PLL_750FX		ASM_CONST(0x00004000)
125 #define CPU_FTR_NO_DPM			ASM_CONST(0x00008000)
126 #define CPU_FTR_476_DD2			ASM_CONST(0x00010000)
127 #define CPU_FTR_NEED_COHERENT		ASM_CONST(0x00020000)
128 #define CPU_FTR_NO_BTIC			ASM_CONST(0x00040000)
129 #define CPU_FTR_DEBUG_LVL_EXC		ASM_CONST(0x00080000)
130 #define CPU_FTR_NODSISRALIGN		ASM_CONST(0x00100000)
131 #define CPU_FTR_PPC_LE			ASM_CONST(0x00200000)
132 #define CPU_FTR_REAL_LE			ASM_CONST(0x00400000)
133 #define CPU_FTR_FPU_UNAVAILABLE		ASM_CONST(0x00800000)
134 #define CPU_FTR_UNIFIED_ID_CACHE	ASM_CONST(0x01000000)
135 #define CPU_FTR_SPE			ASM_CONST(0x02000000)
136 #define CPU_FTR_NEED_PAIRED_STWCX	ASM_CONST(0x04000000)
137 #define CPU_FTR_LWSYNC			ASM_CONST(0x08000000)
138 #define CPU_FTR_NOEXECUTE		ASM_CONST(0x10000000)
139 #define CPU_FTR_INDEXED_DCR		ASM_CONST(0x20000000)
140 #define CPU_FTR_EMB_HV			ASM_CONST(0x40000000)
141 
142 /*
143  * Add the 64-bit processor unique features in the top half of the word;
144  * on 32-bit, make the names available but defined to be 0.
145  */
146 #ifdef __powerpc64__
147 #define LONG_ASM_CONST(x)		ASM_CONST(x)
148 #else
149 #define LONG_ASM_CONST(x)		0
150 #endif
151 
152 #define CPU_FTR_HVMODE			LONG_ASM_CONST(0x0000000100000000)
153 #define CPU_FTR_ARCH_201		LONG_ASM_CONST(0x0000000200000000)
154 #define CPU_FTR_ARCH_206		LONG_ASM_CONST(0x0000000400000000)
155 #define CPU_FTR_ARCH_207S		LONG_ASM_CONST(0x0000000800000000)
156 #define CPU_FTR_IABR			LONG_ASM_CONST(0x0000001000000000)
157 #define CPU_FTR_MMCRA			LONG_ASM_CONST(0x0000002000000000)
158 #define CPU_FTR_CTRL			LONG_ASM_CONST(0x0000004000000000)
159 #define CPU_FTR_SMT			LONG_ASM_CONST(0x0000008000000000)
160 #define CPU_FTR_PAUSE_ZERO		LONG_ASM_CONST(0x0000010000000000)
161 #define CPU_FTR_PURR			LONG_ASM_CONST(0x0000020000000000)
162 #define CPU_FTR_CELL_TB_BUG		LONG_ASM_CONST(0x0000040000000000)
163 #define CPU_FTR_SPURR			LONG_ASM_CONST(0x0000080000000000)
164 #define CPU_FTR_DSCR			LONG_ASM_CONST(0x0000100000000000)
165 #define CPU_FTR_VSX			LONG_ASM_CONST(0x0000200000000000)
166 #define CPU_FTR_SAO			LONG_ASM_CONST(0x0000400000000000)
167 #define CPU_FTR_CP_USE_DCBTZ		LONG_ASM_CONST(0x0000800000000000)
168 #define CPU_FTR_UNALIGNED_LD_STD	LONG_ASM_CONST(0x0001000000000000)
169 #define CPU_FTR_ASYM_SMT		LONG_ASM_CONST(0x0002000000000000)
170 #define CPU_FTR_STCX_CHECKS_ADDRESS	LONG_ASM_CONST(0x0004000000000000)
171 #define CPU_FTR_POPCNTB			LONG_ASM_CONST(0x0008000000000000)
172 #define CPU_FTR_POPCNTD			LONG_ASM_CONST(0x0010000000000000)
173 #define CPU_FTR_ICSWX			LONG_ASM_CONST(0x0020000000000000)
174 #define CPU_FTR_VMX_COPY		LONG_ASM_CONST(0x0040000000000000)
175 #define CPU_FTR_TM			LONG_ASM_CONST(0x0080000000000000)
176 #define CPU_FTR_CFAR			LONG_ASM_CONST(0x0100000000000000)
177 #define	CPU_FTR_HAS_PPR			LONG_ASM_CONST(0x0200000000000000)
178 #define CPU_FTR_DAWR			LONG_ASM_CONST(0x0400000000000000)
179 #define CPU_FTR_DABRX			LONG_ASM_CONST(0x0800000000000000)
180 
181 #ifndef __ASSEMBLY__
182 
183 #define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
184 
185 #define MMU_FTR_PPCAS_ARCH_V2 	(MMU_FTR_SLB | MMU_FTR_TLBIEL | \
186 				 MMU_FTR_16M_PAGE)
187 
188 /* We only set the altivec features if the kernel was compiled with altivec
189  * support
190  */
191 #ifdef CONFIG_ALTIVEC
192 #define CPU_FTR_ALTIVEC_COMP	CPU_FTR_ALTIVEC
193 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
194 #else
195 #define CPU_FTR_ALTIVEC_COMP	0
196 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
197 #endif
198 
199 /* We only set the VSX features if the kernel was compiled with VSX
200  * support
201  */
202 #ifdef CONFIG_VSX
203 #define CPU_FTR_VSX_COMP	CPU_FTR_VSX
204 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
205 #else
206 #define CPU_FTR_VSX_COMP	0
207 #define PPC_FEATURE_HAS_VSX_COMP    0
208 #endif
209 
210 /* We only set the spe features if the kernel was compiled with spe
211  * support
212  */
213 #ifdef CONFIG_SPE
214 #define CPU_FTR_SPE_COMP	CPU_FTR_SPE
215 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
216 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
217 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
218 #else
219 #define CPU_FTR_SPE_COMP	0
220 #define PPC_FEATURE_HAS_SPE_COMP    0
221 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
222 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
223 #endif
224 
225 /* We only set the TM feature if the kernel was compiled with TM supprt */
226 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
227 #define CPU_FTR_TM_COMP		CPU_FTR_TM
228 #define PPC_FEATURE2_HTM_COMP	PPC_FEATURE2_HTM
229 #else
230 #define CPU_FTR_TM_COMP		0
231 #define PPC_FEATURE2_HTM_COMP	0
232 #endif
233 
234 /* We need to mark all pages as being coherent if we're SMP or we have a
235  * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
236  * require it for PCI "streaming/prefetch" to work properly.
237  * This is also required by 52xx family.
238  */
239 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
240 	|| defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
241 	|| defined(CONFIG_PPC_MPC52xx)
242 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
243 #else
244 #define CPU_FTR_COMMON                  0
245 #endif
246 
247 /* The powersave features NAP & DOZE seems to confuse BDI when
248    debugging. So if a BDI is used, disable theses
249  */
250 #ifndef CONFIG_BDI_SWITCH
251 #define CPU_FTR_MAYBE_CAN_DOZE	CPU_FTR_CAN_DOZE
252 #define CPU_FTR_MAYBE_CAN_NAP	CPU_FTR_CAN_NAP
253 #else
254 #define CPU_FTR_MAYBE_CAN_DOZE	0
255 #define CPU_FTR_MAYBE_CAN_NAP	0
256 #endif
257 
258 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
259 		     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
260 		     !defined(CONFIG_BOOKE))
261 
262 #define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | \
263 	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
264 #define CPU_FTRS_603	(CPU_FTR_COMMON | \
265 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
266 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
267 #define CPU_FTRS_604	(CPU_FTR_COMMON | \
268 	    CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
269 #define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | \
270 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
271 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
272 #define CPU_FTRS_740	(CPU_FTR_COMMON | \
273 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
274 	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
275 	    CPU_FTR_PPC_LE)
276 #define CPU_FTRS_750	(CPU_FTR_COMMON | \
277 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
278 	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
279 	    CPU_FTR_PPC_LE)
280 #define CPU_FTRS_750CL	(CPU_FTRS_750)
281 #define CPU_FTRS_750FX1	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
282 #define CPU_FTRS_750FX2	(CPU_FTRS_750 | CPU_FTR_NO_DPM)
283 #define CPU_FTRS_750FX	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
284 #define CPU_FTRS_750GX	(CPU_FTRS_750FX)
285 #define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | \
286 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
287 	    CPU_FTR_ALTIVEC_COMP | \
288 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
289 #define CPU_FTRS_7400	(CPU_FTR_COMMON | \
290 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
291 	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
292 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
293 #define CPU_FTRS_7450_20	(CPU_FTR_COMMON | \
294 	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
295 	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
296 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
297 #define CPU_FTRS_7450_21	(CPU_FTR_COMMON | \
298 	    CPU_FTR_USE_TB | \
299 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
300 	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
301 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
302 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
303 #define CPU_FTRS_7450_23	(CPU_FTR_COMMON | \
304 	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
305 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
306 	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
307 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
308 #define CPU_FTRS_7455_1	(CPU_FTR_COMMON | \
309 	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
310 	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
311 	    CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
312 #define CPU_FTRS_7455_20	(CPU_FTR_COMMON | \
313 	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
314 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
315 	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
316 	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
317 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
318 #define CPU_FTRS_7455	(CPU_FTR_COMMON | \
319 	    CPU_FTR_USE_TB | \
320 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
321 	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
322 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
323 #define CPU_FTRS_7447_10	(CPU_FTR_COMMON | \
324 	    CPU_FTR_USE_TB | \
325 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
326 	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
327 	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
328 	    CPU_FTR_NEED_PAIRED_STWCX)
329 #define CPU_FTRS_7447	(CPU_FTR_COMMON | \
330 	    CPU_FTR_USE_TB | \
331 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
332 	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
333 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
334 #define CPU_FTRS_7447A	(CPU_FTR_COMMON | \
335 	    CPU_FTR_USE_TB | \
336 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
337 	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
338 	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
339 #define CPU_FTRS_7448	(CPU_FTR_COMMON | \
340 	    CPU_FTR_USE_TB | \
341 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
342 	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
343 	    CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
344 #define CPU_FTRS_82XX	(CPU_FTR_COMMON | \
345 	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
346 #define CPU_FTRS_G2_LE	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
347 	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
348 #define CPU_FTRS_E300	(CPU_FTR_MAYBE_CAN_DOZE | \
349 	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
350 	    CPU_FTR_COMMON)
351 #define CPU_FTRS_E300C2	(CPU_FTR_MAYBE_CAN_DOZE | \
352 	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
353 	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
354 #define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | CPU_FTR_USE_TB)
355 #define CPU_FTRS_8XX	(CPU_FTR_USE_TB)
356 #define CPU_FTRS_40X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
357 #define CPU_FTRS_44X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
358 #define CPU_FTRS_440x6	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
359 	    CPU_FTR_INDEXED_DCR)
360 #define CPU_FTRS_47X	(CPU_FTRS_440x6)
361 #define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
362 	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
363 	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
364 	    CPU_FTR_DEBUG_LVL_EXC)
365 #define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
366 	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
367 	    CPU_FTR_NOEXECUTE)
368 #define CPU_FTRS_E500_2	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
369 	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
370 	    CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
371 #define CPU_FTRS_E500MC	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
372 	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
373 	    CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
374 /*
375  * e5500/e6500 erratum A-006958 is a timebase bug that can use the
376  * same workaround as CPU_FTR_CELL_TB_BUG.
377  */
378 #define CPU_FTRS_E5500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
379 	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
380 	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
381 	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
382 #define CPU_FTRS_E6500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
383 	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
384 	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
385 	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
386 	    CPU_FTR_CELL_TB_BUG)
387 #define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
388 
389 /* 64-bit CPUs */
390 #define CPU_FTRS_POWER3	(CPU_FTR_USE_TB | \
391 	    CPU_FTR_IABR | CPU_FTR_PPC_LE)
392 #define CPU_FTRS_RS64	(CPU_FTR_USE_TB | \
393 	    CPU_FTR_IABR | \
394 	    CPU_FTR_MMCRA | CPU_FTR_CTRL)
395 #define CPU_FTRS_POWER4	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
396 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
397 	    CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
398 	    CPU_FTR_STCX_CHECKS_ADDRESS)
399 #define CPU_FTRS_PPC970	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
400 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
401 	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
402 	    CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
403 	    CPU_FTR_HVMODE | CPU_FTR_DABRX)
404 #define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
405 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
406 	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
407 	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
408 	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
409 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
410 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
411 	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
412 	    CPU_FTR_COHERENT_ICACHE | \
413 	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
414 	    CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
415 	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
416 	    CPU_FTR_DABRX)
417 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
418 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
419 	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
420 	    CPU_FTR_COHERENT_ICACHE | \
421 	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
422 	    CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
423 	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
424 	    CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
425 	    CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
426 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
427 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
428 	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
429 	    CPU_FTR_COHERENT_ICACHE | \
430 	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
431 	    CPU_FTR_DSCR | CPU_FTR_SAO  | \
432 	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
433 	    CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
434 	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
435 	    CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
436 #define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
437 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
438 	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
439 	    CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
440 	    CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
441 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
442 	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
443 	    CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
444 #define CPU_FTRS_COMPATIBLE	(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
445 
446 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
447 		     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
448 		     CPU_FTR_ICSWX | CPU_FTR_DABRX )
449 
450 #ifdef __powerpc64__
451 #ifdef CONFIG_PPC_BOOK3E
452 #define CPU_FTRS_POSSIBLE	(CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
453 #else
454 #define CPU_FTRS_POSSIBLE	\
455 	    (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |	\
456 	    CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |	\
457 	    CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL |		\
458 	    CPU_FTRS_PA6T | CPU_FTR_VSX)
459 #endif
460 #else
461 enum {
462 	CPU_FTRS_POSSIBLE =
463 #if CLASSIC_PPC
464 	    CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
465 	    CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
466 	    CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
467 	    CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
468 	    CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
469 	    CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
470 	    CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
471 	    CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
472 	    CPU_FTRS_CLASSIC32 |
473 #else
474 	    CPU_FTRS_GENERIC_32 |
475 #endif
476 #ifdef CONFIG_8xx
477 	    CPU_FTRS_8XX |
478 #endif
479 #ifdef CONFIG_40x
480 	    CPU_FTRS_40X |
481 #endif
482 #ifdef CONFIG_44x
483 	    CPU_FTRS_44X | CPU_FTRS_440x6 |
484 #endif
485 #ifdef CONFIG_PPC_47x
486 	    CPU_FTRS_47X | CPU_FTR_476_DD2 |
487 #endif
488 #ifdef CONFIG_E200
489 	    CPU_FTRS_E200 |
490 #endif
491 #ifdef CONFIG_E500
492 	    CPU_FTRS_E500 | CPU_FTRS_E500_2 |
493 #endif
494 #ifdef CONFIG_PPC_E500MC
495 	    CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
496 #endif
497 	    0,
498 };
499 #endif /* __powerpc64__ */
500 
501 #ifdef __powerpc64__
502 #ifdef CONFIG_PPC_BOOK3E
503 #define CPU_FTRS_ALWAYS		(CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
504 #else
505 #define CPU_FTRS_ALWAYS		\
506 	    (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &	\
507 	    CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &	\
508 	    CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
509 #endif
510 #else
511 enum {
512 	CPU_FTRS_ALWAYS =
513 #if CLASSIC_PPC
514 	    CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
515 	    CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
516 	    CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
517 	    CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
518 	    CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
519 	    CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
520 	    CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
521 	    CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
522 	    CPU_FTRS_CLASSIC32 &
523 #else
524 	    CPU_FTRS_GENERIC_32 &
525 #endif
526 #ifdef CONFIG_8xx
527 	    CPU_FTRS_8XX &
528 #endif
529 #ifdef CONFIG_40x
530 	    CPU_FTRS_40X &
531 #endif
532 #ifdef CONFIG_44x
533 	    CPU_FTRS_44X & CPU_FTRS_440x6 &
534 #endif
535 #ifdef CONFIG_E200
536 	    CPU_FTRS_E200 &
537 #endif
538 #ifdef CONFIG_E500
539 	    CPU_FTRS_E500 & CPU_FTRS_E500_2 &
540 #endif
541 #ifdef CONFIG_PPC_E500MC
542 	    CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
543 #endif
544 	    ~CPU_FTR_EMB_HV &	/* can be removed at runtime */
545 	    CPU_FTRS_POSSIBLE,
546 };
547 #endif /* __powerpc64__ */
548 
549 static inline int cpu_has_feature(unsigned long feature)
550 {
551 	return (CPU_FTRS_ALWAYS & feature) ||
552 	       (CPU_FTRS_POSSIBLE
553 		& cur_cpu_spec->cpu_features
554 		& feature);
555 }
556 
557 #define HBP_NUM 1
558 
559 #endif /* !__ASSEMBLY__ */
560 
561 #endif /* __ASM_POWERPC_CPUTABLE_H */
562