1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_CPUIDLE_H 3 #define _ASM_POWERPC_CPUIDLE_H 4 5 #ifdef CONFIG_PPC_POWERNV 6 /* Thread state used in powernv idle state management */ 7 #define PNV_THREAD_RUNNING 0 8 #define PNV_THREAD_NAP 1 9 #define PNV_THREAD_SLEEP 2 10 #define PNV_THREAD_WINKLE 3 11 12 /* 13 * Core state used in powernv idle for POWER8. 14 * 15 * The lock bit synchronizes updates to the state, as well as parts of the 16 * sleep/wake code (see kernel/idle_book3s.S). 17 * 18 * Bottom 8 bits track the idle state of each thread. Bit is cleared before 19 * the thread executes an idle instruction (nap/sleep/winkle). 20 * 21 * Then there is winkle tracking. A core does not lose complete state 22 * until every thread is in winkle. So the winkle count field counts the 23 * number of threads in winkle (small window of false positives is okay 24 * around the sleep/wake, so long as there are no false negatives). 25 * 26 * When the winkle count reaches 8 (the COUNT_ALL_BIT becomes set), then 27 * the THREAD_WINKLE_BITS are set, which indicate which threads have not 28 * yet woken from the winkle state. 29 */ 30 #define PNV_CORE_IDLE_LOCK_BIT 0x10000000 31 32 #define PNV_CORE_IDLE_WINKLE_COUNT 0x00010000 33 #define PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT 0x00080000 34 #define PNV_CORE_IDLE_WINKLE_COUNT_BITS 0x000F0000 35 #define PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT 8 36 #define PNV_CORE_IDLE_THREAD_WINKLE_BITS 0x0000FF00 37 38 #define PNV_CORE_IDLE_THREAD_BITS 0x000000FF 39 40 /* 41 * ============================ NOTE ================================= 42 * The older firmware populates only the RL field in the psscr_val and 43 * sets the psscr_mask to 0xf. On such a firmware, the kernel sets the 44 * remaining PSSCR fields to default values as follows: 45 * 46 * - ESL and EC bits are to 1. So wakeup from any stop state will be 47 * at vector 0x100. 48 * 49 * - MTL and PSLL are set to the maximum allowed value as per the ISA, 50 * i.e. 15. 51 * 52 * - The Transition Rate, TR is set to the Maximum value 3. 53 */ 54 #define PSSCR_HV_DEFAULT_VAL (PSSCR_ESL | PSSCR_EC | \ 55 PSSCR_PSLL_MASK | PSSCR_TR_MASK | \ 56 PSSCR_MTL_MASK) 57 58 #define PSSCR_HV_DEFAULT_MASK (PSSCR_ESL | PSSCR_EC | \ 59 PSSCR_PSLL_MASK | PSSCR_TR_MASK | \ 60 PSSCR_MTL_MASK | PSSCR_RL_MASK) 61 #define PSSCR_EC_SHIFT 20 62 #define PSSCR_ESL_SHIFT 21 63 #define GET_PSSCR_EC(x) (((x) & PSSCR_EC) >> PSSCR_EC_SHIFT) 64 #define GET_PSSCR_ESL(x) (((x) & PSSCR_ESL) >> PSSCR_ESL_SHIFT) 65 #define GET_PSSCR_RL(x) ((x) & PSSCR_RL_MASK) 66 67 #define ERR_EC_ESL_MISMATCH -1 68 #define ERR_DEEP_STATE_ESL_MISMATCH -2 69 70 #ifndef __ASSEMBLY__ 71 /* Additional SPRs that need to be saved/restored during stop */ 72 struct stop_sprs { 73 u64 pid; 74 u64 ldbar; 75 u64 fscr; 76 u64 hfscr; 77 u64 mmcr1; 78 u64 mmcr2; 79 u64 mmcra; 80 }; 81 82 extern u32 pnv_fastsleep_workaround_at_entry[]; 83 extern u32 pnv_fastsleep_workaround_at_exit[]; 84 85 extern u64 pnv_first_deep_stop_state; 86 87 unsigned long pnv_cpu_offline(unsigned int cpu); 88 int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags); 89 static inline void report_invalid_psscr_val(u64 psscr_val, int err) 90 { 91 switch (err) { 92 case ERR_EC_ESL_MISMATCH: 93 pr_warn("Invalid psscr 0x%016llx : ESL,EC bits unequal", 94 psscr_val); 95 break; 96 case ERR_DEEP_STATE_ESL_MISMATCH: 97 pr_warn("Invalid psscr 0x%016llx : ESL cleared for deep stop-state", 98 psscr_val); 99 } 100 } 101 #endif 102 103 #endif 104 105 #endif 106