1 #ifndef _ASM_POWERPC_CPUIDLE_H 2 #define _ASM_POWERPC_CPUIDLE_H 3 4 #ifdef CONFIG_PPC_POWERNV 5 /* Thread state used in powernv idle state management */ 6 #define PNV_THREAD_RUNNING 0 7 #define PNV_THREAD_NAP 1 8 #define PNV_THREAD_SLEEP 2 9 #define PNV_THREAD_WINKLE 3 10 11 /* 12 * Core state used in powernv idle for POWER8. 13 * 14 * The lock bit synchronizes updates to the state, as well as parts of the 15 * sleep/wake code (see kernel/idle_book3s.S). 16 * 17 * Bottom 8 bits track the idle state of each thread. Bit is cleared before 18 * the thread executes an idle instruction (nap/sleep/winkle). 19 * 20 * Then there is winkle tracking. A core does not lose complete state 21 * until every thread is in winkle. So the winkle count field counts the 22 * number of threads in winkle (small window of false positives is okay 23 * around the sleep/wake, so long as there are no false negatives). 24 * 25 * When the winkle count reaches 8 (the COUNT_ALL_BIT becomes set), then 26 * the THREAD_WINKLE_BITS are set, which indicate which threads have not 27 * yet woken from the winkle state. 28 */ 29 #define PNV_CORE_IDLE_LOCK_BIT 0x10000000 30 31 #define PNV_CORE_IDLE_WINKLE_COUNT 0x00010000 32 #define PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT 0x00080000 33 #define PNV_CORE_IDLE_WINKLE_COUNT_BITS 0x000F0000 34 #define PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT 8 35 #define PNV_CORE_IDLE_THREAD_WINKLE_BITS 0x0000FF00 36 37 #define PNV_CORE_IDLE_THREAD_BITS 0x000000FF 38 39 /* 40 * ============================ NOTE ================================= 41 * The older firmware populates only the RL field in the psscr_val and 42 * sets the psscr_mask to 0xf. On such a firmware, the kernel sets the 43 * remaining PSSCR fields to default values as follows: 44 * 45 * - ESL and EC bits are to 1. So wakeup from any stop state will be 46 * at vector 0x100. 47 * 48 * - MTL and PSLL are set to the maximum allowed value as per the ISA, 49 * i.e. 15. 50 * 51 * - The Transition Rate, TR is set to the Maximum value 3. 52 */ 53 #define PSSCR_HV_DEFAULT_VAL (PSSCR_ESL | PSSCR_EC | \ 54 PSSCR_PSLL_MASK | PSSCR_TR_MASK | \ 55 PSSCR_MTL_MASK) 56 57 #define PSSCR_HV_DEFAULT_MASK (PSSCR_ESL | PSSCR_EC | \ 58 PSSCR_PSLL_MASK | PSSCR_TR_MASK | \ 59 PSSCR_MTL_MASK | PSSCR_RL_MASK) 60 #define PSSCR_EC_SHIFT 20 61 #define PSSCR_ESL_SHIFT 21 62 #define GET_PSSCR_EC(x) (((x) & PSSCR_EC) >> PSSCR_EC_SHIFT) 63 #define GET_PSSCR_ESL(x) (((x) & PSSCR_ESL) >> PSSCR_ESL_SHIFT) 64 #define GET_PSSCR_RL(x) ((x) & PSSCR_RL_MASK) 65 66 #define ERR_EC_ESL_MISMATCH -1 67 #define ERR_DEEP_STATE_ESL_MISMATCH -2 68 69 #ifndef __ASSEMBLY__ 70 /* Additional SPRs that need to be saved/restored during stop */ 71 struct stop_sprs { 72 u64 pid; 73 u64 ldbar; 74 u64 fscr; 75 u64 hfscr; 76 u64 mmcr1; 77 u64 mmcr2; 78 u64 mmcra; 79 }; 80 81 extern u32 pnv_fastsleep_workaround_at_entry[]; 82 extern u32 pnv_fastsleep_workaround_at_exit[]; 83 84 extern u64 pnv_first_deep_stop_state; 85 86 unsigned long pnv_cpu_offline(unsigned int cpu); 87 int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags); 88 static inline void report_invalid_psscr_val(u64 psscr_val, int err) 89 { 90 switch (err) { 91 case ERR_EC_ESL_MISMATCH: 92 pr_warn("Invalid psscr 0x%016llx : ESL,EC bits unequal", 93 psscr_val); 94 break; 95 case ERR_DEEP_STATE_ESL_MISMATCH: 96 pr_warn("Invalid psscr 0x%016llx : ESL cleared for deep stop-state", 97 psscr_val); 98 } 99 } 100 #endif 101 102 #endif 103 104 #endif 105