1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 */ 4 #ifndef _ASM_POWERPC_CACHEFLUSH_H 5 #define _ASM_POWERPC_CACHEFLUSH_H 6 7 #include <linux/mm.h> 8 #include <asm/cputable.h> 9 #include <asm/cpu_has_feature.h> 10 11 /* 12 * This flag is used to indicate that the page pointed to by a pte is clean 13 * and does not require cleaning before returning it to the user. 14 */ 15 #define PG_dcache_clean PG_arch_1 16 17 #ifdef CONFIG_PPC_BOOK3S_64 18 /* 19 * Book3s has no ptesync after setting a pte, so without this ptesync it's 20 * possible for a kernel virtual mapping access to return a spurious fault 21 * if it's accessed right after the pte is set. The page fault handler does 22 * not expect this type of fault. flush_cache_vmap is not exactly the right 23 * place to put this, but it seems to work well enough. 24 */ 25 static inline void flush_cache_vmap(unsigned long start, unsigned long end) 26 { 27 asm volatile("ptesync" ::: "memory"); 28 } 29 #define flush_cache_vmap flush_cache_vmap 30 #endif /* CONFIG_PPC_BOOK3S_64 */ 31 32 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 33 extern void flush_dcache_page(struct page *page); 34 35 void flush_icache_range(unsigned long start, unsigned long stop); 36 #define flush_icache_range flush_icache_range 37 38 void flush_icache_user_page(struct vm_area_struct *vma, struct page *page, 39 unsigned long addr, int len); 40 #define flush_icache_user_page flush_icache_user_page 41 42 void flush_dcache_icache_page(struct page *page); 43 void __flush_dcache_icache(void *page); 44 45 /** 46 * flush_dcache_range(): Write any modified data cache blocks out to memory and 47 * invalidate them. Does not invalidate the corresponding instruction cache 48 * blocks. 49 * 50 * @start: the start address 51 * @stop: the stop address (exclusive) 52 */ 53 static inline void flush_dcache_range(unsigned long start, unsigned long stop) 54 { 55 unsigned long shift = l1_dcache_shift(); 56 unsigned long bytes = l1_dcache_bytes(); 57 void *addr = (void *)(start & ~(bytes - 1)); 58 unsigned long size = stop - (unsigned long)addr + (bytes - 1); 59 unsigned long i; 60 61 if (IS_ENABLED(CONFIG_PPC64)) 62 mb(); /* sync */ 63 64 for (i = 0; i < size >> shift; i++, addr += bytes) 65 dcbf(addr); 66 mb(); /* sync */ 67 68 } 69 70 /* 71 * Write any modified data cache blocks out to memory. 72 * Does not invalidate the corresponding cache lines (especially for 73 * any corresponding instruction cache). 74 */ 75 static inline void clean_dcache_range(unsigned long start, unsigned long stop) 76 { 77 unsigned long shift = l1_dcache_shift(); 78 unsigned long bytes = l1_dcache_bytes(); 79 void *addr = (void *)(start & ~(bytes - 1)); 80 unsigned long size = stop - (unsigned long)addr + (bytes - 1); 81 unsigned long i; 82 83 for (i = 0; i < size >> shift; i++, addr += bytes) 84 dcbst(addr); 85 mb(); /* sync */ 86 } 87 88 /* 89 * Like above, but invalidate the D-cache. This is used by the 8xx 90 * to invalidate the cache so the PPC core doesn't get stale data 91 * from the CPM (no cache snooping here :-). 92 */ 93 static inline void invalidate_dcache_range(unsigned long start, 94 unsigned long stop) 95 { 96 unsigned long shift = l1_dcache_shift(); 97 unsigned long bytes = l1_dcache_bytes(); 98 void *addr = (void *)(start & ~(bytes - 1)); 99 unsigned long size = stop - (unsigned long)addr + (bytes - 1); 100 unsigned long i; 101 102 for (i = 0; i < size >> shift; i++, addr += bytes) 103 dcbi(addr); 104 mb(); /* sync */ 105 } 106 107 #ifdef CONFIG_4xx 108 static inline void flush_instruction_cache(void) 109 { 110 iccci((void *)KERNELBASE); 111 isync(); 112 } 113 #else 114 void flush_instruction_cache(void); 115 #endif 116 117 #include <asm-generic/cacheflush.h> 118 119 #endif /* _ASM_POWERPC_CACHEFLUSH_H */ 120