12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2b8b572e1SStephen Rothwell /*
3b8b572e1SStephen Rothwell */
4b8b572e1SStephen Rothwell #ifndef _ASM_POWERPC_CACHEFLUSH_H
5b8b572e1SStephen Rothwell #define _ASM_POWERPC_CACHEFLUSH_H
6b8b572e1SStephen Rothwell
7b8b572e1SStephen Rothwell #include <linux/mm.h>
8b8b572e1SStephen Rothwell #include <asm/cputable.h>
9d3580427SAneesh Kumar K.V #include <asm/cpu_has_feature.h>
10b8b572e1SStephen Rothwell
11ec94b9b2SAneesh Kumar K.V /*
12ec94b9b2SAneesh Kumar K.V * This flag is used to indicate that the page pointed to by a pte is clean
13ec94b9b2SAneesh Kumar K.V * and does not require cleaning before returning it to the user.
14ec94b9b2SAneesh Kumar K.V */
15ec94b9b2SAneesh Kumar K.V #define PG_dcache_clean PG_arch_1
16ec94b9b2SAneesh Kumar K.V
17ff5bc793SNicholas Piggin #ifdef CONFIG_PPC_BOOK3S_64
18f1cb8f9bSNicholas Piggin /*
19f1cb8f9bSNicholas Piggin * Book3s has no ptesync after setting a pte, so without this ptesync it's
20f1cb8f9bSNicholas Piggin * possible for a kernel virtual mapping access to return a spurious fault
21f1cb8f9bSNicholas Piggin * if it's accessed right after the pte is set. The page fault handler does
22f1cb8f9bSNicholas Piggin * not expect this type of fault. flush_cache_vmap is not exactly the right
23f1cb8f9bSNicholas Piggin * place to put this, but it seems to work well enough.
24f1cb8f9bSNicholas Piggin */
flush_cache_vmap(unsigned long start,unsigned long end)2504db3edeSQian Cai static inline void flush_cache_vmap(unsigned long start, unsigned long end)
2604db3edeSQian Cai {
2704db3edeSQian Cai asm volatile("ptesync" ::: "memory");
2804db3edeSQian Cai }
295019f760SChristoph Hellwig #define flush_cache_vmap flush_cache_vmap
305019f760SChristoph Hellwig #endif /* CONFIG_PPC_BOOK3S_64 */
31f1cb8f9bSNicholas Piggin
322d4dc890SIlya Loginov #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
336c960208SChristophe Leroy /*
346c960208SChristophe Leroy * This is called when a page has been modified by the kernel.
356c960208SChristophe Leroy * It just marks the page as not i-cache clean. We do the i-cache
366c960208SChristophe Leroy * flush later when the page is given to a user process, if necessary.
376c960208SChristophe Leroy */
flush_dcache_folio(struct folio * folio)38*9fee28baSMatthew Wilcox (Oracle) static inline void flush_dcache_folio(struct folio *folio)
396c960208SChristophe Leroy {
406c960208SChristophe Leroy if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
416c960208SChristophe Leroy return;
426c960208SChristophe Leroy /* avoid an atomic op if possible */
43*9fee28baSMatthew Wilcox (Oracle) if (test_bit(PG_dcache_clean, &folio->flags))
44*9fee28baSMatthew Wilcox (Oracle) clear_bit(PG_dcache_clean, &folio->flags);
45*9fee28baSMatthew Wilcox (Oracle) }
46*9fee28baSMatthew Wilcox (Oracle) #define flush_dcache_folio flush_dcache_folio
47*9fee28baSMatthew Wilcox (Oracle)
flush_dcache_page(struct page * page)48*9fee28baSMatthew Wilcox (Oracle) static inline void flush_dcache_page(struct page *page)
49*9fee28baSMatthew Wilcox (Oracle) {
50*9fee28baSMatthew Wilcox (Oracle) flush_dcache_folio(page_folio(page));
516c960208SChristophe Leroy }
52b8b572e1SStephen Rothwell
5323eb7f56SAlastair D'Silva void flush_icache_range(unsigned long start, unsigned long stop);
545019f760SChristoph Hellwig #define flush_icache_range flush_icache_range
555019f760SChristoph Hellwig
56885f7f8eSChristoph Hellwig void flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
575019f760SChristoph Hellwig unsigned long addr, int len);
58885f7f8eSChristoph Hellwig #define flush_icache_user_page flush_icache_user_page
595019f760SChristoph Hellwig
60*9fee28baSMatthew Wilcox (Oracle) void flush_dcache_icache_folio(struct folio *folio);
61b8b572e1SStephen Rothwell
6223eb7f56SAlastair D'Silva /**
6323eb7f56SAlastair D'Silva * flush_dcache_range(): Write any modified data cache blocks out to memory and
6423eb7f56SAlastair D'Silva * invalidate them. Does not invalidate the corresponding instruction cache
6523eb7f56SAlastair D'Silva * blocks.
6623eb7f56SAlastair D'Silva *
6723eb7f56SAlastair D'Silva * @start: the start address
6823eb7f56SAlastair D'Silva * @stop: the stop address (exclusive)
69affe587bSChristophe Leroy */
flush_dcache_range(unsigned long start,unsigned long stop)70affe587bSChristophe Leroy static inline void flush_dcache_range(unsigned long start, unsigned long stop)
71affe587bSChristophe Leroy {
727a0745c5SAlastair D'Silva unsigned long shift = l1_dcache_shift();
737a0745c5SAlastair D'Silva unsigned long bytes = l1_dcache_bytes();
74d98fc70fSChristophe Leroy void *addr = (void *)(start & ~(bytes - 1));
75d98fc70fSChristophe Leroy unsigned long size = stop - (unsigned long)addr + (bytes - 1);
76affe587bSChristophe Leroy unsigned long i;
77affe587bSChristophe Leroy
78233ba546SAneesh Kumar K.V if (IS_ENABLED(CONFIG_PPC64))
7922e9c88dSChristophe Leroy mb(); /* sync */
8022e9c88dSChristophe Leroy
81d98fc70fSChristophe Leroy for (i = 0; i < size >> shift; i++, addr += bytes)
82affe587bSChristophe Leroy dcbf(addr);
83affe587bSChristophe Leroy mb(); /* sync */
8422e9c88dSChristophe Leroy
85affe587bSChristophe Leroy }
86affe587bSChristophe Leroy
87affe587bSChristophe Leroy /*
88affe587bSChristophe Leroy * Write any modified data cache blocks out to memory.
89affe587bSChristophe Leroy * Does not invalidate the corresponding cache lines (especially for
90affe587bSChristophe Leroy * any corresponding instruction cache).
91affe587bSChristophe Leroy */
clean_dcache_range(unsigned long start,unsigned long stop)92affe587bSChristophe Leroy static inline void clean_dcache_range(unsigned long start, unsigned long stop)
93affe587bSChristophe Leroy {
947a0745c5SAlastair D'Silva unsigned long shift = l1_dcache_shift();
957a0745c5SAlastair D'Silva unsigned long bytes = l1_dcache_bytes();
96d98fc70fSChristophe Leroy void *addr = (void *)(start & ~(bytes - 1));
97d98fc70fSChristophe Leroy unsigned long size = stop - (unsigned long)addr + (bytes - 1);
98affe587bSChristophe Leroy unsigned long i;
99affe587bSChristophe Leroy
100d98fc70fSChristophe Leroy for (i = 0; i < size >> shift; i++, addr += bytes)
101affe587bSChristophe Leroy dcbst(addr);
102affe587bSChristophe Leroy mb(); /* sync */
103affe587bSChristophe Leroy }
104affe587bSChristophe Leroy
105affe587bSChristophe Leroy /*
106affe587bSChristophe Leroy * Like above, but invalidate the D-cache. This is used by the 8xx
107affe587bSChristophe Leroy * to invalidate the cache so the PPC core doesn't get stale data
108affe587bSChristophe Leroy * from the CPM (no cache snooping here :-).
109affe587bSChristophe Leroy */
invalidate_dcache_range(unsigned long start,unsigned long stop)110affe587bSChristophe Leroy static inline void invalidate_dcache_range(unsigned long start,
111affe587bSChristophe Leroy unsigned long stop)
112affe587bSChristophe Leroy {
1137a0745c5SAlastair D'Silva unsigned long shift = l1_dcache_shift();
1147a0745c5SAlastair D'Silva unsigned long bytes = l1_dcache_bytes();
115d98fc70fSChristophe Leroy void *addr = (void *)(start & ~(bytes - 1));
116d98fc70fSChristophe Leroy unsigned long size = stop - (unsigned long)addr + (bytes - 1);
117affe587bSChristophe Leroy unsigned long i;
118affe587bSChristophe Leroy
119d98fc70fSChristophe Leroy for (i = 0; i < size >> shift; i++, addr += bytes)
120affe587bSChristophe Leroy dcbi(addr);
121affe587bSChristophe Leroy mb(); /* sync */
122affe587bSChristophe Leroy }
123affe587bSChristophe Leroy
124de39b194SChristophe Leroy #ifdef CONFIG_4xx
flush_instruction_cache(void)125de39b194SChristophe Leroy static inline void flush_instruction_cache(void)
126de39b194SChristophe Leroy {
127de39b194SChristophe Leroy iccci((void *)KERNELBASE);
128de39b194SChristophe Leroy isync();
129de39b194SChristophe Leroy }
130de39b194SChristophe Leroy #else
131f663f331SChristophe Leroy void flush_instruction_cache(void);
132de39b194SChristophe Leroy #endif
133f663f331SChristophe Leroy
1345019f760SChristoph Hellwig #include <asm-generic/cacheflush.h>
135b8b572e1SStephen Rothwell
136b8b572e1SStephen Rothwell #endif /* _ASM_POWERPC_CACHEFLUSH_H */
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