1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_PGTABLE_RADIX_H 3 #define _ASM_POWERPC_PGTABLE_RADIX_H 4 5 #ifndef __ASSEMBLY__ 6 #include <asm/cmpxchg.h> 7 #endif 8 9 #ifdef CONFIG_PPC_64K_PAGES 10 #include <asm/book3s/64/radix-64k.h> 11 #else 12 #include <asm/book3s/64/radix-4k.h> 13 #endif 14 15 /* 16 * For P9 DD1 only, we need to track whether the pte's huge. 17 */ 18 #define R_PAGE_LARGE _RPAGE_RSV1 19 20 21 #ifndef __ASSEMBLY__ 22 #include <asm/book3s/64/tlbflush-radix.h> 23 #include <asm/cpu_has_feature.h> 24 #endif 25 26 /* An empty PTE can still have a R or C writeback */ 27 #define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED) 28 29 /* Bits to set in a RPMD/RPUD/RPGD */ 30 #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE) 31 #define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE) 32 #define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE) 33 34 /* Don't have anything in the reserved bits and leaf bits */ 35 #define RADIX_PMD_BAD_BITS 0x60000000000000e0UL 36 #define RADIX_PUD_BAD_BITS 0x60000000000000e0UL 37 #define RADIX_PGD_BAD_BITS 0x60000000000000e0UL 38 39 /* 40 * Size of EA range mapped by our pagetables. 41 */ 42 #define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \ 43 RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT) 44 #define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE) 45 46 /* 47 * We support 52 bit address space, Use top bit for kernel 48 * virtual mapping. Also make sure kernel fit in the top 49 * quadrant. 50 * 51 * +------------------+ 52 * +------------------+ Kernel virtual map (0xc008000000000000) 53 * | | 54 * | | 55 * | | 56 * 0b11......+------------------+ Kernel linear map (0xc....) 57 * | | 58 * | 2 quadrant | 59 * | | 60 * 0b10......+------------------+ 61 * | | 62 * | 1 quadrant | 63 * | | 64 * 0b01......+------------------+ 65 * | | 66 * | 0 quadrant | 67 * | | 68 * 0b00......+------------------+ 69 * 70 * 71 * 3rd quadrant expanded: 72 * +------------------------------+ 73 * | | 74 * | | 75 * | | 76 * +------------------------------+ Kernel IO map end (0xc010000000000000) 77 * | | 78 * | | 79 * | 1/2 of virtual map | 80 * | | 81 * | | 82 * +------------------------------+ Kernel IO map start 83 * | | 84 * | 1/4 of virtual map | 85 * | | 86 * +------------------------------+ Kernel vmemap start 87 * | | 88 * | 1/4 of virtual map | 89 * | | 90 * +------------------------------+ Kernel virt start (0xc008000000000000) 91 * | | 92 * | | 93 * | | 94 * +------------------------------+ Kernel linear (0xc.....) 95 */ 96 97 #define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000) 98 #define RADIX_KERN_VIRT_SIZE ASM_CONST(0x0008000000000000) 99 100 /* 101 * The vmalloc space starts at the beginning of that region, and 102 * occupies a quarter of it on radix config. 103 * (we keep a quarter for the virtual memmap) 104 */ 105 #define RADIX_VMALLOC_START RADIX_KERN_VIRT_START 106 #define RADIX_VMALLOC_SIZE (RADIX_KERN_VIRT_SIZE >> 2) 107 #define RADIX_VMALLOC_END (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE) 108 /* 109 * Defines the address of the vmemap area, in its own region on 110 * hash table CPUs. 111 */ 112 #define RADIX_VMEMMAP_BASE (RADIX_VMALLOC_END) 113 114 #define RADIX_KERN_IO_START (RADIX_KERN_VIRT_START + (RADIX_KERN_VIRT_SIZE >> 1)) 115 116 #ifndef __ASSEMBLY__ 117 #define RADIX_PTE_TABLE_SIZE (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE) 118 #define RADIX_PMD_TABLE_SIZE (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE) 119 #define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE) 120 #define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE) 121 122 #ifdef CONFIG_STRICT_KERNEL_RWX 123 extern void radix__mark_rodata_ro(void); 124 extern void radix__mark_initmem_nx(void); 125 #endif 126 127 extern void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep, 128 pte_t entry, unsigned long address, 129 int psize); 130 131 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr, 132 unsigned long set) 133 { 134 __be64 old_be, tmp_be; 135 136 __asm__ __volatile__( 137 "1: ldarx %0,0,%3 # pte_update\n" 138 " andc %1,%0,%5 \n" 139 " or %1,%1,%4 \n" 140 " stdcx. %1,0,%3 \n" 141 " bne- 1b" 142 : "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep) 143 : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr)) 144 : "cc" ); 145 146 return be64_to_cpu(old_be); 147 } 148 149 static inline unsigned long radix__pte_update(struct mm_struct *mm, 150 unsigned long addr, 151 pte_t *ptep, unsigned long clr, 152 unsigned long set, 153 int huge) 154 { 155 unsigned long old_pte; 156 157 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 158 159 unsigned long new_pte; 160 161 old_pte = __radix_pte_update(ptep, ~0ul, 0); 162 /* 163 * new value of pte 164 */ 165 new_pte = (old_pte | set) & ~clr; 166 radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr); 167 if (new_pte) 168 __radix_pte_update(ptep, 0, new_pte); 169 } else 170 old_pte = __radix_pte_update(ptep, clr, set); 171 if (!huge) 172 assert_pte_locked(mm, addr); 173 174 return old_pte; 175 } 176 177 static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm, 178 unsigned long addr, 179 pte_t *ptep, int full) 180 { 181 unsigned long old_pte; 182 183 if (full) { 184 old_pte = pte_val(*ptep); 185 *ptep = __pte(0); 186 } else 187 old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0); 188 189 return __pte(old_pte); 190 } 191 192 static inline int radix__pte_same(pte_t pte_a, pte_t pte_b) 193 { 194 return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0); 195 } 196 197 static inline int radix__pte_none(pte_t pte) 198 { 199 return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0; 200 } 201 202 static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr, 203 pte_t *ptep, pte_t pte, int percpu) 204 { 205 *ptep = pte; 206 207 /* 208 * The architecture suggests a ptesync after setting the pte, which 209 * orders the store that updates the pte with subsequent page table 210 * walk accesses which may load the pte. Without this it may be 211 * possible for a subsequent access to result in spurious fault. 212 * 213 * This is not necessary for correctness, because a spurious fault 214 * is tolerated by the page fault handler, and this store will 215 * eventually be seen. In testing, there was no noticable increase 216 * in user faults on POWER9. Avoiding ptesync here is a significant 217 * win for things like fork. If a future microarchitecture benefits 218 * from ptesync, it should probably go into update_mmu_cache, rather 219 * than set_pte_at (which is used to set ptes unrelated to faults). 220 * 221 * Spurious faults to vmalloc region are not tolerated, so there is 222 * a ptesync in flush_cache_vmap. 223 */ 224 } 225 226 static inline int radix__pmd_bad(pmd_t pmd) 227 { 228 return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS); 229 } 230 231 static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b) 232 { 233 return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0); 234 } 235 236 static inline int radix__pud_bad(pud_t pud) 237 { 238 return !!(pud_val(pud) & RADIX_PUD_BAD_BITS); 239 } 240 241 242 static inline int radix__pgd_bad(pgd_t pgd) 243 { 244 return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS); 245 } 246 247 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 248 249 static inline int radix__pmd_trans_huge(pmd_t pmd) 250 { 251 return (pmd_val(pmd) & (_PAGE_PTE | _PAGE_DEVMAP)) == _PAGE_PTE; 252 } 253 254 static inline pmd_t radix__pmd_mkhuge(pmd_t pmd) 255 { 256 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) 257 return __pmd(pmd_val(pmd) | _PAGE_PTE | R_PAGE_LARGE); 258 return __pmd(pmd_val(pmd) | _PAGE_PTE); 259 } 260 261 extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, 262 pmd_t *pmdp, unsigned long clr, 263 unsigned long set); 264 extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, 265 unsigned long address, pmd_t *pmdp); 266 extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 267 pgtable_t pgtable); 268 extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 269 extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm, 270 unsigned long addr, pmd_t *pmdp); 271 extern int radix__has_transparent_hugepage(void); 272 #endif 273 274 extern int __meminit radix__vmemmap_create_mapping(unsigned long start, 275 unsigned long page_size, 276 unsigned long phys); 277 extern void radix__vmemmap_remove_mapping(unsigned long start, 278 unsigned long page_size); 279 280 extern int radix__map_kernel_page(unsigned long ea, unsigned long pa, 281 pgprot_t flags, unsigned int psz); 282 283 static inline unsigned long radix__get_tree_size(void) 284 { 285 unsigned long rts_field; 286 /* 287 * We support 52 bits, hence: 288 * DD1 52-28 = 24, 0b11000 289 * Others 52-31 = 21, 0b10101 290 * RTS encoding details 291 * bits 0 - 3 of rts -> bits 6 - 8 unsigned long 292 * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long 293 */ 294 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) 295 rts_field = (0x3UL << 61); 296 else { 297 rts_field = (0x5UL << 5); /* 6 - 8 bits */ 298 rts_field |= (0x2UL << 61); 299 } 300 return rts_field; 301 } 302 303 #ifdef CONFIG_MEMORY_HOTPLUG 304 int radix__create_section_mapping(unsigned long start, unsigned long end, int nid); 305 int radix__remove_section_mapping(unsigned long start, unsigned long end); 306 #endif /* CONFIG_MEMORY_HOTPLUG */ 307 #endif /* __ASSEMBLY__ */ 308 #endif 309