1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/5level-fixup.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_NA 0 18 #define _PAGE_RO 0 19 #define _PAGE_USER 0 20 21 #define _PAGE_EXEC 0x00001 /* execute permission */ 22 #define _PAGE_WRITE 0x00002 /* write access allowed */ 23 #define _PAGE_READ 0x00004 /* read access allowed */ 24 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 25 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 26 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 27 #define _PAGE_SAO 0x00010 /* Strong access order */ 28 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 29 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 30 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 31 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 32 /* 33 * Software bits 34 */ 35 #define _RPAGE_SW0 0x2000000000000000UL 36 #define _RPAGE_SW1 0x00800 37 #define _RPAGE_SW2 0x00400 38 #define _RPAGE_SW3 0x00200 39 #define _RPAGE_RSV1 0x1000000000000000UL 40 #define _RPAGE_RSV2 0x0800000000000000UL 41 #define _RPAGE_RSV3 0x0400000000000000UL 42 #define _RPAGE_RSV4 0x0200000000000000UL 43 #define _RPAGE_RSV5 0x00040UL 44 45 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 46 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 47 48 /* 49 * Top and bottom bits of RPN which can be used by hash 50 * translation mode, because we expect them to be zero 51 * otherwise. 52 */ 53 #define _RPAGE_RPN0 0x01000 54 #define _RPAGE_RPN1 0x02000 55 #define _RPAGE_RPN44 0x0100000000000000UL 56 #define _RPAGE_RPN43 0x0080000000000000UL 57 #define _RPAGE_RPN42 0x0040000000000000UL 58 #define _RPAGE_RPN41 0x0020000000000000UL 59 60 /* Max physical address bit as per radix table */ 61 #define _RPAGE_PA_MAX 57 62 63 /* 64 * Max physical address bit we will use for now. 65 * 66 * This is mostly a hardware limitation and for now Power9 has 67 * a 51 bit limit. 68 * 69 * This is different from the number of physical bit required to address 70 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 71 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 72 * number of sections we can support (SECTIONS_SHIFT). 73 * 74 * This is different from Radix page table limitation above and 75 * should always be less than that. The limit is done such that 76 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 77 * for hash linux page table specific bits. 78 * 79 * In order to be compatible with future hardware generations we keep 80 * some offsets and limit this for now to 53 81 */ 82 #define _PAGE_PA_MAX 53 83 84 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 85 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 86 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 87 #define __HAVE_ARCH_PTE_DEVMAP 88 89 /* 90 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 91 * Instead of fixing all of them, add an alternate define which 92 * maps CI pte mapping. 93 */ 94 #define _PAGE_NO_CACHE _PAGE_TOLERANT 95 /* 96 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 97 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 98 * and every thing below PAGE_SHIFT; 99 */ 100 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 101 /* 102 * set of bits not changed in pmd_modify. Even though we have hash specific bits 103 * in here, on radix we expect them to be zero. 104 */ 105 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 106 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 107 _PAGE_SOFT_DIRTY) 108 /* 109 * user access blocked by key 110 */ 111 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 112 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 113 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 114 _PAGE_RW | _PAGE_EXEC) 115 /* 116 * No page size encoding in the linux PTE 117 */ 118 #define _PAGE_PSIZE 0 119 /* 120 * _PAGE_CHG_MASK masks of bits that are to be preserved across 121 * pgprot changes 122 */ 123 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 124 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 125 _PAGE_SOFT_DIRTY) 126 127 #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \ 128 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4) 129 /* 130 * Mask of bits returned by pte_pgprot() 131 */ 132 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ 133 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ 134 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ 135 _PAGE_SOFT_DIRTY | H_PTE_PKEY) 136 /* 137 * We define 2 sets of base prot bits, one for basic pages (ie, 138 * cacheable kernel and user pages) and one for non cacheable 139 * pages. We always set _PAGE_COHERENT when SMP is enabled or 140 * the processor might need it for DMA coherency. 141 */ 142 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 143 #define _PAGE_BASE (_PAGE_BASE_NC) 144 145 /* Permission masks used to generate the __P and __S table, 146 * 147 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 148 * 149 * Write permissions imply read permissions for now (we could make write-only 150 * pages on BookE but we don't bother for now). Execute permission control is 151 * possible on platforms that define _PAGE_EXEC 152 * 153 * Note due to the way vm flags are laid out, the bits are XWR 154 */ 155 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 156 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 157 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 158 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 159 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 160 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 161 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 162 163 #define __P000 PAGE_NONE 164 #define __P001 PAGE_READONLY 165 #define __P010 PAGE_COPY 166 #define __P011 PAGE_COPY 167 #define __P100 PAGE_READONLY_X 168 #define __P101 PAGE_READONLY_X 169 #define __P110 PAGE_COPY_X 170 #define __P111 PAGE_COPY_X 171 172 #define __S000 PAGE_NONE 173 #define __S001 PAGE_READONLY 174 #define __S010 PAGE_SHARED 175 #define __S011 PAGE_SHARED 176 #define __S100 PAGE_READONLY_X 177 #define __S101 PAGE_READONLY_X 178 #define __S110 PAGE_SHARED_X 179 #define __S111 PAGE_SHARED_X 180 181 /* Permission masks used for kernel mappings */ 182 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 183 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 184 _PAGE_TOLERANT) 185 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 186 _PAGE_NON_IDEMPOTENT) 187 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 188 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 189 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 190 191 /* 192 * Protection used for kernel text. We want the debuggers to be able to 193 * set breakpoints anywhere, so don't write protect the kernel text 194 * on platforms where such control is possible. 195 */ 196 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 197 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 198 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 199 #else 200 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 201 #endif 202 203 /* Make modules code happy. We don't set RO yet */ 204 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 205 #define PAGE_AGP (PAGE_KERNEL_NC) 206 207 #ifndef __ASSEMBLY__ 208 /* 209 * page table defines 210 */ 211 extern unsigned long __pte_index_size; 212 extern unsigned long __pmd_index_size; 213 extern unsigned long __pud_index_size; 214 extern unsigned long __pgd_index_size; 215 extern unsigned long __pud_cache_index; 216 #define PTE_INDEX_SIZE __pte_index_size 217 #define PMD_INDEX_SIZE __pmd_index_size 218 #define PUD_INDEX_SIZE __pud_index_size 219 #define PGD_INDEX_SIZE __pgd_index_size 220 /* pmd table use page table fragments */ 221 #define PMD_CACHE_INDEX 0 222 #define PUD_CACHE_INDEX __pud_cache_index 223 /* 224 * Because of use of pte fragments and THP, size of page table 225 * are not always derived out of index size above. 226 */ 227 extern unsigned long __pte_table_size; 228 extern unsigned long __pmd_table_size; 229 extern unsigned long __pud_table_size; 230 extern unsigned long __pgd_table_size; 231 #define PTE_TABLE_SIZE __pte_table_size 232 #define PMD_TABLE_SIZE __pmd_table_size 233 #define PUD_TABLE_SIZE __pud_table_size 234 #define PGD_TABLE_SIZE __pgd_table_size 235 236 extern unsigned long __pmd_val_bits; 237 extern unsigned long __pud_val_bits; 238 extern unsigned long __pgd_val_bits; 239 #define PMD_VAL_BITS __pmd_val_bits 240 #define PUD_VAL_BITS __pud_val_bits 241 #define PGD_VAL_BITS __pgd_val_bits 242 243 extern unsigned long __pte_frag_nr; 244 #define PTE_FRAG_NR __pte_frag_nr 245 extern unsigned long __pte_frag_size_shift; 246 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 247 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 248 249 extern unsigned long __pmd_frag_nr; 250 #define PMD_FRAG_NR __pmd_frag_nr 251 extern unsigned long __pmd_frag_size_shift; 252 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 253 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 254 255 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 256 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 257 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 258 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 259 260 /* PMD_SHIFT determines what a second-level page table entry can map */ 261 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 262 #define PMD_SIZE (1UL << PMD_SHIFT) 263 #define PMD_MASK (~(PMD_SIZE-1)) 264 265 /* PUD_SHIFT determines what a third-level page table entry can map */ 266 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 267 #define PUD_SIZE (1UL << PUD_SHIFT) 268 #define PUD_MASK (~(PUD_SIZE-1)) 269 270 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 271 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 272 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 273 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 274 275 /* Bits to mask out from a PMD to get to the PTE page */ 276 #define PMD_MASKED_BITS 0xc0000000000000ffUL 277 /* Bits to mask out from a PUD to get to the PMD page */ 278 #define PUD_MASKED_BITS 0xc0000000000000ffUL 279 /* Bits to mask out from a PGD to get to the PUD page */ 280 #define PGD_MASKED_BITS 0xc0000000000000ffUL 281 282 /* 283 * Used as an indicator for rcu callback functions 284 */ 285 enum pgtable_index { 286 PTE_INDEX = 0, 287 PMD_INDEX, 288 PUD_INDEX, 289 PGD_INDEX, 290 }; 291 292 extern unsigned long __vmalloc_start; 293 extern unsigned long __vmalloc_end; 294 #define VMALLOC_START __vmalloc_start 295 #define VMALLOC_END __vmalloc_end 296 297 extern unsigned long __kernel_virt_start; 298 extern unsigned long __kernel_virt_size; 299 extern unsigned long __kernel_io_start; 300 #define KERN_VIRT_START __kernel_virt_start 301 #define KERN_VIRT_SIZE __kernel_virt_size 302 #define KERN_IO_START __kernel_io_start 303 extern struct page *vmemmap; 304 extern unsigned long ioremap_bot; 305 extern unsigned long pci_io_base; 306 #endif /* __ASSEMBLY__ */ 307 308 #include <asm/book3s/64/hash.h> 309 #include <asm/book3s/64/radix.h> 310 311 #ifdef CONFIG_PPC_64K_PAGES 312 #include <asm/book3s/64/pgtable-64k.h> 313 #else 314 #include <asm/book3s/64/pgtable-4k.h> 315 #endif 316 317 #include <asm/barrier.h> 318 /* 319 * The second half of the kernel virtual space is used for IO mappings, 320 * it's itself carved into the PIO region (ISA and PHB IO space) and 321 * the ioremap space 322 * 323 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 324 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 325 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 326 */ 327 #define FULL_IO_SIZE 0x80000000ul 328 #define ISA_IO_BASE (KERN_IO_START) 329 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 330 #define PHB_IO_BASE (ISA_IO_END) 331 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 332 #define IOREMAP_BASE (PHB_IO_END) 333 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 334 335 /* Advertise special mapping type for AGP */ 336 #define HAVE_PAGE_AGP 337 338 #ifndef __ASSEMBLY__ 339 340 /* 341 * This is the default implementation of various PTE accessors, it's 342 * used in all cases except Book3S with 64K pages where we have a 343 * concept of sub-pages 344 */ 345 #ifndef __real_pte 346 347 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 348 #define __rpte_to_pte(r) ((r).pte) 349 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 350 351 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 352 do { \ 353 index = 0; \ 354 shift = mmu_psize_defs[psize].shift; \ 355 356 #define pte_iterate_hashed_end() } while(0) 357 358 /* 359 * We expect this to be called only for user addresses or kernel virtual 360 * addresses other than the linear mapping. 361 */ 362 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 363 364 #endif /* __real_pte */ 365 366 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 367 pte_t *ptep, unsigned long clr, 368 unsigned long set, int huge) 369 { 370 if (radix_enabled()) 371 return radix__pte_update(mm, addr, ptep, clr, set, huge); 372 return hash__pte_update(mm, addr, ptep, clr, set, huge); 373 } 374 /* 375 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 376 * We currently remove entries from the hashtable regardless of whether 377 * the entry was young or dirty. 378 * 379 * We should be more intelligent about this but for the moment we override 380 * these functions and force a tlb flush unconditionally 381 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 382 * function for both hash and radix. 383 */ 384 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 385 unsigned long addr, pte_t *ptep) 386 { 387 unsigned long old; 388 389 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 390 return 0; 391 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 392 return (old & _PAGE_ACCESSED) != 0; 393 } 394 395 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 396 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 397 ({ \ 398 int __r; \ 399 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 400 __r; \ 401 }) 402 403 static inline int __pte_write(pte_t pte) 404 { 405 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 406 } 407 408 #ifdef CONFIG_NUMA_BALANCING 409 #define pte_savedwrite pte_savedwrite 410 static inline bool pte_savedwrite(pte_t pte) 411 { 412 /* 413 * Saved write ptes are prot none ptes that doesn't have 414 * privileged bit sit. We mark prot none as one which has 415 * present and pviliged bit set and RWX cleared. To mark 416 * protnone which used to have _PAGE_WRITE set we clear 417 * the privileged bit. 418 */ 419 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 420 } 421 #else 422 #define pte_savedwrite pte_savedwrite 423 static inline bool pte_savedwrite(pte_t pte) 424 { 425 return false; 426 } 427 #endif 428 429 static inline int pte_write(pte_t pte) 430 { 431 return __pte_write(pte) || pte_savedwrite(pte); 432 } 433 434 static inline int pte_read(pte_t pte) 435 { 436 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 437 } 438 439 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 440 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 441 pte_t *ptep) 442 { 443 if (__pte_write(*ptep)) 444 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 445 else if (unlikely(pte_savedwrite(*ptep))) 446 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 447 } 448 449 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 450 unsigned long addr, pte_t *ptep) 451 { 452 /* 453 * We should not find protnone for hugetlb, but this complete the 454 * interface. 455 */ 456 if (__pte_write(*ptep)) 457 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 458 else if (unlikely(pte_savedwrite(*ptep))) 459 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 460 } 461 462 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 463 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 464 unsigned long addr, pte_t *ptep) 465 { 466 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 467 return __pte(old); 468 } 469 470 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 471 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 472 unsigned long addr, 473 pte_t *ptep, int full) 474 { 475 if (full && radix_enabled()) { 476 /* 477 * Let's skip the DD1 style pte update here. We know that 478 * this is a full mm pte clear and hence can be sure there is 479 * no parallel set_pte. 480 */ 481 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 482 } 483 return ptep_get_and_clear(mm, addr, ptep); 484 } 485 486 487 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 488 pte_t * ptep) 489 { 490 pte_update(mm, addr, ptep, ~0UL, 0, 0); 491 } 492 493 static inline int pte_dirty(pte_t pte) 494 { 495 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 496 } 497 498 static inline int pte_young(pte_t pte) 499 { 500 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 501 } 502 503 static inline int pte_special(pte_t pte) 504 { 505 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 506 } 507 508 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 509 510 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 511 static inline bool pte_soft_dirty(pte_t pte) 512 { 513 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 514 } 515 516 static inline pte_t pte_mksoft_dirty(pte_t pte) 517 { 518 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); 519 } 520 521 static inline pte_t pte_clear_soft_dirty(pte_t pte) 522 { 523 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); 524 } 525 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 526 527 #ifdef CONFIG_NUMA_BALANCING 528 static inline int pte_protnone(pte_t pte) 529 { 530 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 531 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 532 } 533 534 #define pte_mk_savedwrite pte_mk_savedwrite 535 static inline pte_t pte_mk_savedwrite(pte_t pte) 536 { 537 /* 538 * Used by Autonuma subsystem to preserve the write bit 539 * while marking the pte PROT_NONE. Only allow this 540 * on PROT_NONE pte 541 */ 542 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 543 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 544 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED); 545 } 546 547 #define pte_clear_savedwrite pte_clear_savedwrite 548 static inline pte_t pte_clear_savedwrite(pte_t pte) 549 { 550 /* 551 * Used by KSM subsystem to make a protnone pte readonly. 552 */ 553 VM_BUG_ON(!pte_protnone(pte)); 554 return __pte(pte_val(pte) | _PAGE_PRIVILEGED); 555 } 556 #else 557 #define pte_clear_savedwrite pte_clear_savedwrite 558 static inline pte_t pte_clear_savedwrite(pte_t pte) 559 { 560 VM_WARN_ON(1); 561 return __pte(pte_val(pte) & ~_PAGE_WRITE); 562 } 563 #endif /* CONFIG_NUMA_BALANCING */ 564 565 static inline int pte_present(pte_t pte) 566 { 567 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 568 } 569 570 #ifdef CONFIG_PPC_MEM_KEYS 571 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 572 #else 573 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 574 { 575 return true; 576 } 577 #endif /* CONFIG_PPC_MEM_KEYS */ 578 579 #define pte_access_permitted pte_access_permitted 580 static inline bool pte_access_permitted(pte_t pte, bool write) 581 { 582 unsigned long pteval = pte_val(pte); 583 /* Also check for pte_user */ 584 unsigned long clear_pte_bits = _PAGE_PRIVILEGED; 585 /* 586 * _PAGE_READ is needed for any access and will be 587 * cleared for PROT_NONE 588 */ 589 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ; 590 591 if (write) 592 need_pte_bits |= _PAGE_WRITE; 593 594 if ((pteval & need_pte_bits) != need_pte_bits) 595 return false; 596 597 if ((pteval & clear_pte_bits) == clear_pte_bits) 598 return false; 599 600 return arch_pte_access_permitted(pte_val(pte), write, 0); 601 } 602 603 /* 604 * Conversion functions: convert a page and protection to a page entry, 605 * and a page entry and page directory to the page they refer to. 606 * 607 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 608 * long for now. 609 */ 610 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 611 { 612 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 613 pgprot_val(pgprot)); 614 } 615 616 static inline unsigned long pte_pfn(pte_t pte) 617 { 618 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 619 } 620 621 /* Generic modifiers for PTE bits */ 622 static inline pte_t pte_wrprotect(pte_t pte) 623 { 624 if (unlikely(pte_savedwrite(pte))) 625 return pte_clear_savedwrite(pte); 626 return __pte(pte_val(pte) & ~_PAGE_WRITE); 627 } 628 629 static inline pte_t pte_mkclean(pte_t pte) 630 { 631 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 632 } 633 634 static inline pte_t pte_mkold(pte_t pte) 635 { 636 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 637 } 638 639 static inline pte_t pte_mkwrite(pte_t pte) 640 { 641 /* 642 * write implies read, hence set both 643 */ 644 return __pte(pte_val(pte) | _PAGE_RW); 645 } 646 647 static inline pte_t pte_mkdirty(pte_t pte) 648 { 649 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 650 } 651 652 static inline pte_t pte_mkyoung(pte_t pte) 653 { 654 return __pte(pte_val(pte) | _PAGE_ACCESSED); 655 } 656 657 static inline pte_t pte_mkspecial(pte_t pte) 658 { 659 return __pte(pte_val(pte) | _PAGE_SPECIAL); 660 } 661 662 static inline pte_t pte_mkhuge(pte_t pte) 663 { 664 return pte; 665 } 666 667 static inline pte_t pte_mkdevmap(pte_t pte) 668 { 669 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP); 670 } 671 672 /* 673 * This is potentially called with a pmd as the argument, in which case it's not 674 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 675 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 676 * use in page directory entries (ie. non-ptes). 677 */ 678 static inline int pte_devmap(pte_t pte) 679 { 680 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 681 682 return (pte_raw(pte) & mask) == mask; 683 } 684 685 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 686 { 687 /* FIXME!! check whether this need to be a conditional */ 688 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 689 } 690 691 static inline bool pte_user(pte_t pte) 692 { 693 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 694 } 695 696 /* Encode and de-code a swap entry */ 697 #define MAX_SWAPFILES_CHECK() do { \ 698 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 699 /* \ 700 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 701 * We filter HPTEFLAGS on set_pte. \ 702 */ \ 703 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 704 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 705 } while (0) 706 /* 707 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 708 */ 709 #define SWP_TYPE_BITS 5 710 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 711 & ((1UL << SWP_TYPE_BITS) - 1)) 712 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 713 #define __swp_entry(type, offset) ((swp_entry_t) { \ 714 ((type) << _PAGE_BIT_SWAP_TYPE) \ 715 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 716 /* 717 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 718 * swap type and offset we get from swap and convert that to pte to find a 719 * matching pte in linux page table. 720 * Clear bits not found in swap entries here. 721 */ 722 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 723 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 724 725 #ifdef CONFIG_MEM_SOFT_DIRTY 726 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 727 #else 728 #define _PAGE_SWP_SOFT_DIRTY 0UL 729 #endif /* CONFIG_MEM_SOFT_DIRTY */ 730 731 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 732 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 733 { 734 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); 735 } 736 737 static inline bool pte_swp_soft_dirty(pte_t pte) 738 { 739 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 740 } 741 742 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 743 { 744 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); 745 } 746 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 747 748 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 749 { 750 /* 751 * This check for _PAGE_RWX and _PAGE_PRESENT bits 752 */ 753 if (access & ~ptev) 754 return false; 755 /* 756 * This check for access to privilege space 757 */ 758 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 759 return false; 760 761 return true; 762 } 763 /* 764 * Generic functions with hash/radix callbacks 765 */ 766 767 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 768 pte_t *ptep, pte_t entry, 769 unsigned long address, 770 int psize) 771 { 772 if (radix_enabled()) 773 return radix__ptep_set_access_flags(vma, ptep, entry, 774 address, psize); 775 return hash__ptep_set_access_flags(ptep, entry); 776 } 777 778 #define __HAVE_ARCH_PTE_SAME 779 static inline int pte_same(pte_t pte_a, pte_t pte_b) 780 { 781 if (radix_enabled()) 782 return radix__pte_same(pte_a, pte_b); 783 return hash__pte_same(pte_a, pte_b); 784 } 785 786 static inline int pte_none(pte_t pte) 787 { 788 if (radix_enabled()) 789 return radix__pte_none(pte); 790 return hash__pte_none(pte); 791 } 792 793 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 794 pte_t *ptep, pte_t pte, int percpu) 795 { 796 if (radix_enabled()) 797 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 798 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 799 } 800 801 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 802 803 #define pgprot_noncached pgprot_noncached 804 static inline pgprot_t pgprot_noncached(pgprot_t prot) 805 { 806 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 807 _PAGE_NON_IDEMPOTENT); 808 } 809 810 #define pgprot_noncached_wc pgprot_noncached_wc 811 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 812 { 813 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 814 _PAGE_TOLERANT); 815 } 816 817 #define pgprot_cached pgprot_cached 818 static inline pgprot_t pgprot_cached(pgprot_t prot) 819 { 820 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 821 } 822 823 #define pgprot_writecombine pgprot_writecombine 824 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 825 { 826 return pgprot_noncached_wc(prot); 827 } 828 /* 829 * check a pte mapping have cache inhibited property 830 */ 831 static inline bool pte_ci(pte_t pte) 832 { 833 unsigned long pte_v = pte_val(pte); 834 835 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || 836 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) 837 return true; 838 return false; 839 } 840 841 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 842 { 843 *pmdp = __pmd(val); 844 } 845 846 static inline void pmd_clear(pmd_t *pmdp) 847 { 848 *pmdp = __pmd(0); 849 } 850 851 static inline int pmd_none(pmd_t pmd) 852 { 853 return !pmd_raw(pmd); 854 } 855 856 static inline int pmd_present(pmd_t pmd) 857 { 858 859 return !pmd_none(pmd); 860 } 861 862 static inline int pmd_bad(pmd_t pmd) 863 { 864 if (radix_enabled()) 865 return radix__pmd_bad(pmd); 866 return hash__pmd_bad(pmd); 867 } 868 869 static inline void pud_set(pud_t *pudp, unsigned long val) 870 { 871 *pudp = __pud(val); 872 } 873 874 static inline void pud_clear(pud_t *pudp) 875 { 876 *pudp = __pud(0); 877 } 878 879 static inline int pud_none(pud_t pud) 880 { 881 return !pud_raw(pud); 882 } 883 884 static inline int pud_present(pud_t pud) 885 { 886 return !pud_none(pud); 887 } 888 889 extern struct page *pud_page(pud_t pud); 890 extern struct page *pmd_page(pmd_t pmd); 891 static inline pte_t pud_pte(pud_t pud) 892 { 893 return __pte_raw(pud_raw(pud)); 894 } 895 896 static inline pud_t pte_pud(pte_t pte) 897 { 898 return __pud_raw(pte_raw(pte)); 899 } 900 #define pud_write(pud) pte_write(pud_pte(pud)) 901 902 static inline int pud_bad(pud_t pud) 903 { 904 if (radix_enabled()) 905 return radix__pud_bad(pud); 906 return hash__pud_bad(pud); 907 } 908 909 #define pud_access_permitted pud_access_permitted 910 static inline bool pud_access_permitted(pud_t pud, bool write) 911 { 912 return pte_access_permitted(pud_pte(pud), write); 913 } 914 915 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 916 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 917 { 918 *pgdp = __pgd(val); 919 } 920 921 static inline void pgd_clear(pgd_t *pgdp) 922 { 923 *pgdp = __pgd(0); 924 } 925 926 static inline int pgd_none(pgd_t pgd) 927 { 928 return !pgd_raw(pgd); 929 } 930 931 static inline int pgd_present(pgd_t pgd) 932 { 933 return !pgd_none(pgd); 934 } 935 936 static inline pte_t pgd_pte(pgd_t pgd) 937 { 938 return __pte_raw(pgd_raw(pgd)); 939 } 940 941 static inline pgd_t pte_pgd(pte_t pte) 942 { 943 return __pgd_raw(pte_raw(pte)); 944 } 945 946 static inline int pgd_bad(pgd_t pgd) 947 { 948 if (radix_enabled()) 949 return radix__pgd_bad(pgd); 950 return hash__pgd_bad(pgd); 951 } 952 953 #define pgd_access_permitted pgd_access_permitted 954 static inline bool pgd_access_permitted(pgd_t pgd, bool write) 955 { 956 return pte_access_permitted(pgd_pte(pgd), write); 957 } 958 959 extern struct page *pgd_page(pgd_t pgd); 960 961 /* Pointers in the page table tree are physical addresses */ 962 #define __pgtable_ptr_val(ptr) __pa(ptr) 963 964 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 965 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 966 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 967 968 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 969 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 970 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 971 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 972 973 /* 974 * Find an entry in a page-table-directory. We combine the address region 975 * (the high order N bits) and the pgd portion of the address. 976 */ 977 978 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 979 980 #define pud_offset(pgdp, addr) \ 981 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 982 #define pmd_offset(pudp,addr) \ 983 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 984 #define pte_offset_kernel(dir,addr) \ 985 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 986 987 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 988 #define pte_unmap(pte) do { } while(0) 989 990 /* to find an entry in a kernel page-table-directory */ 991 /* This now only contains the vmalloc pages */ 992 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 993 994 #define pte_ERROR(e) \ 995 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 996 #define pmd_ERROR(e) \ 997 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 998 #define pud_ERROR(e) \ 999 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1000 #define pgd_ERROR(e) \ 1001 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1002 1003 static inline int map_kernel_page(unsigned long ea, unsigned long pa, 1004 unsigned long flags) 1005 { 1006 if (radix_enabled()) { 1007 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1008 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1009 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1010 #endif 1011 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); 1012 } 1013 return hash__map_kernel_page(ea, pa, flags); 1014 } 1015 1016 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1017 unsigned long page_size, 1018 unsigned long phys) 1019 { 1020 if (radix_enabled()) 1021 return radix__vmemmap_create_mapping(start, page_size, phys); 1022 return hash__vmemmap_create_mapping(start, page_size, phys); 1023 } 1024 1025 #ifdef CONFIG_MEMORY_HOTPLUG 1026 static inline void vmemmap_remove_mapping(unsigned long start, 1027 unsigned long page_size) 1028 { 1029 if (radix_enabled()) 1030 return radix__vmemmap_remove_mapping(start, page_size); 1031 return hash__vmemmap_remove_mapping(start, page_size); 1032 } 1033 #endif 1034 struct page *realmode_pfn_to_page(unsigned long pfn); 1035 1036 static inline pte_t pmd_pte(pmd_t pmd) 1037 { 1038 return __pte_raw(pmd_raw(pmd)); 1039 } 1040 1041 static inline pmd_t pte_pmd(pte_t pte) 1042 { 1043 return __pmd_raw(pte_raw(pte)); 1044 } 1045 1046 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1047 { 1048 return (pte_t *)pmd; 1049 } 1050 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1051 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1052 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1053 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1054 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1055 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1056 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1057 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1058 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1059 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1060 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1061 1062 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1063 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1064 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1065 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1066 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1067 1068 #ifdef CONFIG_NUMA_BALANCING 1069 static inline int pmd_protnone(pmd_t pmd) 1070 { 1071 return pte_protnone(pmd_pte(pmd)); 1072 } 1073 #endif /* CONFIG_NUMA_BALANCING */ 1074 1075 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1076 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1077 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1078 1079 #define pmd_access_permitted pmd_access_permitted 1080 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1081 { 1082 return pte_access_permitted(pmd_pte(pmd), write); 1083 } 1084 1085 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1086 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1087 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1088 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1089 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1090 pmd_t *pmdp, pmd_t pmd); 1091 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1092 pmd_t *pmd); 1093 extern int hash__has_transparent_hugepage(void); 1094 static inline int has_transparent_hugepage(void) 1095 { 1096 if (radix_enabled()) 1097 return radix__has_transparent_hugepage(); 1098 return hash__has_transparent_hugepage(); 1099 } 1100 #define has_transparent_hugepage has_transparent_hugepage 1101 1102 static inline unsigned long 1103 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1104 unsigned long clr, unsigned long set) 1105 { 1106 if (radix_enabled()) 1107 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1108 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1109 } 1110 1111 static inline int pmd_large(pmd_t pmd) 1112 { 1113 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1114 } 1115 1116 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1117 { 1118 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1119 } 1120 /* 1121 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1122 * the below will work for radix too 1123 */ 1124 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1125 unsigned long addr, pmd_t *pmdp) 1126 { 1127 unsigned long old; 1128 1129 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1130 return 0; 1131 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1132 return ((old & _PAGE_ACCESSED) != 0); 1133 } 1134 1135 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1136 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1137 pmd_t *pmdp) 1138 { 1139 if (__pmd_write((*pmdp))) 1140 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1141 else if (unlikely(pmd_savedwrite(*pmdp))) 1142 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1143 } 1144 1145 static inline int pmd_trans_huge(pmd_t pmd) 1146 { 1147 if (radix_enabled()) 1148 return radix__pmd_trans_huge(pmd); 1149 return hash__pmd_trans_huge(pmd); 1150 } 1151 1152 #define __HAVE_ARCH_PMD_SAME 1153 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1154 { 1155 if (radix_enabled()) 1156 return radix__pmd_same(pmd_a, pmd_b); 1157 return hash__pmd_same(pmd_a, pmd_b); 1158 } 1159 1160 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1161 { 1162 if (radix_enabled()) 1163 return radix__pmd_mkhuge(pmd); 1164 return hash__pmd_mkhuge(pmd); 1165 } 1166 1167 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1168 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1169 unsigned long address, pmd_t *pmdp, 1170 pmd_t entry, int dirty); 1171 1172 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1173 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1174 unsigned long address, pmd_t *pmdp); 1175 1176 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1177 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1178 unsigned long addr, pmd_t *pmdp) 1179 { 1180 if (radix_enabled()) 1181 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1182 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1183 } 1184 1185 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1186 unsigned long address, pmd_t *pmdp) 1187 { 1188 if (radix_enabled()) 1189 return radix__pmdp_collapse_flush(vma, address, pmdp); 1190 return hash__pmdp_collapse_flush(vma, address, pmdp); 1191 } 1192 #define pmdp_collapse_flush pmdp_collapse_flush 1193 1194 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1195 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1196 pmd_t *pmdp, pgtable_t pgtable) 1197 { 1198 if (radix_enabled()) 1199 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1200 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1201 } 1202 1203 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1204 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1205 pmd_t *pmdp) 1206 { 1207 if (radix_enabled()) 1208 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1209 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1210 } 1211 1212 #define __HAVE_ARCH_PMDP_INVALIDATE 1213 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1214 pmd_t *pmdp); 1215 1216 #define pmd_move_must_withdraw pmd_move_must_withdraw 1217 struct spinlock; 1218 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1219 struct spinlock *old_pmd_ptl, 1220 struct vm_area_struct *vma) 1221 { 1222 if (radix_enabled()) 1223 return false; 1224 /* 1225 * Archs like ppc64 use pgtable to store per pmd 1226 * specific information. So when we switch the pmd, 1227 * we should also withdraw and deposit the pgtable 1228 */ 1229 return true; 1230 } 1231 1232 1233 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1234 static inline bool arch_needs_pgtable_deposit(void) 1235 { 1236 if (radix_enabled()) 1237 return false; 1238 return true; 1239 } 1240 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1241 1242 1243 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1244 { 1245 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1246 } 1247 1248 static inline int pmd_devmap(pmd_t pmd) 1249 { 1250 return pte_devmap(pmd_pte(pmd)); 1251 } 1252 1253 static inline int pud_devmap(pud_t pud) 1254 { 1255 return 0; 1256 } 1257 1258 static inline int pgd_devmap(pgd_t pgd) 1259 { 1260 return 0; 1261 } 1262 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1263 1264 static inline const int pud_pfn(pud_t pud) 1265 { 1266 /* 1267 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1268 * check so this should never be used. If it grows another user we 1269 * want to know about it. 1270 */ 1271 BUILD_BUG(); 1272 return 0; 1273 } 1274 1275 #endif /* __ASSEMBLY__ */ 1276 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1277