1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x00040UL 36 37 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 38 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 39 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 40 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 41 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 42 43 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 44 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 45 /* 46 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 47 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 48 * differentiate between two use a SW field when invalidating. 49 * 50 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 51 * 52 * This is used only when _PAGE_PRESENT is cleared. 53 */ 54 #define _PAGE_INVALID _RPAGE_SW0 55 56 /* 57 * Top and bottom bits of RPN which can be used by hash 58 * translation mode, because we expect them to be zero 59 * otherwise. 60 */ 61 #define _RPAGE_RPN0 0x01000 62 #define _RPAGE_RPN1 0x02000 63 #define _RPAGE_RPN43 0x0080000000000000UL 64 #define _RPAGE_RPN42 0x0040000000000000UL 65 #define _RPAGE_RPN41 0x0020000000000000UL 66 67 /* Max physical address bit as per radix table */ 68 #define _RPAGE_PA_MAX 56 69 70 /* 71 * Max physical address bit we will use for now. 72 * 73 * This is mostly a hardware limitation and for now Power9 has 74 * a 51 bit limit. 75 * 76 * This is different from the number of physical bit required to address 77 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 78 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 79 * number of sections we can support (SECTIONS_SHIFT). 80 * 81 * This is different from Radix page table limitation above and 82 * should always be less than that. The limit is done such that 83 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 84 * for hash linux page table specific bits. 85 * 86 * In order to be compatible with future hardware generations we keep 87 * some offsets and limit this for now to 53 88 */ 89 #define _PAGE_PA_MAX 53 90 91 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 92 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 93 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 120 _PAGE_RW | _PAGE_EXEC) 121 /* 122 * _PAGE_CHG_MASK masks of bits that are to be preserved across 123 * pgprot changes 124 */ 125 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 126 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 127 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 128 129 /* 130 * We define 2 sets of base prot bits, one for basic pages (ie, 131 * cacheable kernel and user pages) and one for non cacheable 132 * pages. We always set _PAGE_COHERENT when SMP is enabled or 133 * the processor might need it for DMA coherency. 134 */ 135 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 136 #define _PAGE_BASE (_PAGE_BASE_NC) 137 138 /* Permission masks used to generate the __P and __S table, 139 * 140 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 141 * 142 * Write permissions imply read permissions for now (we could make write-only 143 * pages on BookE but we don't bother for now). Execute permission control is 144 * possible on platforms that define _PAGE_EXEC 145 */ 146 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 147 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 148 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 149 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 150 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 151 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 152 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 153 154 /* Permission masks used for kernel mappings */ 155 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 156 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 157 _PAGE_TOLERANT) 158 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 159 _PAGE_NON_IDEMPOTENT) 160 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 161 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 162 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 163 164 /* 165 * Protection used for kernel text. We want the debuggers to be able to 166 * set breakpoints anywhere, so don't write protect the kernel text 167 * on platforms where such control is possible. 168 */ 169 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 170 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 171 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 172 #else 173 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 174 #endif 175 176 /* Make modules code happy. We don't set RO yet */ 177 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 178 #define PAGE_AGP (PAGE_KERNEL_NC) 179 180 #ifndef __ASSEMBLY__ 181 /* 182 * page table defines 183 */ 184 extern unsigned long __pte_index_size; 185 extern unsigned long __pmd_index_size; 186 extern unsigned long __pud_index_size; 187 extern unsigned long __pgd_index_size; 188 extern unsigned long __pud_cache_index; 189 #define PTE_INDEX_SIZE __pte_index_size 190 #define PMD_INDEX_SIZE __pmd_index_size 191 #define PUD_INDEX_SIZE __pud_index_size 192 #define PGD_INDEX_SIZE __pgd_index_size 193 /* pmd table use page table fragments */ 194 #define PMD_CACHE_INDEX 0 195 #define PUD_CACHE_INDEX __pud_cache_index 196 /* 197 * Because of use of pte fragments and THP, size of page table 198 * are not always derived out of index size above. 199 */ 200 extern unsigned long __pte_table_size; 201 extern unsigned long __pmd_table_size; 202 extern unsigned long __pud_table_size; 203 extern unsigned long __pgd_table_size; 204 #define PTE_TABLE_SIZE __pte_table_size 205 #define PMD_TABLE_SIZE __pmd_table_size 206 #define PUD_TABLE_SIZE __pud_table_size 207 #define PGD_TABLE_SIZE __pgd_table_size 208 209 extern unsigned long __pmd_val_bits; 210 extern unsigned long __pud_val_bits; 211 extern unsigned long __pgd_val_bits; 212 #define PMD_VAL_BITS __pmd_val_bits 213 #define PUD_VAL_BITS __pud_val_bits 214 #define PGD_VAL_BITS __pgd_val_bits 215 216 extern unsigned long __pte_frag_nr; 217 #define PTE_FRAG_NR __pte_frag_nr 218 extern unsigned long __pte_frag_size_shift; 219 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 220 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 221 222 extern unsigned long __pmd_frag_nr; 223 #define PMD_FRAG_NR __pmd_frag_nr 224 extern unsigned long __pmd_frag_size_shift; 225 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 226 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 227 228 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 229 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 230 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 231 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 232 233 /* PMD_SHIFT determines what a second-level page table entry can map */ 234 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 235 #define PMD_SIZE (1UL << PMD_SHIFT) 236 #define PMD_MASK (~(PMD_SIZE-1)) 237 238 /* PUD_SHIFT determines what a third-level page table entry can map */ 239 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 240 #define PUD_SIZE (1UL << PUD_SHIFT) 241 #define PUD_MASK (~(PUD_SIZE-1)) 242 243 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 244 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 245 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 246 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 247 248 /* Bits to mask out from a PMD to get to the PTE page */ 249 #define PMD_MASKED_BITS 0xc0000000000000ffUL 250 /* Bits to mask out from a PUD to get to the PMD page */ 251 #define PUD_MASKED_BITS 0xc0000000000000ffUL 252 /* Bits to mask out from a PGD to get to the PUD page */ 253 #define P4D_MASKED_BITS 0xc0000000000000ffUL 254 255 /* 256 * Used as an indicator for rcu callback functions 257 */ 258 enum pgtable_index { 259 PTE_INDEX = 0, 260 PMD_INDEX, 261 PUD_INDEX, 262 PGD_INDEX, 263 /* 264 * Below are used with 4k page size and hugetlb 265 */ 266 HTLB_16M_INDEX, 267 HTLB_16G_INDEX, 268 }; 269 270 extern unsigned long __vmalloc_start; 271 extern unsigned long __vmalloc_end; 272 #define VMALLOC_START __vmalloc_start 273 #define VMALLOC_END __vmalloc_end 274 275 static inline unsigned int ioremap_max_order(void) 276 { 277 if (radix_enabled()) 278 return PUD_SHIFT; 279 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 280 } 281 #define IOREMAP_MAX_ORDER ioremap_max_order() 282 283 extern unsigned long __kernel_virt_start; 284 extern unsigned long __kernel_io_start; 285 extern unsigned long __kernel_io_end; 286 #define KERN_VIRT_START __kernel_virt_start 287 #define KERN_IO_START __kernel_io_start 288 #define KERN_IO_END __kernel_io_end 289 290 extern struct page *vmemmap; 291 extern unsigned long pci_io_base; 292 #endif /* __ASSEMBLY__ */ 293 294 #include <asm/book3s/64/hash.h> 295 #include <asm/book3s/64/radix.h> 296 297 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 298 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 299 #else 300 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 301 #endif 302 303 304 #ifdef CONFIG_PPC_64K_PAGES 305 #include <asm/book3s/64/pgtable-64k.h> 306 #else 307 #include <asm/book3s/64/pgtable-4k.h> 308 #endif 309 310 #include <asm/barrier.h> 311 /* 312 * IO space itself carved into the PIO region (ISA and PHB IO space) and 313 * the ioremap space 314 * 315 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 316 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 317 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 318 */ 319 #define FULL_IO_SIZE 0x80000000ul 320 #define ISA_IO_BASE (KERN_IO_START) 321 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 322 #define PHB_IO_BASE (ISA_IO_END) 323 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 324 #define IOREMAP_BASE (PHB_IO_END) 325 #define IOREMAP_START (ioremap_bot) 326 #define IOREMAP_END (KERN_IO_END) 327 328 /* Advertise special mapping type for AGP */ 329 #define HAVE_PAGE_AGP 330 331 #ifndef __ASSEMBLY__ 332 333 /* 334 * This is the default implementation of various PTE accessors, it's 335 * used in all cases except Book3S with 64K pages where we have a 336 * concept of sub-pages 337 */ 338 #ifndef __real_pte 339 340 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 341 #define __rpte_to_pte(r) ((r).pte) 342 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 343 344 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 345 do { \ 346 index = 0; \ 347 shift = mmu_psize_defs[psize].shift; \ 348 349 #define pte_iterate_hashed_end() } while(0) 350 351 /* 352 * We expect this to be called only for user addresses or kernel virtual 353 * addresses other than the linear mapping. 354 */ 355 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 356 357 #endif /* __real_pte */ 358 359 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 360 pte_t *ptep, unsigned long clr, 361 unsigned long set, int huge) 362 { 363 if (radix_enabled()) 364 return radix__pte_update(mm, addr, ptep, clr, set, huge); 365 return hash__pte_update(mm, addr, ptep, clr, set, huge); 366 } 367 /* 368 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 369 * We currently remove entries from the hashtable regardless of whether 370 * the entry was young or dirty. 371 * 372 * We should be more intelligent about this but for the moment we override 373 * these functions and force a tlb flush unconditionally 374 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 375 * function for both hash and radix. 376 */ 377 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 378 unsigned long addr, pte_t *ptep) 379 { 380 unsigned long old; 381 382 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 383 return 0; 384 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 385 return (old & _PAGE_ACCESSED) != 0; 386 } 387 388 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 389 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 390 ({ \ 391 int __r; \ 392 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 393 __r; \ 394 }) 395 396 static inline int __pte_write(pte_t pte) 397 { 398 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 399 } 400 401 #ifdef CONFIG_NUMA_BALANCING 402 #define pte_savedwrite pte_savedwrite 403 static inline bool pte_savedwrite(pte_t pte) 404 { 405 /* 406 * Saved write ptes are prot none ptes that doesn't have 407 * privileged bit sit. We mark prot none as one which has 408 * present and pviliged bit set and RWX cleared. To mark 409 * protnone which used to have _PAGE_WRITE set we clear 410 * the privileged bit. 411 */ 412 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 413 } 414 #else 415 #define pte_savedwrite pte_savedwrite 416 static inline bool pte_savedwrite(pte_t pte) 417 { 418 return false; 419 } 420 #endif 421 422 static inline int pte_write(pte_t pte) 423 { 424 return __pte_write(pte) || pte_savedwrite(pte); 425 } 426 427 static inline int pte_read(pte_t pte) 428 { 429 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 430 } 431 432 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 433 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 434 pte_t *ptep) 435 { 436 if (__pte_write(*ptep)) 437 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 438 else if (unlikely(pte_savedwrite(*ptep))) 439 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 440 } 441 442 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 443 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 444 unsigned long addr, pte_t *ptep) 445 { 446 /* 447 * We should not find protnone for hugetlb, but this complete the 448 * interface. 449 */ 450 if (__pte_write(*ptep)) 451 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 452 else if (unlikely(pte_savedwrite(*ptep))) 453 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 454 } 455 456 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 457 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 458 unsigned long addr, pte_t *ptep) 459 { 460 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 461 return __pte(old); 462 } 463 464 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 465 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 466 unsigned long addr, 467 pte_t *ptep, int full) 468 { 469 if (full && radix_enabled()) { 470 /* 471 * We know that this is a full mm pte clear and 472 * hence can be sure there is no parallel set_pte. 473 */ 474 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 475 } 476 return ptep_get_and_clear(mm, addr, ptep); 477 } 478 479 480 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 481 pte_t * ptep) 482 { 483 pte_update(mm, addr, ptep, ~0UL, 0, 0); 484 } 485 486 static inline int pte_dirty(pte_t pte) 487 { 488 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 489 } 490 491 static inline int pte_young(pte_t pte) 492 { 493 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 494 } 495 496 static inline int pte_special(pte_t pte) 497 { 498 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 499 } 500 501 static inline bool pte_exec(pte_t pte) 502 { 503 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 504 } 505 506 507 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 508 static inline bool pte_soft_dirty(pte_t pte) 509 { 510 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 511 } 512 513 static inline pte_t pte_mksoft_dirty(pte_t pte) 514 { 515 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 516 } 517 518 static inline pte_t pte_clear_soft_dirty(pte_t pte) 519 { 520 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 521 } 522 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 523 524 #ifdef CONFIG_NUMA_BALANCING 525 static inline int pte_protnone(pte_t pte) 526 { 527 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 528 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 529 } 530 531 #define pte_mk_savedwrite pte_mk_savedwrite 532 static inline pte_t pte_mk_savedwrite(pte_t pte) 533 { 534 /* 535 * Used by Autonuma subsystem to preserve the write bit 536 * while marking the pte PROT_NONE. Only allow this 537 * on PROT_NONE pte 538 */ 539 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 540 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 541 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 542 } 543 544 #define pte_clear_savedwrite pte_clear_savedwrite 545 static inline pte_t pte_clear_savedwrite(pte_t pte) 546 { 547 /* 548 * Used by KSM subsystem to make a protnone pte readonly. 549 */ 550 VM_BUG_ON(!pte_protnone(pte)); 551 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 552 } 553 #else 554 #define pte_clear_savedwrite pte_clear_savedwrite 555 static inline pte_t pte_clear_savedwrite(pte_t pte) 556 { 557 VM_WARN_ON(1); 558 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 559 } 560 #endif /* CONFIG_NUMA_BALANCING */ 561 562 static inline bool pte_hw_valid(pte_t pte) 563 { 564 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 565 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 566 } 567 568 static inline int pte_present(pte_t pte) 569 { 570 /* 571 * A pte is considerent present if _PAGE_PRESENT is set. 572 * We also need to consider the pte present which is marked 573 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 574 * if we find _PAGE_PRESENT cleared. 575 */ 576 577 if (pte_hw_valid(pte)) 578 return true; 579 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 580 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 581 } 582 583 #ifdef CONFIG_PPC_MEM_KEYS 584 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 585 #else 586 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 587 { 588 return true; 589 } 590 #endif /* CONFIG_PPC_MEM_KEYS */ 591 592 static inline bool pte_user(pte_t pte) 593 { 594 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 595 } 596 597 #define pte_access_permitted pte_access_permitted 598 static inline bool pte_access_permitted(pte_t pte, bool write) 599 { 600 /* 601 * _PAGE_READ is needed for any access and will be 602 * cleared for PROT_NONE 603 */ 604 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 605 return false; 606 607 if (write && !pte_write(pte)) 608 return false; 609 610 return arch_pte_access_permitted(pte_val(pte), write, 0); 611 } 612 613 /* 614 * Conversion functions: convert a page and protection to a page entry, 615 * and a page entry and page directory to the page they refer to. 616 * 617 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 618 * long for now. 619 */ 620 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 621 { 622 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 623 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 624 625 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 626 } 627 628 static inline unsigned long pte_pfn(pte_t pte) 629 { 630 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 631 } 632 633 /* Generic modifiers for PTE bits */ 634 static inline pte_t pte_wrprotect(pte_t pte) 635 { 636 if (unlikely(pte_savedwrite(pte))) 637 return pte_clear_savedwrite(pte); 638 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 639 } 640 641 static inline pte_t pte_exprotect(pte_t pte) 642 { 643 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 644 } 645 646 static inline pte_t pte_mkclean(pte_t pte) 647 { 648 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 649 } 650 651 static inline pte_t pte_mkold(pte_t pte) 652 { 653 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 654 } 655 656 static inline pte_t pte_mkexec(pte_t pte) 657 { 658 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 659 } 660 661 static inline pte_t pte_mkwrite(pte_t pte) 662 { 663 /* 664 * write implies read, hence set both 665 */ 666 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 667 } 668 669 static inline pte_t pte_mkdirty(pte_t pte) 670 { 671 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 672 } 673 674 static inline pte_t pte_mkyoung(pte_t pte) 675 { 676 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 677 } 678 679 static inline pte_t pte_mkspecial(pte_t pte) 680 { 681 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 682 } 683 684 static inline pte_t pte_mkhuge(pte_t pte) 685 { 686 return pte; 687 } 688 689 static inline pte_t pte_mkdevmap(pte_t pte) 690 { 691 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 692 } 693 694 static inline pte_t pte_mkprivileged(pte_t pte) 695 { 696 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 697 } 698 699 static inline pte_t pte_mkuser(pte_t pte) 700 { 701 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 702 } 703 704 /* 705 * This is potentially called with a pmd as the argument, in which case it's not 706 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 707 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 708 * use in page directory entries (ie. non-ptes). 709 */ 710 static inline int pte_devmap(pte_t pte) 711 { 712 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 713 714 return (pte_raw(pte) & mask) == mask; 715 } 716 717 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 718 { 719 /* FIXME!! check whether this need to be a conditional */ 720 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 721 cpu_to_be64(pgprot_val(newprot))); 722 } 723 724 /* Encode and de-code a swap entry */ 725 #define MAX_SWAPFILES_CHECK() do { \ 726 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 727 /* \ 728 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 729 * We filter HPTEFLAGS on set_pte. \ 730 */ \ 731 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 732 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 733 } while (0) 734 735 #define SWP_TYPE_BITS 5 736 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 737 & ((1UL << SWP_TYPE_BITS) - 1)) 738 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 739 #define __swp_entry(type, offset) ((swp_entry_t) { \ 740 ((type) << _PAGE_BIT_SWAP_TYPE) \ 741 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 742 /* 743 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 744 * swap type and offset we get from swap and convert that to pte to find a 745 * matching pte in linux page table. 746 * Clear bits not found in swap entries here. 747 */ 748 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 749 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 750 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 751 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 752 753 #ifdef CONFIG_MEM_SOFT_DIRTY 754 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 755 #else 756 #define _PAGE_SWP_SOFT_DIRTY 0UL 757 #endif /* CONFIG_MEM_SOFT_DIRTY */ 758 759 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 760 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 761 { 762 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 763 } 764 765 static inline bool pte_swp_soft_dirty(pte_t pte) 766 { 767 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 768 } 769 770 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 771 { 772 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 773 } 774 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 775 776 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 777 { 778 /* 779 * This check for _PAGE_RWX and _PAGE_PRESENT bits 780 */ 781 if (access & ~ptev) 782 return false; 783 /* 784 * This check for access to privilege space 785 */ 786 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 787 return false; 788 789 return true; 790 } 791 /* 792 * Generic functions with hash/radix callbacks 793 */ 794 795 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 796 pte_t *ptep, pte_t entry, 797 unsigned long address, 798 int psize) 799 { 800 if (radix_enabled()) 801 return radix__ptep_set_access_flags(vma, ptep, entry, 802 address, psize); 803 return hash__ptep_set_access_flags(ptep, entry); 804 } 805 806 #define __HAVE_ARCH_PTE_SAME 807 static inline int pte_same(pte_t pte_a, pte_t pte_b) 808 { 809 if (radix_enabled()) 810 return radix__pte_same(pte_a, pte_b); 811 return hash__pte_same(pte_a, pte_b); 812 } 813 814 static inline int pte_none(pte_t pte) 815 { 816 if (radix_enabled()) 817 return radix__pte_none(pte); 818 return hash__pte_none(pte); 819 } 820 821 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 822 pte_t *ptep, pte_t pte, int percpu) 823 { 824 825 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 826 /* 827 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 828 * in all the callers. 829 */ 830 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 831 832 if (radix_enabled()) 833 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 834 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 835 } 836 837 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 838 839 #define pgprot_noncached pgprot_noncached 840 static inline pgprot_t pgprot_noncached(pgprot_t prot) 841 { 842 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 843 _PAGE_NON_IDEMPOTENT); 844 } 845 846 #define pgprot_noncached_wc pgprot_noncached_wc 847 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 848 { 849 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 850 _PAGE_TOLERANT); 851 } 852 853 #define pgprot_cached pgprot_cached 854 static inline pgprot_t pgprot_cached(pgprot_t prot) 855 { 856 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 857 } 858 859 #define pgprot_writecombine pgprot_writecombine 860 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 861 { 862 return pgprot_noncached_wc(prot); 863 } 864 /* 865 * check a pte mapping have cache inhibited property 866 */ 867 static inline bool pte_ci(pte_t pte) 868 { 869 __be64 pte_v = pte_raw(pte); 870 871 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 872 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 873 return true; 874 return false; 875 } 876 877 static inline void pmd_clear(pmd_t *pmdp) 878 { 879 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 880 /* 881 * Don't use this if we can possibly have a hash page table 882 * entry mapping this. 883 */ 884 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 885 } 886 *pmdp = __pmd(0); 887 } 888 889 static inline int pmd_none(pmd_t pmd) 890 { 891 return !pmd_raw(pmd); 892 } 893 894 static inline int pmd_present(pmd_t pmd) 895 { 896 /* 897 * A pmd is considerent present if _PAGE_PRESENT is set. 898 * We also need to consider the pmd present which is marked 899 * invalid during a split. Hence we look for _PAGE_INVALID 900 * if we find _PAGE_PRESENT cleared. 901 */ 902 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 903 return true; 904 905 return false; 906 } 907 908 static inline int pmd_is_serializing(pmd_t pmd) 909 { 910 /* 911 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 912 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 913 * 914 * This condition may also occur when flushing a pmd while flushing 915 * it (see ptep_modify_prot_start), so callers must ensure this 916 * case is fine as well. 917 */ 918 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 919 cpu_to_be64(_PAGE_INVALID)) 920 return true; 921 922 return false; 923 } 924 925 static inline int pmd_bad(pmd_t pmd) 926 { 927 if (radix_enabled()) 928 return radix__pmd_bad(pmd); 929 return hash__pmd_bad(pmd); 930 } 931 932 static inline void pud_clear(pud_t *pudp) 933 { 934 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 935 /* 936 * Don't use this if we can possibly have a hash page table 937 * entry mapping this. 938 */ 939 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 940 } 941 *pudp = __pud(0); 942 } 943 944 static inline int pud_none(pud_t pud) 945 { 946 return !pud_raw(pud); 947 } 948 949 static inline int pud_present(pud_t pud) 950 { 951 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 952 } 953 954 extern struct page *pud_page(pud_t pud); 955 extern struct page *pmd_page(pmd_t pmd); 956 static inline pte_t pud_pte(pud_t pud) 957 { 958 return __pte_raw(pud_raw(pud)); 959 } 960 961 static inline pud_t pte_pud(pte_t pte) 962 { 963 return __pud_raw(pte_raw(pte)); 964 } 965 #define pud_write(pud) pte_write(pud_pte(pud)) 966 967 static inline int pud_bad(pud_t pud) 968 { 969 if (radix_enabled()) 970 return radix__pud_bad(pud); 971 return hash__pud_bad(pud); 972 } 973 974 #define pud_access_permitted pud_access_permitted 975 static inline bool pud_access_permitted(pud_t pud, bool write) 976 { 977 return pte_access_permitted(pud_pte(pud), write); 978 } 979 980 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 981 static inline __be64 p4d_raw(p4d_t x) 982 { 983 return pgd_raw(x.pgd); 984 } 985 986 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 987 988 static inline void p4d_clear(p4d_t *p4dp) 989 { 990 *p4dp = __p4d(0); 991 } 992 993 static inline int p4d_none(p4d_t p4d) 994 { 995 return !p4d_raw(p4d); 996 } 997 998 static inline int p4d_present(p4d_t p4d) 999 { 1000 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 1001 } 1002 1003 static inline pte_t p4d_pte(p4d_t p4d) 1004 { 1005 return __pte_raw(p4d_raw(p4d)); 1006 } 1007 1008 static inline p4d_t pte_p4d(pte_t pte) 1009 { 1010 return __p4d_raw(pte_raw(pte)); 1011 } 1012 1013 static inline int p4d_bad(p4d_t p4d) 1014 { 1015 if (radix_enabled()) 1016 return radix__p4d_bad(p4d); 1017 return hash__p4d_bad(p4d); 1018 } 1019 1020 #define p4d_access_permitted p4d_access_permitted 1021 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 1022 { 1023 return pte_access_permitted(p4d_pte(p4d), write); 1024 } 1025 1026 extern struct page *p4d_page(p4d_t p4d); 1027 1028 /* Pointers in the page table tree are physical addresses */ 1029 #define __pgtable_ptr_val(ptr) __pa(ptr) 1030 1031 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 1032 #define p4d_page_vaddr(p4d) __va(p4d_val(p4d) & ~P4D_MASKED_BITS) 1033 1034 #define pte_ERROR(e) \ 1035 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1036 #define pmd_ERROR(e) \ 1037 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1038 #define pud_ERROR(e) \ 1039 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1040 #define pgd_ERROR(e) \ 1041 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1042 1043 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1044 { 1045 if (radix_enabled()) { 1046 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1047 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1048 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1049 #endif 1050 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1051 } 1052 return hash__map_kernel_page(ea, pa, prot); 1053 } 1054 1055 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1056 unsigned long page_size, 1057 unsigned long phys) 1058 { 1059 if (radix_enabled()) 1060 return radix__vmemmap_create_mapping(start, page_size, phys); 1061 return hash__vmemmap_create_mapping(start, page_size, phys); 1062 } 1063 1064 #ifdef CONFIG_MEMORY_HOTPLUG 1065 static inline void vmemmap_remove_mapping(unsigned long start, 1066 unsigned long page_size) 1067 { 1068 if (radix_enabled()) 1069 return radix__vmemmap_remove_mapping(start, page_size); 1070 return hash__vmemmap_remove_mapping(start, page_size); 1071 } 1072 #endif 1073 1074 static inline pte_t pmd_pte(pmd_t pmd) 1075 { 1076 return __pte_raw(pmd_raw(pmd)); 1077 } 1078 1079 static inline pmd_t pte_pmd(pte_t pte) 1080 { 1081 return __pmd_raw(pte_raw(pte)); 1082 } 1083 1084 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1085 { 1086 return (pte_t *)pmd; 1087 } 1088 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1089 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1090 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1091 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1092 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1093 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1094 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1095 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1096 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1097 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1098 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1099 1100 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1101 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1102 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1103 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1104 1105 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1106 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1107 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1108 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1109 #endif 1110 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1111 1112 #ifdef CONFIG_NUMA_BALANCING 1113 static inline int pmd_protnone(pmd_t pmd) 1114 { 1115 return pte_protnone(pmd_pte(pmd)); 1116 } 1117 #endif /* CONFIG_NUMA_BALANCING */ 1118 1119 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1120 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1121 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1122 1123 #define pmd_access_permitted pmd_access_permitted 1124 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1125 { 1126 /* 1127 * pmdp_invalidate sets this combination (which is not caught by 1128 * !pte_present() check in pte_access_permitted), to prevent 1129 * lock-free lookups, as part of the serialize_against_pte_lookup() 1130 * synchronisation. 1131 * 1132 * This also catches the case where the PTE's hardware PRESENT bit is 1133 * cleared while TLB is flushed, which is suboptimal but should not 1134 * be frequent. 1135 */ 1136 if (pmd_is_serializing(pmd)) 1137 return false; 1138 1139 return pte_access_permitted(pmd_pte(pmd), write); 1140 } 1141 1142 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1143 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1144 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1145 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1146 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1147 pmd_t *pmdp, pmd_t pmd); 1148 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1149 unsigned long addr, pmd_t *pmd) 1150 { 1151 } 1152 1153 extern int hash__has_transparent_hugepage(void); 1154 static inline int has_transparent_hugepage(void) 1155 { 1156 if (radix_enabled()) 1157 return radix__has_transparent_hugepage(); 1158 return hash__has_transparent_hugepage(); 1159 } 1160 #define has_transparent_hugepage has_transparent_hugepage 1161 1162 static inline unsigned long 1163 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1164 unsigned long clr, unsigned long set) 1165 { 1166 if (radix_enabled()) 1167 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1168 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1169 } 1170 1171 /* 1172 * returns true for pmd migration entries, THP, devmap, hugetlb 1173 * But compile time dependent on THP config 1174 */ 1175 static inline int pmd_large(pmd_t pmd) 1176 { 1177 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1178 } 1179 1180 /* 1181 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1182 * the below will work for radix too 1183 */ 1184 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1185 unsigned long addr, pmd_t *pmdp) 1186 { 1187 unsigned long old; 1188 1189 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1190 return 0; 1191 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1192 return ((old & _PAGE_ACCESSED) != 0); 1193 } 1194 1195 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1196 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1197 pmd_t *pmdp) 1198 { 1199 if (__pmd_write((*pmdp))) 1200 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1201 else if (unlikely(pmd_savedwrite(*pmdp))) 1202 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1203 } 1204 1205 /* 1206 * Only returns true for a THP. False for pmd migration entry. 1207 * We also need to return true when we come across a pte that 1208 * in between a thp split. While splitting THP, we mark the pmd 1209 * invalid (pmdp_invalidate()) before we set it with pte page 1210 * address. A pmd_trans_huge() check against a pmd entry during that time 1211 * should return true. 1212 * We should not call this on a hugetlb entry. We should check for HugeTLB 1213 * entry using vma->vm_flags 1214 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1215 */ 1216 static inline int pmd_trans_huge(pmd_t pmd) 1217 { 1218 if (!pmd_present(pmd)) 1219 return false; 1220 1221 if (radix_enabled()) 1222 return radix__pmd_trans_huge(pmd); 1223 return hash__pmd_trans_huge(pmd); 1224 } 1225 1226 #define __HAVE_ARCH_PMD_SAME 1227 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1228 { 1229 if (radix_enabled()) 1230 return radix__pmd_same(pmd_a, pmd_b); 1231 return hash__pmd_same(pmd_a, pmd_b); 1232 } 1233 1234 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1235 { 1236 if (radix_enabled()) 1237 return radix__pmd_mkhuge(pmd); 1238 return hash__pmd_mkhuge(pmd); 1239 } 1240 1241 /* 1242 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1243 */ 1244 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1245 { 1246 #ifdef CONFIG_DEBUG_VM 1247 if (radix_enabled()) 1248 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1249 else 1250 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1251 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1252 #endif 1253 return pmd; 1254 } 1255 1256 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1257 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1258 unsigned long address, pmd_t *pmdp, 1259 pmd_t entry, int dirty); 1260 1261 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1262 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1263 unsigned long address, pmd_t *pmdp); 1264 1265 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1266 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1267 unsigned long addr, pmd_t *pmdp) 1268 { 1269 if (radix_enabled()) 1270 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1271 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1272 } 1273 1274 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1275 unsigned long address, pmd_t *pmdp) 1276 { 1277 if (radix_enabled()) 1278 return radix__pmdp_collapse_flush(vma, address, pmdp); 1279 return hash__pmdp_collapse_flush(vma, address, pmdp); 1280 } 1281 #define pmdp_collapse_flush pmdp_collapse_flush 1282 1283 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1284 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1285 unsigned long addr, 1286 pmd_t *pmdp, int full); 1287 1288 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1289 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1290 pmd_t *pmdp, pgtable_t pgtable) 1291 { 1292 if (radix_enabled()) 1293 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1294 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1295 } 1296 1297 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1298 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1299 pmd_t *pmdp) 1300 { 1301 if (radix_enabled()) 1302 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1303 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1304 } 1305 1306 #define __HAVE_ARCH_PMDP_INVALIDATE 1307 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1308 pmd_t *pmdp); 1309 1310 #define pmd_move_must_withdraw pmd_move_must_withdraw 1311 struct spinlock; 1312 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1313 struct spinlock *old_pmd_ptl, 1314 struct vm_area_struct *vma); 1315 /* 1316 * Hash translation mode use the deposited table to store hash pte 1317 * slot information. 1318 */ 1319 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1320 static inline bool arch_needs_pgtable_deposit(void) 1321 { 1322 if (radix_enabled()) 1323 return false; 1324 return true; 1325 } 1326 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1327 1328 1329 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1330 { 1331 if (radix_enabled()) 1332 return radix__pmd_mkdevmap(pmd); 1333 return hash__pmd_mkdevmap(pmd); 1334 } 1335 1336 static inline int pmd_devmap(pmd_t pmd) 1337 { 1338 return pte_devmap(pmd_pte(pmd)); 1339 } 1340 1341 static inline int pud_devmap(pud_t pud) 1342 { 1343 return 0; 1344 } 1345 1346 static inline int pgd_devmap(pgd_t pgd) 1347 { 1348 return 0; 1349 } 1350 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1351 1352 static inline int pud_pfn(pud_t pud) 1353 { 1354 /* 1355 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1356 * check so this should never be used. If it grows another user we 1357 * want to know about it. 1358 */ 1359 BUILD_BUG(); 1360 return 0; 1361 } 1362 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1363 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1364 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1365 pte_t *, pte_t, pte_t); 1366 1367 /* 1368 * Returns true for a R -> RW upgrade of pte 1369 */ 1370 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1371 { 1372 if (!(old_val & _PAGE_READ)) 1373 return false; 1374 1375 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1376 return true; 1377 1378 return false; 1379 } 1380 1381 /* 1382 * Like pmd_huge() and pmd_large(), but works regardless of config options 1383 */ 1384 #define pmd_is_leaf pmd_is_leaf 1385 #define pmd_leaf pmd_is_leaf 1386 static inline bool pmd_is_leaf(pmd_t pmd) 1387 { 1388 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1389 } 1390 1391 #define pud_is_leaf pud_is_leaf 1392 #define pud_leaf pud_is_leaf 1393 static inline bool pud_is_leaf(pud_t pud) 1394 { 1395 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1396 } 1397 1398 #define p4d_is_leaf p4d_is_leaf 1399 #define p4d_leaf p4d_is_leaf 1400 static inline bool p4d_is_leaf(p4d_t p4d) 1401 { 1402 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PTE)); 1403 } 1404 1405 #endif /* __ASSEMBLY__ */ 1406 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1407