1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/5level-fixup.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_RO 0 18 #define _PAGE_SHARED 0 19 20 #define _PAGE_EXEC 0x00001 /* execute permission */ 21 #define _PAGE_WRITE 0x00002 /* write access allowed */ 22 #define _PAGE_READ 0x00004 /* read access allowed */ 23 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 24 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 25 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 26 #define _PAGE_SAO 0x00010 /* Strong access order */ 27 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 28 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 29 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 30 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 31 /* 32 * Software bits 33 */ 34 #define _RPAGE_SW0 0x2000000000000000UL 35 #define _RPAGE_SW1 0x00800 36 #define _RPAGE_SW2 0x00400 37 #define _RPAGE_SW3 0x00200 38 #define _RPAGE_RSV1 0x1000000000000000UL 39 #define _RPAGE_RSV2 0x0800000000000000UL 40 #define _RPAGE_RSV3 0x0400000000000000UL 41 #define _RPAGE_RSV4 0x0200000000000000UL 42 43 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 44 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 45 46 /* 47 * Top and bottom bits of RPN which can be used by hash 48 * translation mode, because we expect them to be zero 49 * otherwise. 50 */ 51 #define _RPAGE_RPN0 0x01000 52 #define _RPAGE_RPN1 0x02000 53 #define _RPAGE_RPN44 0x0100000000000000UL 54 #define _RPAGE_RPN43 0x0080000000000000UL 55 #define _RPAGE_RPN42 0x0040000000000000UL 56 #define _RPAGE_RPN41 0x0020000000000000UL 57 58 /* Max physical address bit as per radix table */ 59 #define _RPAGE_PA_MAX 57 60 61 /* 62 * Max physical address bit we will use for now. 63 * 64 * This is mostly a hardware limitation and for now Power9 has 65 * a 51 bit limit. 66 * 67 * This is different from the number of physical bit required to address 68 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 69 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 70 * number of sections we can support (SECTIONS_SHIFT). 71 * 72 * This is different from Radix page table limitation above and 73 * should always be less than that. The limit is done such that 74 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 75 * for hash linux page table specific bits. 76 * 77 * In order to be compatible with future hardware generations we keep 78 * some offsets and limit this for now to 53 79 */ 80 #define _PAGE_PA_MAX 53 81 82 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 83 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 84 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 85 #define __HAVE_ARCH_PTE_DEVMAP 86 87 /* 88 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 89 * Instead of fixing all of them, add an alternate define which 90 * maps CI pte mapping. 91 */ 92 #define _PAGE_NO_CACHE _PAGE_TOLERANT 93 /* 94 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 95 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 96 * and every thing below PAGE_SHIFT; 97 */ 98 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 99 /* 100 * set of bits not changed in pmd_modify. Even though we have hash specific bits 101 * in here, on radix we expect them to be zero. 102 */ 103 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 104 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 105 _PAGE_SOFT_DIRTY) 106 /* 107 * user access blocked by key 108 */ 109 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 110 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 111 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 112 _PAGE_RW | _PAGE_EXEC) 113 /* 114 * No page size encoding in the linux PTE 115 */ 116 #define _PAGE_PSIZE 0 117 /* 118 * _PAGE_CHG_MASK masks of bits that are to be preserved across 119 * pgprot changes 120 */ 121 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 122 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 123 _PAGE_SOFT_DIRTY) 124 /* 125 * Mask of bits returned by pte_pgprot() 126 */ 127 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ 128 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ 129 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ 130 _PAGE_SOFT_DIRTY) 131 /* 132 * We define 2 sets of base prot bits, one for basic pages (ie, 133 * cacheable kernel and user pages) and one for non cacheable 134 * pages. We always set _PAGE_COHERENT when SMP is enabled or 135 * the processor might need it for DMA coherency. 136 */ 137 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 138 #define _PAGE_BASE (_PAGE_BASE_NC) 139 140 /* Permission masks used to generate the __P and __S table, 141 * 142 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 143 * 144 * Write permissions imply read permissions for now (we could make write-only 145 * pages on BookE but we don't bother for now). Execute permission control is 146 * possible on platforms that define _PAGE_EXEC 147 * 148 * Note due to the way vm flags are laid out, the bits are XWR 149 */ 150 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 151 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 152 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 153 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 154 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 155 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 156 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 157 158 #define __P000 PAGE_NONE 159 #define __P001 PAGE_READONLY 160 #define __P010 PAGE_COPY 161 #define __P011 PAGE_COPY 162 #define __P100 PAGE_READONLY_X 163 #define __P101 PAGE_READONLY_X 164 #define __P110 PAGE_COPY_X 165 #define __P111 PAGE_COPY_X 166 167 #define __S000 PAGE_NONE 168 #define __S001 PAGE_READONLY 169 #define __S010 PAGE_SHARED 170 #define __S011 PAGE_SHARED 171 #define __S100 PAGE_READONLY_X 172 #define __S101 PAGE_READONLY_X 173 #define __S110 PAGE_SHARED_X 174 #define __S111 PAGE_SHARED_X 175 176 /* Permission masks used for kernel mappings */ 177 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 178 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 179 _PAGE_TOLERANT) 180 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 181 _PAGE_NON_IDEMPOTENT) 182 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 183 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 184 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 185 186 /* 187 * Protection used for kernel text. We want the debuggers to be able to 188 * set breakpoints anywhere, so don't write protect the kernel text 189 * on platforms where such control is possible. 190 */ 191 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 192 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 193 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 194 #else 195 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 196 #endif 197 198 /* Make modules code happy. We don't set RO yet */ 199 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 200 #define PAGE_AGP (PAGE_KERNEL_NC) 201 202 #ifndef __ASSEMBLY__ 203 /* 204 * page table defines 205 */ 206 extern unsigned long __pte_index_size; 207 extern unsigned long __pmd_index_size; 208 extern unsigned long __pud_index_size; 209 extern unsigned long __pgd_index_size; 210 extern unsigned long __pmd_cache_index; 211 #define PTE_INDEX_SIZE __pte_index_size 212 #define PMD_INDEX_SIZE __pmd_index_size 213 #define PUD_INDEX_SIZE __pud_index_size 214 #define PGD_INDEX_SIZE __pgd_index_size 215 #define PMD_CACHE_INDEX __pmd_cache_index 216 /* 217 * Because of use of pte fragments and THP, size of page table 218 * are not always derived out of index size above. 219 */ 220 extern unsigned long __pte_table_size; 221 extern unsigned long __pmd_table_size; 222 extern unsigned long __pud_table_size; 223 extern unsigned long __pgd_table_size; 224 #define PTE_TABLE_SIZE __pte_table_size 225 #define PMD_TABLE_SIZE __pmd_table_size 226 #define PUD_TABLE_SIZE __pud_table_size 227 #define PGD_TABLE_SIZE __pgd_table_size 228 229 extern unsigned long __pmd_val_bits; 230 extern unsigned long __pud_val_bits; 231 extern unsigned long __pgd_val_bits; 232 #define PMD_VAL_BITS __pmd_val_bits 233 #define PUD_VAL_BITS __pud_val_bits 234 #define PGD_VAL_BITS __pgd_val_bits 235 236 extern unsigned long __pte_frag_nr; 237 #define PTE_FRAG_NR __pte_frag_nr 238 extern unsigned long __pte_frag_size_shift; 239 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 240 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 241 242 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 243 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 244 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 245 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 246 247 /* PMD_SHIFT determines what a second-level page table entry can map */ 248 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 249 #define PMD_SIZE (1UL << PMD_SHIFT) 250 #define PMD_MASK (~(PMD_SIZE-1)) 251 252 /* PUD_SHIFT determines what a third-level page table entry can map */ 253 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 254 #define PUD_SIZE (1UL << PUD_SHIFT) 255 #define PUD_MASK (~(PUD_SIZE-1)) 256 257 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 258 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 259 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 260 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 261 262 /* Bits to mask out from a PMD to get to the PTE page */ 263 #define PMD_MASKED_BITS 0xc0000000000000ffUL 264 /* Bits to mask out from a PUD to get to the PMD page */ 265 #define PUD_MASKED_BITS 0xc0000000000000ffUL 266 /* Bits to mask out from a PGD to get to the PUD page */ 267 #define PGD_MASKED_BITS 0xc0000000000000ffUL 268 269 extern unsigned long __vmalloc_start; 270 extern unsigned long __vmalloc_end; 271 #define VMALLOC_START __vmalloc_start 272 #define VMALLOC_END __vmalloc_end 273 274 extern unsigned long __kernel_virt_start; 275 extern unsigned long __kernel_virt_size; 276 extern unsigned long __kernel_io_start; 277 #define KERN_VIRT_START __kernel_virt_start 278 #define KERN_VIRT_SIZE __kernel_virt_size 279 #define KERN_IO_START __kernel_io_start 280 extern struct page *vmemmap; 281 extern unsigned long ioremap_bot; 282 extern unsigned long pci_io_base; 283 #endif /* __ASSEMBLY__ */ 284 285 #include <asm/book3s/64/hash.h> 286 #include <asm/book3s/64/radix.h> 287 288 #ifdef CONFIG_PPC_64K_PAGES 289 #include <asm/book3s/64/pgtable-64k.h> 290 #else 291 #include <asm/book3s/64/pgtable-4k.h> 292 #endif 293 294 #include <asm/barrier.h> 295 /* 296 * The second half of the kernel virtual space is used for IO mappings, 297 * it's itself carved into the PIO region (ISA and PHB IO space) and 298 * the ioremap space 299 * 300 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 301 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 302 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 303 */ 304 #define FULL_IO_SIZE 0x80000000ul 305 #define ISA_IO_BASE (KERN_IO_START) 306 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 307 #define PHB_IO_BASE (ISA_IO_END) 308 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 309 #define IOREMAP_BASE (PHB_IO_END) 310 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 311 312 /* Advertise special mapping type for AGP */ 313 #define HAVE_PAGE_AGP 314 315 /* Advertise support for _PAGE_SPECIAL */ 316 #define __HAVE_ARCH_PTE_SPECIAL 317 318 #ifndef __ASSEMBLY__ 319 320 /* 321 * This is the default implementation of various PTE accessors, it's 322 * used in all cases except Book3S with 64K pages where we have a 323 * concept of sub-pages 324 */ 325 #ifndef __real_pte 326 327 #define __real_pte(e,p) ((real_pte_t){(e)}) 328 #define __rpte_to_pte(r) ((r).pte) 329 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 330 331 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 332 do { \ 333 index = 0; \ 334 shift = mmu_psize_defs[psize].shift; \ 335 336 #define pte_iterate_hashed_end() } while(0) 337 338 /* 339 * We expect this to be called only for user addresses or kernel virtual 340 * addresses other than the linear mapping. 341 */ 342 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 343 344 #endif /* __real_pte */ 345 346 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 347 pte_t *ptep, unsigned long clr, 348 unsigned long set, int huge) 349 { 350 if (radix_enabled()) 351 return radix__pte_update(mm, addr, ptep, clr, set, huge); 352 return hash__pte_update(mm, addr, ptep, clr, set, huge); 353 } 354 /* 355 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 356 * We currently remove entries from the hashtable regardless of whether 357 * the entry was young or dirty. 358 * 359 * We should be more intelligent about this but for the moment we override 360 * these functions and force a tlb flush unconditionally 361 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 362 * function for both hash and radix. 363 */ 364 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 365 unsigned long addr, pte_t *ptep) 366 { 367 unsigned long old; 368 369 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 370 return 0; 371 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 372 return (old & _PAGE_ACCESSED) != 0; 373 } 374 375 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 376 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 377 ({ \ 378 int __r; \ 379 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 380 __r; \ 381 }) 382 383 static inline int __pte_write(pte_t pte) 384 { 385 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 386 } 387 388 #ifdef CONFIG_NUMA_BALANCING 389 #define pte_savedwrite pte_savedwrite 390 static inline bool pte_savedwrite(pte_t pte) 391 { 392 /* 393 * Saved write ptes are prot none ptes that doesn't have 394 * privileged bit sit. We mark prot none as one which has 395 * present and pviliged bit set and RWX cleared. To mark 396 * protnone which used to have _PAGE_WRITE set we clear 397 * the privileged bit. 398 */ 399 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 400 } 401 #else 402 #define pte_savedwrite pte_savedwrite 403 static inline bool pte_savedwrite(pte_t pte) 404 { 405 return false; 406 } 407 #endif 408 409 static inline int pte_write(pte_t pte) 410 { 411 return __pte_write(pte) || pte_savedwrite(pte); 412 } 413 414 static inline int pte_read(pte_t pte) 415 { 416 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 417 } 418 419 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 420 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 421 pte_t *ptep) 422 { 423 if (__pte_write(*ptep)) 424 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 425 else if (unlikely(pte_savedwrite(*ptep))) 426 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 427 } 428 429 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 430 unsigned long addr, pte_t *ptep) 431 { 432 /* 433 * We should not find protnone for hugetlb, but this complete the 434 * interface. 435 */ 436 if (__pte_write(*ptep)) 437 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 438 else if (unlikely(pte_savedwrite(*ptep))) 439 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 440 } 441 442 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 443 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 444 unsigned long addr, pte_t *ptep) 445 { 446 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 447 return __pte(old); 448 } 449 450 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 451 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 452 unsigned long addr, 453 pte_t *ptep, int full) 454 { 455 if (full && radix_enabled()) { 456 /* 457 * Let's skip the DD1 style pte update here. We know that 458 * this is a full mm pte clear and hence can be sure there is 459 * no parallel set_pte. 460 */ 461 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 462 } 463 return ptep_get_and_clear(mm, addr, ptep); 464 } 465 466 467 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 468 pte_t * ptep) 469 { 470 pte_update(mm, addr, ptep, ~0UL, 0, 0); 471 } 472 473 static inline int pte_dirty(pte_t pte) 474 { 475 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 476 } 477 478 static inline int pte_young(pte_t pte) 479 { 480 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 481 } 482 483 static inline int pte_special(pte_t pte) 484 { 485 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 486 } 487 488 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 489 490 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 491 static inline bool pte_soft_dirty(pte_t pte) 492 { 493 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 494 } 495 496 static inline pte_t pte_mksoft_dirty(pte_t pte) 497 { 498 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); 499 } 500 501 static inline pte_t pte_clear_soft_dirty(pte_t pte) 502 { 503 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); 504 } 505 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 506 507 #ifdef CONFIG_NUMA_BALANCING 508 static inline int pte_protnone(pte_t pte) 509 { 510 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 511 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 512 } 513 514 #define pte_mk_savedwrite pte_mk_savedwrite 515 static inline pte_t pte_mk_savedwrite(pte_t pte) 516 { 517 /* 518 * Used by Autonuma subsystem to preserve the write bit 519 * while marking the pte PROT_NONE. Only allow this 520 * on PROT_NONE pte 521 */ 522 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 523 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 524 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED); 525 } 526 527 #define pte_clear_savedwrite pte_clear_savedwrite 528 static inline pte_t pte_clear_savedwrite(pte_t pte) 529 { 530 /* 531 * Used by KSM subsystem to make a protnone pte readonly. 532 */ 533 VM_BUG_ON(!pte_protnone(pte)); 534 return __pte(pte_val(pte) | _PAGE_PRIVILEGED); 535 } 536 #else 537 #define pte_clear_savedwrite pte_clear_savedwrite 538 static inline pte_t pte_clear_savedwrite(pte_t pte) 539 { 540 VM_WARN_ON(1); 541 return __pte(pte_val(pte) & ~_PAGE_WRITE); 542 } 543 #endif /* CONFIG_NUMA_BALANCING */ 544 545 static inline int pte_present(pte_t pte) 546 { 547 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 548 } 549 /* 550 * Conversion functions: convert a page and protection to a page entry, 551 * and a page entry and page directory to the page they refer to. 552 * 553 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 554 * long for now. 555 */ 556 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 557 { 558 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 559 pgprot_val(pgprot)); 560 } 561 562 static inline unsigned long pte_pfn(pte_t pte) 563 { 564 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 565 } 566 567 /* Generic modifiers for PTE bits */ 568 static inline pte_t pte_wrprotect(pte_t pte) 569 { 570 if (unlikely(pte_savedwrite(pte))) 571 return pte_clear_savedwrite(pte); 572 return __pte(pte_val(pte) & ~_PAGE_WRITE); 573 } 574 575 static inline pte_t pte_mkclean(pte_t pte) 576 { 577 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 578 } 579 580 static inline pte_t pte_mkold(pte_t pte) 581 { 582 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 583 } 584 585 static inline pte_t pte_mkwrite(pte_t pte) 586 { 587 /* 588 * write implies read, hence set both 589 */ 590 return __pte(pte_val(pte) | _PAGE_RW); 591 } 592 593 static inline pte_t pte_mkdirty(pte_t pte) 594 { 595 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 596 } 597 598 static inline pte_t pte_mkyoung(pte_t pte) 599 { 600 return __pte(pte_val(pte) | _PAGE_ACCESSED); 601 } 602 603 static inline pte_t pte_mkspecial(pte_t pte) 604 { 605 return __pte(pte_val(pte) | _PAGE_SPECIAL); 606 } 607 608 static inline pte_t pte_mkhuge(pte_t pte) 609 { 610 return pte; 611 } 612 613 static inline pte_t pte_mkdevmap(pte_t pte) 614 { 615 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP); 616 } 617 618 /* 619 * This is potentially called with a pmd as the argument, in which case it's not 620 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 621 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 622 * use in page directory entries (ie. non-ptes). 623 */ 624 static inline int pte_devmap(pte_t pte) 625 { 626 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 627 628 return (pte_raw(pte) & mask) == mask; 629 } 630 631 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 632 { 633 /* FIXME!! check whether this need to be a conditional */ 634 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 635 } 636 637 static inline bool pte_user(pte_t pte) 638 { 639 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 640 } 641 642 /* Encode and de-code a swap entry */ 643 #define MAX_SWAPFILES_CHECK() do { \ 644 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 645 /* \ 646 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 647 * We filter HPTEFLAGS on set_pte. \ 648 */ \ 649 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 650 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 651 } while (0) 652 /* 653 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 654 */ 655 #define SWP_TYPE_BITS 5 656 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 657 & ((1UL << SWP_TYPE_BITS) - 1)) 658 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 659 #define __swp_entry(type, offset) ((swp_entry_t) { \ 660 ((type) << _PAGE_BIT_SWAP_TYPE) \ 661 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 662 /* 663 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 664 * swap type and offset we get from swap and convert that to pte to find a 665 * matching pte in linux page table. 666 * Clear bits not found in swap entries here. 667 */ 668 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 669 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 670 671 #ifdef CONFIG_MEM_SOFT_DIRTY 672 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 673 #else 674 #define _PAGE_SWP_SOFT_DIRTY 0UL 675 #endif /* CONFIG_MEM_SOFT_DIRTY */ 676 677 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 678 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 679 { 680 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); 681 } 682 683 static inline bool pte_swp_soft_dirty(pte_t pte) 684 { 685 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 686 } 687 688 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 689 { 690 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); 691 } 692 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 693 694 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 695 { 696 /* 697 * This check for _PAGE_RWX and _PAGE_PRESENT bits 698 */ 699 if (access & ~ptev) 700 return false; 701 /* 702 * This check for access to privilege space 703 */ 704 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 705 return false; 706 707 return true; 708 } 709 /* 710 * Generic functions with hash/radix callbacks 711 */ 712 713 static inline void __ptep_set_access_flags(struct mm_struct *mm, 714 pte_t *ptep, pte_t entry, 715 unsigned long address) 716 { 717 if (radix_enabled()) 718 return radix__ptep_set_access_flags(mm, ptep, entry, address); 719 return hash__ptep_set_access_flags(ptep, entry); 720 } 721 722 #define __HAVE_ARCH_PTE_SAME 723 static inline int pte_same(pte_t pte_a, pte_t pte_b) 724 { 725 if (radix_enabled()) 726 return radix__pte_same(pte_a, pte_b); 727 return hash__pte_same(pte_a, pte_b); 728 } 729 730 static inline int pte_none(pte_t pte) 731 { 732 if (radix_enabled()) 733 return radix__pte_none(pte); 734 return hash__pte_none(pte); 735 } 736 737 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 738 pte_t *ptep, pte_t pte, int percpu) 739 { 740 if (radix_enabled()) 741 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 742 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 743 } 744 745 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 746 747 #define pgprot_noncached pgprot_noncached 748 static inline pgprot_t pgprot_noncached(pgprot_t prot) 749 { 750 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 751 _PAGE_NON_IDEMPOTENT); 752 } 753 754 #define pgprot_noncached_wc pgprot_noncached_wc 755 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 756 { 757 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 758 _PAGE_TOLERANT); 759 } 760 761 #define pgprot_cached pgprot_cached 762 static inline pgprot_t pgprot_cached(pgprot_t prot) 763 { 764 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 765 } 766 767 #define pgprot_writecombine pgprot_writecombine 768 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 769 { 770 return pgprot_noncached_wc(prot); 771 } 772 /* 773 * check a pte mapping have cache inhibited property 774 */ 775 static inline bool pte_ci(pte_t pte) 776 { 777 unsigned long pte_v = pte_val(pte); 778 779 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || 780 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) 781 return true; 782 return false; 783 } 784 785 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 786 { 787 *pmdp = __pmd(val); 788 } 789 790 static inline void pmd_clear(pmd_t *pmdp) 791 { 792 *pmdp = __pmd(0); 793 } 794 795 static inline int pmd_none(pmd_t pmd) 796 { 797 return !pmd_raw(pmd); 798 } 799 800 static inline int pmd_present(pmd_t pmd) 801 { 802 803 return !pmd_none(pmd); 804 } 805 806 static inline int pmd_bad(pmd_t pmd) 807 { 808 if (radix_enabled()) 809 return radix__pmd_bad(pmd); 810 return hash__pmd_bad(pmd); 811 } 812 813 static inline void pud_set(pud_t *pudp, unsigned long val) 814 { 815 *pudp = __pud(val); 816 } 817 818 static inline void pud_clear(pud_t *pudp) 819 { 820 *pudp = __pud(0); 821 } 822 823 static inline int pud_none(pud_t pud) 824 { 825 return !pud_raw(pud); 826 } 827 828 static inline int pud_present(pud_t pud) 829 { 830 return !pud_none(pud); 831 } 832 833 extern struct page *pud_page(pud_t pud); 834 extern struct page *pmd_page(pmd_t pmd); 835 static inline pte_t pud_pte(pud_t pud) 836 { 837 return __pte_raw(pud_raw(pud)); 838 } 839 840 static inline pud_t pte_pud(pte_t pte) 841 { 842 return __pud_raw(pte_raw(pte)); 843 } 844 #define pud_write(pud) pte_write(pud_pte(pud)) 845 846 static inline int pud_bad(pud_t pud) 847 { 848 if (radix_enabled()) 849 return radix__pud_bad(pud); 850 return hash__pud_bad(pud); 851 } 852 853 854 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 855 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 856 { 857 *pgdp = __pgd(val); 858 } 859 860 static inline void pgd_clear(pgd_t *pgdp) 861 { 862 *pgdp = __pgd(0); 863 } 864 865 static inline int pgd_none(pgd_t pgd) 866 { 867 return !pgd_raw(pgd); 868 } 869 870 static inline int pgd_present(pgd_t pgd) 871 { 872 return !pgd_none(pgd); 873 } 874 875 static inline pte_t pgd_pte(pgd_t pgd) 876 { 877 return __pte_raw(pgd_raw(pgd)); 878 } 879 880 static inline pgd_t pte_pgd(pte_t pte) 881 { 882 return __pgd_raw(pte_raw(pte)); 883 } 884 885 static inline int pgd_bad(pgd_t pgd) 886 { 887 if (radix_enabled()) 888 return radix__pgd_bad(pgd); 889 return hash__pgd_bad(pgd); 890 } 891 892 extern struct page *pgd_page(pgd_t pgd); 893 894 /* Pointers in the page table tree are physical addresses */ 895 #define __pgtable_ptr_val(ptr) __pa(ptr) 896 897 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 898 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 899 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 900 901 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 902 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 903 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 904 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 905 906 /* 907 * Find an entry in a page-table-directory. We combine the address region 908 * (the high order N bits) and the pgd portion of the address. 909 */ 910 911 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 912 913 #define pud_offset(pgdp, addr) \ 914 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 915 #define pmd_offset(pudp,addr) \ 916 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 917 #define pte_offset_kernel(dir,addr) \ 918 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 919 920 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 921 #define pte_unmap(pte) do { } while(0) 922 923 /* to find an entry in a kernel page-table-directory */ 924 /* This now only contains the vmalloc pages */ 925 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 926 927 #define pte_ERROR(e) \ 928 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 929 #define pmd_ERROR(e) \ 930 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 931 #define pud_ERROR(e) \ 932 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 933 #define pgd_ERROR(e) \ 934 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 935 936 static inline int map_kernel_page(unsigned long ea, unsigned long pa, 937 unsigned long flags) 938 { 939 if (radix_enabled()) { 940 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 941 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 942 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 943 #endif 944 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); 945 } 946 return hash__map_kernel_page(ea, pa, flags); 947 } 948 949 static inline int __meminit vmemmap_create_mapping(unsigned long start, 950 unsigned long page_size, 951 unsigned long phys) 952 { 953 if (radix_enabled()) 954 return radix__vmemmap_create_mapping(start, page_size, phys); 955 return hash__vmemmap_create_mapping(start, page_size, phys); 956 } 957 958 #ifdef CONFIG_MEMORY_HOTPLUG 959 static inline void vmemmap_remove_mapping(unsigned long start, 960 unsigned long page_size) 961 { 962 if (radix_enabled()) 963 return radix__vmemmap_remove_mapping(start, page_size); 964 return hash__vmemmap_remove_mapping(start, page_size); 965 } 966 #endif 967 struct page *realmode_pfn_to_page(unsigned long pfn); 968 969 static inline pte_t pmd_pte(pmd_t pmd) 970 { 971 return __pte_raw(pmd_raw(pmd)); 972 } 973 974 static inline pmd_t pte_pmd(pte_t pte) 975 { 976 return __pmd_raw(pte_raw(pte)); 977 } 978 979 static inline pte_t *pmdp_ptep(pmd_t *pmd) 980 { 981 return (pte_t *)pmd; 982 } 983 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 984 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 985 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 986 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 987 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 988 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 989 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 990 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 991 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 992 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 993 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 994 995 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 996 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 997 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 998 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 999 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1000 1001 #ifdef CONFIG_NUMA_BALANCING 1002 static inline int pmd_protnone(pmd_t pmd) 1003 { 1004 return pte_protnone(pmd_pte(pmd)); 1005 } 1006 #endif /* CONFIG_NUMA_BALANCING */ 1007 1008 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1009 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1010 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1011 1012 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1013 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1014 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1015 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1016 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1017 pmd_t *pmdp, pmd_t pmd); 1018 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1019 pmd_t *pmd); 1020 extern int hash__has_transparent_hugepage(void); 1021 static inline int has_transparent_hugepage(void) 1022 { 1023 if (radix_enabled()) 1024 return radix__has_transparent_hugepage(); 1025 return hash__has_transparent_hugepage(); 1026 } 1027 #define has_transparent_hugepage has_transparent_hugepage 1028 1029 static inline unsigned long 1030 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1031 unsigned long clr, unsigned long set) 1032 { 1033 if (radix_enabled()) 1034 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1035 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1036 } 1037 1038 static inline int pmd_large(pmd_t pmd) 1039 { 1040 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1041 } 1042 1043 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1044 { 1045 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1046 } 1047 /* 1048 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1049 * the below will work for radix too 1050 */ 1051 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1052 unsigned long addr, pmd_t *pmdp) 1053 { 1054 unsigned long old; 1055 1056 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1057 return 0; 1058 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1059 return ((old & _PAGE_ACCESSED) != 0); 1060 } 1061 1062 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1063 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1064 pmd_t *pmdp) 1065 { 1066 if (__pmd_write((*pmdp))) 1067 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1068 else if (unlikely(pmd_savedwrite(*pmdp))) 1069 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1070 } 1071 1072 static inline int pmd_trans_huge(pmd_t pmd) 1073 { 1074 if (radix_enabled()) 1075 return radix__pmd_trans_huge(pmd); 1076 return hash__pmd_trans_huge(pmd); 1077 } 1078 1079 #define __HAVE_ARCH_PMD_SAME 1080 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1081 { 1082 if (radix_enabled()) 1083 return radix__pmd_same(pmd_a, pmd_b); 1084 return hash__pmd_same(pmd_a, pmd_b); 1085 } 1086 1087 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1088 { 1089 if (radix_enabled()) 1090 return radix__pmd_mkhuge(pmd); 1091 return hash__pmd_mkhuge(pmd); 1092 } 1093 1094 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1095 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1096 unsigned long address, pmd_t *pmdp, 1097 pmd_t entry, int dirty); 1098 1099 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1100 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1101 unsigned long address, pmd_t *pmdp); 1102 1103 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1104 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1105 unsigned long addr, pmd_t *pmdp) 1106 { 1107 if (radix_enabled()) 1108 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1109 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1110 } 1111 1112 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1113 unsigned long address, pmd_t *pmdp) 1114 { 1115 if (radix_enabled()) 1116 return radix__pmdp_collapse_flush(vma, address, pmdp); 1117 return hash__pmdp_collapse_flush(vma, address, pmdp); 1118 } 1119 #define pmdp_collapse_flush pmdp_collapse_flush 1120 1121 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1122 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1123 pmd_t *pmdp, pgtable_t pgtable) 1124 { 1125 if (radix_enabled()) 1126 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1127 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1128 } 1129 1130 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1131 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1132 pmd_t *pmdp) 1133 { 1134 if (radix_enabled()) 1135 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1136 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1137 } 1138 1139 #define __HAVE_ARCH_PMDP_INVALIDATE 1140 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1141 pmd_t *pmdp); 1142 1143 #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE 1144 static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma, 1145 unsigned long address, pmd_t *pmdp) 1146 { 1147 if (radix_enabled()) 1148 return radix__pmdp_huge_split_prepare(vma, address, pmdp); 1149 return hash__pmdp_huge_split_prepare(vma, address, pmdp); 1150 } 1151 1152 #define pmd_move_must_withdraw pmd_move_must_withdraw 1153 struct spinlock; 1154 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1155 struct spinlock *old_pmd_ptl, 1156 struct vm_area_struct *vma) 1157 { 1158 if (radix_enabled()) 1159 return false; 1160 /* 1161 * Archs like ppc64 use pgtable to store per pmd 1162 * specific information. So when we switch the pmd, 1163 * we should also withdraw and deposit the pgtable 1164 */ 1165 return true; 1166 } 1167 1168 1169 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1170 static inline bool arch_needs_pgtable_deposit(void) 1171 { 1172 if (radix_enabled()) 1173 return false; 1174 return true; 1175 } 1176 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1177 1178 1179 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1180 { 1181 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1182 } 1183 1184 static inline int pmd_devmap(pmd_t pmd) 1185 { 1186 return pte_devmap(pmd_pte(pmd)); 1187 } 1188 1189 static inline int pud_devmap(pud_t pud) 1190 { 1191 return 0; 1192 } 1193 1194 static inline int pgd_devmap(pgd_t pgd) 1195 { 1196 return 0; 1197 } 1198 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1199 1200 static inline const int pud_pfn(pud_t pud) 1201 { 1202 /* 1203 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1204 * check so this should never be used. If it grows another user we 1205 * want to know about it. 1206 */ 1207 BUILD_BUG(); 1208 return 0; 1209 } 1210 1211 #endif /* __ASSEMBLY__ */ 1212 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1213