1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/5level-fixup.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x1000000000000000UL 36 #define _RPAGE_RSV2 0x0800000000000000UL 37 #define _RPAGE_RSV3 0x0400000000000000UL 38 #define _RPAGE_RSV4 0x0200000000000000UL 39 #define _RPAGE_RSV5 0x00040UL 40 41 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 43 /* 44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 46 * differentiate between two use a SW field when invalidating. 47 * 48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 49 * 50 * This is used only when _PAGE_PRESENT is cleared. 51 */ 52 #define _PAGE_INVALID _RPAGE_SW0 53 54 /* 55 * Top and bottom bits of RPN which can be used by hash 56 * translation mode, because we expect them to be zero 57 * otherwise. 58 */ 59 #define _RPAGE_RPN0 0x01000 60 #define _RPAGE_RPN1 0x02000 61 #define _RPAGE_RPN44 0x0100000000000000UL 62 #define _RPAGE_RPN43 0x0080000000000000UL 63 #define _RPAGE_RPN42 0x0040000000000000UL 64 #define _RPAGE_RPN41 0x0020000000000000UL 65 66 /* Max physical address bit as per radix table */ 67 #define _RPAGE_PA_MAX 57 68 69 /* 70 * Max physical address bit we will use for now. 71 * 72 * This is mostly a hardware limitation and for now Power9 has 73 * a 51 bit limit. 74 * 75 * This is different from the number of physical bit required to address 76 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 77 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 78 * number of sections we can support (SECTIONS_SHIFT). 79 * 80 * This is different from Radix page table limitation above and 81 * should always be less than that. The limit is done such that 82 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 83 * for hash linux page table specific bits. 84 * 85 * In order to be compatible with future hardware generations we keep 86 * some offsets and limit this for now to 53 87 */ 88 #define _PAGE_PA_MAX 53 89 90 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 91 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 92 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 93 94 /* 95 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 96 * Instead of fixing all of them, add an alternate define which 97 * maps CI pte mapping. 98 */ 99 #define _PAGE_NO_CACHE _PAGE_TOLERANT 100 /* 101 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 102 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 103 * and every thing below PAGE_SHIFT; 104 */ 105 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 106 /* 107 * set of bits not changed in pmd_modify. Even though we have hash specific bits 108 * in here, on radix we expect them to be zero. 109 */ 110 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 111 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 112 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 113 /* 114 * user access blocked by key 115 */ 116 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 117 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 118 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 119 _PAGE_RW | _PAGE_EXEC) 120 /* 121 * _PAGE_CHG_MASK masks of bits that are to be preserved across 122 * pgprot changes 123 */ 124 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 125 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 126 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 127 128 #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \ 129 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4) 130 /* 131 * We define 2 sets of base prot bits, one for basic pages (ie, 132 * cacheable kernel and user pages) and one for non cacheable 133 * pages. We always set _PAGE_COHERENT when SMP is enabled or 134 * the processor might need it for DMA coherency. 135 */ 136 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 137 #define _PAGE_BASE (_PAGE_BASE_NC) 138 139 /* Permission masks used to generate the __P and __S table, 140 * 141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 142 * 143 * Write permissions imply read permissions for now (we could make write-only 144 * pages on BookE but we don't bother for now). Execute permission control is 145 * possible on platforms that define _PAGE_EXEC 146 */ 147 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 148 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 149 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 150 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 151 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 152 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 153 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 154 155 /* Permission masks used for kernel mappings */ 156 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 157 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 158 _PAGE_TOLERANT) 159 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 160 _PAGE_NON_IDEMPOTENT) 161 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 162 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 163 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 164 165 /* 166 * Protection used for kernel text. We want the debuggers to be able to 167 * set breakpoints anywhere, so don't write protect the kernel text 168 * on platforms where such control is possible. 169 */ 170 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 171 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 172 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 173 #else 174 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 175 #endif 176 177 /* Make modules code happy. We don't set RO yet */ 178 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 179 #define PAGE_AGP (PAGE_KERNEL_NC) 180 181 #ifndef __ASSEMBLY__ 182 /* 183 * page table defines 184 */ 185 extern unsigned long __pte_index_size; 186 extern unsigned long __pmd_index_size; 187 extern unsigned long __pud_index_size; 188 extern unsigned long __pgd_index_size; 189 extern unsigned long __pud_cache_index; 190 #define PTE_INDEX_SIZE __pte_index_size 191 #define PMD_INDEX_SIZE __pmd_index_size 192 #define PUD_INDEX_SIZE __pud_index_size 193 #define PGD_INDEX_SIZE __pgd_index_size 194 /* pmd table use page table fragments */ 195 #define PMD_CACHE_INDEX 0 196 #define PUD_CACHE_INDEX __pud_cache_index 197 /* 198 * Because of use of pte fragments and THP, size of page table 199 * are not always derived out of index size above. 200 */ 201 extern unsigned long __pte_table_size; 202 extern unsigned long __pmd_table_size; 203 extern unsigned long __pud_table_size; 204 extern unsigned long __pgd_table_size; 205 #define PTE_TABLE_SIZE __pte_table_size 206 #define PMD_TABLE_SIZE __pmd_table_size 207 #define PUD_TABLE_SIZE __pud_table_size 208 #define PGD_TABLE_SIZE __pgd_table_size 209 210 extern unsigned long __pmd_val_bits; 211 extern unsigned long __pud_val_bits; 212 extern unsigned long __pgd_val_bits; 213 #define PMD_VAL_BITS __pmd_val_bits 214 #define PUD_VAL_BITS __pud_val_bits 215 #define PGD_VAL_BITS __pgd_val_bits 216 217 extern unsigned long __pte_frag_nr; 218 #define PTE_FRAG_NR __pte_frag_nr 219 extern unsigned long __pte_frag_size_shift; 220 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 221 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 222 223 extern unsigned long __pmd_frag_nr; 224 #define PMD_FRAG_NR __pmd_frag_nr 225 extern unsigned long __pmd_frag_size_shift; 226 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 227 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 228 229 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 230 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 231 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 232 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 233 234 /* PMD_SHIFT determines what a second-level page table entry can map */ 235 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 236 #define PMD_SIZE (1UL << PMD_SHIFT) 237 #define PMD_MASK (~(PMD_SIZE-1)) 238 239 /* PUD_SHIFT determines what a third-level page table entry can map */ 240 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 241 #define PUD_SIZE (1UL << PUD_SHIFT) 242 #define PUD_MASK (~(PUD_SIZE-1)) 243 244 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 245 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 246 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 247 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 248 249 /* Bits to mask out from a PMD to get to the PTE page */ 250 #define PMD_MASKED_BITS 0xc0000000000000ffUL 251 /* Bits to mask out from a PUD to get to the PMD page */ 252 #define PUD_MASKED_BITS 0xc0000000000000ffUL 253 /* Bits to mask out from a PGD to get to the PUD page */ 254 #define PGD_MASKED_BITS 0xc0000000000000ffUL 255 256 /* 257 * Used as an indicator for rcu callback functions 258 */ 259 enum pgtable_index { 260 PTE_INDEX = 0, 261 PMD_INDEX, 262 PUD_INDEX, 263 PGD_INDEX, 264 /* 265 * Below are used with 4k page size and hugetlb 266 */ 267 HTLB_16M_INDEX, 268 HTLB_16G_INDEX, 269 }; 270 271 extern unsigned long __vmalloc_start; 272 extern unsigned long __vmalloc_end; 273 #define VMALLOC_START __vmalloc_start 274 #define VMALLOC_END __vmalloc_end 275 276 static inline unsigned int ioremap_max_order(void) 277 { 278 if (radix_enabled()) 279 return PUD_SHIFT; 280 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 281 } 282 #define IOREMAP_MAX_ORDER ioremap_max_order() 283 284 extern unsigned long __kernel_virt_start; 285 extern unsigned long __kernel_io_start; 286 extern unsigned long __kernel_io_end; 287 #define KERN_VIRT_START __kernel_virt_start 288 #define KERN_IO_START __kernel_io_start 289 #define KERN_IO_END __kernel_io_end 290 291 extern struct page *vmemmap; 292 extern unsigned long ioremap_bot; 293 extern unsigned long pci_io_base; 294 #endif /* __ASSEMBLY__ */ 295 296 #include <asm/book3s/64/hash.h> 297 #include <asm/book3s/64/radix.h> 298 299 #ifdef CONFIG_PPC_64K_PAGES 300 #include <asm/book3s/64/pgtable-64k.h> 301 #else 302 #include <asm/book3s/64/pgtable-4k.h> 303 #endif 304 305 #include <asm/barrier.h> 306 /* 307 * IO space itself carved into the PIO region (ISA and PHB IO space) and 308 * the ioremap space 309 * 310 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 311 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 312 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 313 */ 314 #define FULL_IO_SIZE 0x80000000ul 315 #define ISA_IO_BASE (KERN_IO_START) 316 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 317 #define PHB_IO_BASE (ISA_IO_END) 318 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 319 #define IOREMAP_BASE (PHB_IO_END) 320 #define IOREMAP_END (KERN_IO_END) 321 322 /* Advertise special mapping type for AGP */ 323 #define HAVE_PAGE_AGP 324 325 #ifndef __ASSEMBLY__ 326 327 /* 328 * This is the default implementation of various PTE accessors, it's 329 * used in all cases except Book3S with 64K pages where we have a 330 * concept of sub-pages 331 */ 332 #ifndef __real_pte 333 334 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 335 #define __rpte_to_pte(r) ((r).pte) 336 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 337 338 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 339 do { \ 340 index = 0; \ 341 shift = mmu_psize_defs[psize].shift; \ 342 343 #define pte_iterate_hashed_end() } while(0) 344 345 /* 346 * We expect this to be called only for user addresses or kernel virtual 347 * addresses other than the linear mapping. 348 */ 349 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 350 351 #endif /* __real_pte */ 352 353 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 354 pte_t *ptep, unsigned long clr, 355 unsigned long set, int huge) 356 { 357 if (radix_enabled()) 358 return radix__pte_update(mm, addr, ptep, clr, set, huge); 359 return hash__pte_update(mm, addr, ptep, clr, set, huge); 360 } 361 /* 362 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 363 * We currently remove entries from the hashtable regardless of whether 364 * the entry was young or dirty. 365 * 366 * We should be more intelligent about this but for the moment we override 367 * these functions and force a tlb flush unconditionally 368 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 369 * function for both hash and radix. 370 */ 371 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 372 unsigned long addr, pte_t *ptep) 373 { 374 unsigned long old; 375 376 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 377 return 0; 378 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 379 return (old & _PAGE_ACCESSED) != 0; 380 } 381 382 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 383 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 384 ({ \ 385 int __r; \ 386 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 387 __r; \ 388 }) 389 390 static inline int __pte_write(pte_t pte) 391 { 392 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 393 } 394 395 #ifdef CONFIG_NUMA_BALANCING 396 #define pte_savedwrite pte_savedwrite 397 static inline bool pte_savedwrite(pte_t pte) 398 { 399 /* 400 * Saved write ptes are prot none ptes that doesn't have 401 * privileged bit sit. We mark prot none as one which has 402 * present and pviliged bit set and RWX cleared. To mark 403 * protnone which used to have _PAGE_WRITE set we clear 404 * the privileged bit. 405 */ 406 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 407 } 408 #else 409 #define pte_savedwrite pte_savedwrite 410 static inline bool pte_savedwrite(pte_t pte) 411 { 412 return false; 413 } 414 #endif 415 416 static inline int pte_write(pte_t pte) 417 { 418 return __pte_write(pte) || pte_savedwrite(pte); 419 } 420 421 static inline int pte_read(pte_t pte) 422 { 423 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 424 } 425 426 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 427 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 428 pte_t *ptep) 429 { 430 if (__pte_write(*ptep)) 431 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 432 else if (unlikely(pte_savedwrite(*ptep))) 433 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 434 } 435 436 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 437 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 438 unsigned long addr, pte_t *ptep) 439 { 440 /* 441 * We should not find protnone for hugetlb, but this complete the 442 * interface. 443 */ 444 if (__pte_write(*ptep)) 445 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 446 else if (unlikely(pte_savedwrite(*ptep))) 447 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 448 } 449 450 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 451 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 452 unsigned long addr, pte_t *ptep) 453 { 454 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 455 return __pte(old); 456 } 457 458 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 459 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 460 unsigned long addr, 461 pte_t *ptep, int full) 462 { 463 if (full && radix_enabled()) { 464 /* 465 * We know that this is a full mm pte clear and 466 * hence can be sure there is no parallel set_pte. 467 */ 468 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 469 } 470 return ptep_get_and_clear(mm, addr, ptep); 471 } 472 473 474 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 475 pte_t * ptep) 476 { 477 pte_update(mm, addr, ptep, ~0UL, 0, 0); 478 } 479 480 static inline int pte_dirty(pte_t pte) 481 { 482 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 483 } 484 485 static inline int pte_young(pte_t pte) 486 { 487 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 488 } 489 490 static inline int pte_special(pte_t pte) 491 { 492 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 493 } 494 495 static inline bool pte_exec(pte_t pte) 496 { 497 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 498 } 499 500 501 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 502 static inline bool pte_soft_dirty(pte_t pte) 503 { 504 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 505 } 506 507 static inline pte_t pte_mksoft_dirty(pte_t pte) 508 { 509 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 510 } 511 512 static inline pte_t pte_clear_soft_dirty(pte_t pte) 513 { 514 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 515 } 516 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 517 518 #ifdef CONFIG_NUMA_BALANCING 519 static inline int pte_protnone(pte_t pte) 520 { 521 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 522 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 523 } 524 525 #define pte_mk_savedwrite pte_mk_savedwrite 526 static inline pte_t pte_mk_savedwrite(pte_t pte) 527 { 528 /* 529 * Used by Autonuma subsystem to preserve the write bit 530 * while marking the pte PROT_NONE. Only allow this 531 * on PROT_NONE pte 532 */ 533 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 534 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 535 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 536 } 537 538 #define pte_clear_savedwrite pte_clear_savedwrite 539 static inline pte_t pte_clear_savedwrite(pte_t pte) 540 { 541 /* 542 * Used by KSM subsystem to make a protnone pte readonly. 543 */ 544 VM_BUG_ON(!pte_protnone(pte)); 545 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 546 } 547 #else 548 #define pte_clear_savedwrite pte_clear_savedwrite 549 static inline pte_t pte_clear_savedwrite(pte_t pte) 550 { 551 VM_WARN_ON(1); 552 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 553 } 554 #endif /* CONFIG_NUMA_BALANCING */ 555 556 static inline int pte_present(pte_t pte) 557 { 558 /* 559 * A pte is considerent present if _PAGE_PRESENT is set. 560 * We also need to consider the pte present which is marked 561 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 562 * if we find _PAGE_PRESENT cleared. 563 */ 564 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)); 565 } 566 567 static inline bool pte_hw_valid(pte_t pte) 568 { 569 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 570 } 571 572 #ifdef CONFIG_PPC_MEM_KEYS 573 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 574 #else 575 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 576 { 577 return true; 578 } 579 #endif /* CONFIG_PPC_MEM_KEYS */ 580 581 static inline bool pte_user(pte_t pte) 582 { 583 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 584 } 585 586 #define pte_access_permitted pte_access_permitted 587 static inline bool pte_access_permitted(pte_t pte, bool write) 588 { 589 /* 590 * _PAGE_READ is needed for any access and will be 591 * cleared for PROT_NONE 592 */ 593 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 594 return false; 595 596 if (write && !pte_write(pte)) 597 return false; 598 599 return arch_pte_access_permitted(pte_val(pte), write, 0); 600 } 601 602 /* 603 * Conversion functions: convert a page and protection to a page entry, 604 * and a page entry and page directory to the page they refer to. 605 * 606 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 607 * long for now. 608 */ 609 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 610 { 611 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 612 pgprot_val(pgprot)); 613 } 614 615 static inline unsigned long pte_pfn(pte_t pte) 616 { 617 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 618 } 619 620 /* Generic modifiers for PTE bits */ 621 static inline pte_t pte_wrprotect(pte_t pte) 622 { 623 if (unlikely(pte_savedwrite(pte))) 624 return pte_clear_savedwrite(pte); 625 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 626 } 627 628 static inline pte_t pte_exprotect(pte_t pte) 629 { 630 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 631 } 632 633 static inline pte_t pte_mkclean(pte_t pte) 634 { 635 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 636 } 637 638 static inline pte_t pte_mkold(pte_t pte) 639 { 640 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 641 } 642 643 static inline pte_t pte_mkexec(pte_t pte) 644 { 645 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 646 } 647 648 static inline pte_t pte_mkpte(pte_t pte) 649 { 650 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 651 } 652 653 static inline pte_t pte_mkwrite(pte_t pte) 654 { 655 /* 656 * write implies read, hence set both 657 */ 658 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 659 } 660 661 static inline pte_t pte_mkdirty(pte_t pte) 662 { 663 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 664 } 665 666 static inline pte_t pte_mkyoung(pte_t pte) 667 { 668 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 669 } 670 671 static inline pte_t pte_mkspecial(pte_t pte) 672 { 673 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 674 } 675 676 static inline pte_t pte_mkhuge(pte_t pte) 677 { 678 return pte; 679 } 680 681 static inline pte_t pte_mkdevmap(pte_t pte) 682 { 683 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 684 } 685 686 static inline pte_t pte_mkprivileged(pte_t pte) 687 { 688 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 689 } 690 691 static inline pte_t pte_mkuser(pte_t pte) 692 { 693 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 694 } 695 696 /* 697 * This is potentially called with a pmd as the argument, in which case it's not 698 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 699 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 700 * use in page directory entries (ie. non-ptes). 701 */ 702 static inline int pte_devmap(pte_t pte) 703 { 704 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 705 706 return (pte_raw(pte) & mask) == mask; 707 } 708 709 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 710 { 711 /* FIXME!! check whether this need to be a conditional */ 712 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 713 cpu_to_be64(pgprot_val(newprot))); 714 } 715 716 /* Encode and de-code a swap entry */ 717 #define MAX_SWAPFILES_CHECK() do { \ 718 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 719 /* \ 720 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 721 * We filter HPTEFLAGS on set_pte. \ 722 */ \ 723 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 724 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 725 } while (0) 726 727 #define SWP_TYPE_BITS 5 728 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 729 & ((1UL << SWP_TYPE_BITS) - 1)) 730 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 731 #define __swp_entry(type, offset) ((swp_entry_t) { \ 732 ((type) << _PAGE_BIT_SWAP_TYPE) \ 733 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 734 /* 735 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 736 * swap type and offset we get from swap and convert that to pte to find a 737 * matching pte in linux page table. 738 * Clear bits not found in swap entries here. 739 */ 740 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 741 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 742 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 743 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 744 745 #ifdef CONFIG_MEM_SOFT_DIRTY 746 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 747 #else 748 #define _PAGE_SWP_SOFT_DIRTY 0UL 749 #endif /* CONFIG_MEM_SOFT_DIRTY */ 750 751 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 752 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 753 { 754 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 755 } 756 757 static inline bool pte_swp_soft_dirty(pte_t pte) 758 { 759 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 760 } 761 762 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 763 { 764 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 765 } 766 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 767 768 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 769 { 770 /* 771 * This check for _PAGE_RWX and _PAGE_PRESENT bits 772 */ 773 if (access & ~ptev) 774 return false; 775 /* 776 * This check for access to privilege space 777 */ 778 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 779 return false; 780 781 return true; 782 } 783 /* 784 * Generic functions with hash/radix callbacks 785 */ 786 787 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 788 pte_t *ptep, pte_t entry, 789 unsigned long address, 790 int psize) 791 { 792 if (radix_enabled()) 793 return radix__ptep_set_access_flags(vma, ptep, entry, 794 address, psize); 795 return hash__ptep_set_access_flags(ptep, entry); 796 } 797 798 #define __HAVE_ARCH_PTE_SAME 799 static inline int pte_same(pte_t pte_a, pte_t pte_b) 800 { 801 if (radix_enabled()) 802 return radix__pte_same(pte_a, pte_b); 803 return hash__pte_same(pte_a, pte_b); 804 } 805 806 static inline int pte_none(pte_t pte) 807 { 808 if (radix_enabled()) 809 return radix__pte_none(pte); 810 return hash__pte_none(pte); 811 } 812 813 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 814 pte_t *ptep, pte_t pte, int percpu) 815 { 816 if (radix_enabled()) 817 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 818 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 819 } 820 821 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 822 823 #define pgprot_noncached pgprot_noncached 824 static inline pgprot_t pgprot_noncached(pgprot_t prot) 825 { 826 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 827 _PAGE_NON_IDEMPOTENT); 828 } 829 830 #define pgprot_noncached_wc pgprot_noncached_wc 831 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 832 { 833 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 834 _PAGE_TOLERANT); 835 } 836 837 #define pgprot_cached pgprot_cached 838 static inline pgprot_t pgprot_cached(pgprot_t prot) 839 { 840 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 841 } 842 843 #define pgprot_writecombine pgprot_writecombine 844 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 845 { 846 return pgprot_noncached_wc(prot); 847 } 848 /* 849 * check a pte mapping have cache inhibited property 850 */ 851 static inline bool pte_ci(pte_t pte) 852 { 853 __be64 pte_v = pte_raw(pte); 854 855 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 856 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 857 return true; 858 return false; 859 } 860 861 static inline void pmd_clear(pmd_t *pmdp) 862 { 863 *pmdp = __pmd(0); 864 } 865 866 static inline int pmd_none(pmd_t pmd) 867 { 868 return !pmd_raw(pmd); 869 } 870 871 static inline int pmd_present(pmd_t pmd) 872 { 873 /* 874 * A pmd is considerent present if _PAGE_PRESENT is set. 875 * We also need to consider the pmd present which is marked 876 * invalid during a split. Hence we look for _PAGE_INVALID 877 * if we find _PAGE_PRESENT cleared. 878 */ 879 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 880 return true; 881 882 return false; 883 } 884 885 static inline int pmd_is_serializing(pmd_t pmd) 886 { 887 /* 888 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 889 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 890 * 891 * This condition may also occur when flushing a pmd while flushing 892 * it (see ptep_modify_prot_start), so callers must ensure this 893 * case is fine as well. 894 */ 895 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 896 cpu_to_be64(_PAGE_INVALID)) 897 return true; 898 899 return false; 900 } 901 902 static inline int pmd_bad(pmd_t pmd) 903 { 904 if (radix_enabled()) 905 return radix__pmd_bad(pmd); 906 return hash__pmd_bad(pmd); 907 } 908 909 static inline void pud_clear(pud_t *pudp) 910 { 911 *pudp = __pud(0); 912 } 913 914 static inline int pud_none(pud_t pud) 915 { 916 return !pud_raw(pud); 917 } 918 919 static inline int pud_present(pud_t pud) 920 { 921 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 922 } 923 924 extern struct page *pud_page(pud_t pud); 925 extern struct page *pmd_page(pmd_t pmd); 926 static inline pte_t pud_pte(pud_t pud) 927 { 928 return __pte_raw(pud_raw(pud)); 929 } 930 931 static inline pud_t pte_pud(pte_t pte) 932 { 933 return __pud_raw(pte_raw(pte)); 934 } 935 #define pud_write(pud) pte_write(pud_pte(pud)) 936 937 static inline int pud_bad(pud_t pud) 938 { 939 if (radix_enabled()) 940 return radix__pud_bad(pud); 941 return hash__pud_bad(pud); 942 } 943 944 #define pud_access_permitted pud_access_permitted 945 static inline bool pud_access_permitted(pud_t pud, bool write) 946 { 947 return pte_access_permitted(pud_pte(pud), write); 948 } 949 950 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 951 952 static inline void pgd_clear(pgd_t *pgdp) 953 { 954 *pgdp = __pgd(0); 955 } 956 957 static inline int pgd_none(pgd_t pgd) 958 { 959 return !pgd_raw(pgd); 960 } 961 962 static inline int pgd_present(pgd_t pgd) 963 { 964 return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT)); 965 } 966 967 static inline pte_t pgd_pte(pgd_t pgd) 968 { 969 return __pte_raw(pgd_raw(pgd)); 970 } 971 972 static inline pgd_t pte_pgd(pte_t pte) 973 { 974 return __pgd_raw(pte_raw(pte)); 975 } 976 977 static inline int pgd_bad(pgd_t pgd) 978 { 979 if (radix_enabled()) 980 return radix__pgd_bad(pgd); 981 return hash__pgd_bad(pgd); 982 } 983 984 #define pgd_access_permitted pgd_access_permitted 985 static inline bool pgd_access_permitted(pgd_t pgd, bool write) 986 { 987 return pte_access_permitted(pgd_pte(pgd), write); 988 } 989 990 extern struct page *pgd_page(pgd_t pgd); 991 992 /* Pointers in the page table tree are physical addresses */ 993 #define __pgtable_ptr_val(ptr) __pa(ptr) 994 995 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 996 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 997 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 998 999 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 1000 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 1001 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 1002 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 1003 1004 /* 1005 * Find an entry in a page-table-directory. We combine the address region 1006 * (the high order N bits) and the pgd portion of the address. 1007 */ 1008 1009 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1010 1011 #define pud_offset(pgdp, addr) \ 1012 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 1013 #define pmd_offset(pudp,addr) \ 1014 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 1015 #define pte_offset_kernel(dir,addr) \ 1016 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 1017 1018 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 1019 1020 static inline void pte_unmap(pte_t *pte) { } 1021 1022 /* to find an entry in a kernel page-table-directory */ 1023 /* This now only contains the vmalloc pages */ 1024 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1025 1026 #define pte_ERROR(e) \ 1027 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1028 #define pmd_ERROR(e) \ 1029 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1030 #define pud_ERROR(e) \ 1031 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1032 #define pgd_ERROR(e) \ 1033 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1034 1035 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1036 { 1037 if (radix_enabled()) { 1038 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1039 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1040 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1041 #endif 1042 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1043 } 1044 return hash__map_kernel_page(ea, pa, prot); 1045 } 1046 1047 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1048 unsigned long page_size, 1049 unsigned long phys) 1050 { 1051 if (radix_enabled()) 1052 return radix__vmemmap_create_mapping(start, page_size, phys); 1053 return hash__vmemmap_create_mapping(start, page_size, phys); 1054 } 1055 1056 #ifdef CONFIG_MEMORY_HOTPLUG 1057 static inline void vmemmap_remove_mapping(unsigned long start, 1058 unsigned long page_size) 1059 { 1060 if (radix_enabled()) 1061 return radix__vmemmap_remove_mapping(start, page_size); 1062 return hash__vmemmap_remove_mapping(start, page_size); 1063 } 1064 #endif 1065 1066 static inline pte_t pmd_pte(pmd_t pmd) 1067 { 1068 return __pte_raw(pmd_raw(pmd)); 1069 } 1070 1071 static inline pmd_t pte_pmd(pte_t pte) 1072 { 1073 return __pmd_raw(pte_raw(pte)); 1074 } 1075 1076 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1077 { 1078 return (pte_t *)pmd; 1079 } 1080 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1081 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1082 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1083 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1084 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1085 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1086 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1087 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1088 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1089 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1090 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1091 1092 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1093 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1094 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1095 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1096 1097 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1098 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1099 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1100 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1101 #endif 1102 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1103 1104 #ifdef CONFIG_NUMA_BALANCING 1105 static inline int pmd_protnone(pmd_t pmd) 1106 { 1107 return pte_protnone(pmd_pte(pmd)); 1108 } 1109 #endif /* CONFIG_NUMA_BALANCING */ 1110 1111 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1112 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1113 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1114 1115 #define pmd_access_permitted pmd_access_permitted 1116 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1117 { 1118 /* 1119 * pmdp_invalidate sets this combination (which is not caught by 1120 * !pte_present() check in pte_access_permitted), to prevent 1121 * lock-free lookups, as part of the serialize_against_pte_lookup() 1122 * synchronisation. 1123 * 1124 * This also catches the case where the PTE's hardware PRESENT bit is 1125 * cleared while TLB is flushed, which is suboptimal but should not 1126 * be frequent. 1127 */ 1128 if (pmd_is_serializing(pmd)) 1129 return false; 1130 1131 return pte_access_permitted(pmd_pte(pmd), write); 1132 } 1133 1134 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1135 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1136 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1137 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1138 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1139 pmd_t *pmdp, pmd_t pmd); 1140 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1141 pmd_t *pmd); 1142 extern int hash__has_transparent_hugepage(void); 1143 static inline int has_transparent_hugepage(void) 1144 { 1145 if (radix_enabled()) 1146 return radix__has_transparent_hugepage(); 1147 return hash__has_transparent_hugepage(); 1148 } 1149 #define has_transparent_hugepage has_transparent_hugepage 1150 1151 static inline unsigned long 1152 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1153 unsigned long clr, unsigned long set) 1154 { 1155 if (radix_enabled()) 1156 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1157 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1158 } 1159 1160 /* 1161 * returns true for pmd migration entries, THP, devmap, hugetlb 1162 * But compile time dependent on THP config 1163 */ 1164 static inline int pmd_large(pmd_t pmd) 1165 { 1166 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1167 } 1168 1169 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1170 { 1171 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1172 } 1173 /* 1174 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1175 * the below will work for radix too 1176 */ 1177 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1178 unsigned long addr, pmd_t *pmdp) 1179 { 1180 unsigned long old; 1181 1182 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1183 return 0; 1184 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1185 return ((old & _PAGE_ACCESSED) != 0); 1186 } 1187 1188 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1189 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1190 pmd_t *pmdp) 1191 { 1192 if (__pmd_write((*pmdp))) 1193 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1194 else if (unlikely(pmd_savedwrite(*pmdp))) 1195 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1196 } 1197 1198 /* 1199 * Only returns true for a THP. False for pmd migration entry. 1200 * We also need to return true when we come across a pte that 1201 * in between a thp split. While splitting THP, we mark the pmd 1202 * invalid (pmdp_invalidate()) before we set it with pte page 1203 * address. A pmd_trans_huge() check against a pmd entry during that time 1204 * should return true. 1205 * We should not call this on a hugetlb entry. We should check for HugeTLB 1206 * entry using vma->vm_flags 1207 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1208 */ 1209 static inline int pmd_trans_huge(pmd_t pmd) 1210 { 1211 if (!pmd_present(pmd)) 1212 return false; 1213 1214 if (radix_enabled()) 1215 return radix__pmd_trans_huge(pmd); 1216 return hash__pmd_trans_huge(pmd); 1217 } 1218 1219 #define __HAVE_ARCH_PMD_SAME 1220 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1221 { 1222 if (radix_enabled()) 1223 return radix__pmd_same(pmd_a, pmd_b); 1224 return hash__pmd_same(pmd_a, pmd_b); 1225 } 1226 1227 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1228 { 1229 if (radix_enabled()) 1230 return radix__pmd_mkhuge(pmd); 1231 return hash__pmd_mkhuge(pmd); 1232 } 1233 1234 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1235 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1236 unsigned long address, pmd_t *pmdp, 1237 pmd_t entry, int dirty); 1238 1239 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1240 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1241 unsigned long address, pmd_t *pmdp); 1242 1243 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1244 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1245 unsigned long addr, pmd_t *pmdp) 1246 { 1247 if (radix_enabled()) 1248 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1249 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1250 } 1251 1252 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1253 unsigned long address, pmd_t *pmdp) 1254 { 1255 if (radix_enabled()) 1256 return radix__pmdp_collapse_flush(vma, address, pmdp); 1257 return hash__pmdp_collapse_flush(vma, address, pmdp); 1258 } 1259 #define pmdp_collapse_flush pmdp_collapse_flush 1260 1261 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1262 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1263 pmd_t *pmdp, pgtable_t pgtable) 1264 { 1265 if (radix_enabled()) 1266 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1267 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1268 } 1269 1270 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1271 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1272 pmd_t *pmdp) 1273 { 1274 if (radix_enabled()) 1275 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1276 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1277 } 1278 1279 #define __HAVE_ARCH_PMDP_INVALIDATE 1280 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1281 pmd_t *pmdp); 1282 1283 #define pmd_move_must_withdraw pmd_move_must_withdraw 1284 struct spinlock; 1285 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1286 struct spinlock *old_pmd_ptl, 1287 struct vm_area_struct *vma); 1288 /* 1289 * Hash translation mode use the deposited table to store hash pte 1290 * slot information. 1291 */ 1292 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1293 static inline bool arch_needs_pgtable_deposit(void) 1294 { 1295 if (radix_enabled()) 1296 return false; 1297 return true; 1298 } 1299 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1300 1301 1302 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1303 { 1304 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1305 } 1306 1307 static inline int pmd_devmap(pmd_t pmd) 1308 { 1309 return pte_devmap(pmd_pte(pmd)); 1310 } 1311 1312 static inline int pud_devmap(pud_t pud) 1313 { 1314 return 0; 1315 } 1316 1317 static inline int pgd_devmap(pgd_t pgd) 1318 { 1319 return 0; 1320 } 1321 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1322 1323 static inline int pud_pfn(pud_t pud) 1324 { 1325 /* 1326 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1327 * check so this should never be used. If it grows another user we 1328 * want to know about it. 1329 */ 1330 BUILD_BUG(); 1331 return 0; 1332 } 1333 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1334 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1335 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1336 pte_t *, pte_t, pte_t); 1337 1338 /* 1339 * Returns true for a R -> RW upgrade of pte 1340 */ 1341 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1342 { 1343 if (!(old_val & _PAGE_READ)) 1344 return false; 1345 1346 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1347 return true; 1348 1349 return false; 1350 } 1351 1352 /* 1353 * Like pmd_huge() and pmd_large(), but works regardless of config options 1354 */ 1355 #define pmd_is_leaf pmd_is_leaf 1356 static inline bool pmd_is_leaf(pmd_t pmd) 1357 { 1358 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1359 } 1360 1361 #define pud_is_leaf pud_is_leaf 1362 static inline bool pud_is_leaf(pud_t pud) 1363 { 1364 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1365 } 1366 1367 #define pgd_is_leaf pgd_is_leaf 1368 static inline bool pgd_is_leaf(pgd_t pgd) 1369 { 1370 return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PTE)); 1371 } 1372 1373 #endif /* __ASSEMBLY__ */ 1374 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1375