1 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 2 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 4 #include <asm-generic/5level-fixup.h> 5 6 #ifndef __ASSEMBLY__ 7 #include <linux/mmdebug.h> 8 #include <linux/bug.h> 9 #endif 10 11 /* 12 * Common bits between hash and Radix page table 13 */ 14 #define _PAGE_BIT_SWAP_TYPE 0 15 16 #define _PAGE_RO 0 17 #define _PAGE_SHARED 0 18 19 #define _PAGE_EXEC 0x00001 /* execute permission */ 20 #define _PAGE_WRITE 0x00002 /* write access allowed */ 21 #define _PAGE_READ 0x00004 /* read access allowed */ 22 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 23 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 24 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 25 #define _PAGE_SAO 0x00010 /* Strong access order */ 26 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 27 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 28 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 29 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 30 /* 31 * Software bits 32 */ 33 #define _RPAGE_SW0 0x2000000000000000UL 34 #define _RPAGE_SW1 0x00800 35 #define _RPAGE_SW2 0x00400 36 #define _RPAGE_SW3 0x00200 37 #define _RPAGE_RSV1 0x1000000000000000UL 38 #define _RPAGE_RSV2 0x0800000000000000UL 39 #define _RPAGE_RSV3 0x0400000000000000UL 40 #define _RPAGE_RSV4 0x0200000000000000UL 41 42 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 43 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 44 45 /* 46 * Top and bottom bits of RPN which can be used by hash 47 * translation mode, because we expect them to be zero 48 * otherwise. 49 */ 50 #define _RPAGE_RPN0 0x01000 51 #define _RPAGE_RPN1 0x02000 52 #define _RPAGE_RPN44 0x0100000000000000UL 53 #define _RPAGE_RPN43 0x0080000000000000UL 54 #define _RPAGE_RPN42 0x0040000000000000UL 55 #define _RPAGE_RPN41 0x0020000000000000UL 56 57 /* Max physical address bit as per radix table */ 58 #define _RPAGE_PA_MAX 57 59 60 /* 61 * Max physical address bit we will use for now. 62 * 63 * This is mostly a hardware limitation and for now Power9 has 64 * a 51 bit limit. 65 * 66 * This is different from the number of physical bit required to address 67 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 68 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 69 * number of sections we can support (SECTIONS_SHIFT). 70 * 71 * This is different from Radix page table limitation above and 72 * should always be less than that. The limit is done such that 73 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 74 * for hash linux page table specific bits. 75 * 76 * In order to be compatible with future hardware generations we keep 77 * some offsets and limit this for now to 53 78 */ 79 #define _PAGE_PA_MAX 53 80 81 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 82 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 83 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 84 #define __HAVE_ARCH_PTE_DEVMAP 85 86 /* 87 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 88 * Instead of fixing all of them, add an alternate define which 89 * maps CI pte mapping. 90 */ 91 #define _PAGE_NO_CACHE _PAGE_TOLERANT 92 /* 93 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 94 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 95 * and every thing below PAGE_SHIFT; 96 */ 97 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 98 /* 99 * set of bits not changed in pmd_modify. Even though we have hash specific bits 100 * in here, on radix we expect them to be zero. 101 */ 102 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 103 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 104 _PAGE_SOFT_DIRTY) 105 /* 106 * user access blocked by key 107 */ 108 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 109 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 110 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 111 _PAGE_RW | _PAGE_EXEC) 112 /* 113 * No page size encoding in the linux PTE 114 */ 115 #define _PAGE_PSIZE 0 116 /* 117 * _PAGE_CHG_MASK masks of bits that are to be preserved across 118 * pgprot changes 119 */ 120 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 121 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 122 _PAGE_SOFT_DIRTY) 123 /* 124 * Mask of bits returned by pte_pgprot() 125 */ 126 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ 127 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ 128 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ 129 _PAGE_SOFT_DIRTY) 130 /* 131 * We define 2 sets of base prot bits, one for basic pages (ie, 132 * cacheable kernel and user pages) and one for non cacheable 133 * pages. We always set _PAGE_COHERENT when SMP is enabled or 134 * the processor might need it for DMA coherency. 135 */ 136 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 137 #define _PAGE_BASE (_PAGE_BASE_NC) 138 139 /* Permission masks used to generate the __P and __S table, 140 * 141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 142 * 143 * Write permissions imply read permissions for now (we could make write-only 144 * pages on BookE but we don't bother for now). Execute permission control is 145 * possible on platforms that define _PAGE_EXEC 146 * 147 * Note due to the way vm flags are laid out, the bits are XWR 148 */ 149 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 150 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 151 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 152 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 153 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 154 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 155 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 156 157 #define __P000 PAGE_NONE 158 #define __P001 PAGE_READONLY 159 #define __P010 PAGE_COPY 160 #define __P011 PAGE_COPY 161 #define __P100 PAGE_READONLY_X 162 #define __P101 PAGE_READONLY_X 163 #define __P110 PAGE_COPY_X 164 #define __P111 PAGE_COPY_X 165 166 #define __S000 PAGE_NONE 167 #define __S001 PAGE_READONLY 168 #define __S010 PAGE_SHARED 169 #define __S011 PAGE_SHARED 170 #define __S100 PAGE_READONLY_X 171 #define __S101 PAGE_READONLY_X 172 #define __S110 PAGE_SHARED_X 173 #define __S111 PAGE_SHARED_X 174 175 /* Permission masks used for kernel mappings */ 176 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 177 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 178 _PAGE_TOLERANT) 179 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 180 _PAGE_NON_IDEMPOTENT) 181 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 182 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 183 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 184 185 /* 186 * Protection used for kernel text. We want the debuggers to be able to 187 * set breakpoints anywhere, so don't write protect the kernel text 188 * on platforms where such control is possible. 189 */ 190 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 191 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 192 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 193 #else 194 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 195 #endif 196 197 /* Make modules code happy. We don't set RO yet */ 198 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 199 #define PAGE_AGP (PAGE_KERNEL_NC) 200 201 #ifndef __ASSEMBLY__ 202 /* 203 * page table defines 204 */ 205 extern unsigned long __pte_index_size; 206 extern unsigned long __pmd_index_size; 207 extern unsigned long __pud_index_size; 208 extern unsigned long __pgd_index_size; 209 extern unsigned long __pmd_cache_index; 210 #define PTE_INDEX_SIZE __pte_index_size 211 #define PMD_INDEX_SIZE __pmd_index_size 212 #define PUD_INDEX_SIZE __pud_index_size 213 #define PGD_INDEX_SIZE __pgd_index_size 214 #define PMD_CACHE_INDEX __pmd_cache_index 215 /* 216 * Because of use of pte fragments and THP, size of page table 217 * are not always derived out of index size above. 218 */ 219 extern unsigned long __pte_table_size; 220 extern unsigned long __pmd_table_size; 221 extern unsigned long __pud_table_size; 222 extern unsigned long __pgd_table_size; 223 #define PTE_TABLE_SIZE __pte_table_size 224 #define PMD_TABLE_SIZE __pmd_table_size 225 #define PUD_TABLE_SIZE __pud_table_size 226 #define PGD_TABLE_SIZE __pgd_table_size 227 228 extern unsigned long __pmd_val_bits; 229 extern unsigned long __pud_val_bits; 230 extern unsigned long __pgd_val_bits; 231 #define PMD_VAL_BITS __pmd_val_bits 232 #define PUD_VAL_BITS __pud_val_bits 233 #define PGD_VAL_BITS __pgd_val_bits 234 235 extern unsigned long __pte_frag_nr; 236 #define PTE_FRAG_NR __pte_frag_nr 237 extern unsigned long __pte_frag_size_shift; 238 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 239 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 240 241 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 242 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 243 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 244 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 245 246 /* PMD_SHIFT determines what a second-level page table entry can map */ 247 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 248 #define PMD_SIZE (1UL << PMD_SHIFT) 249 #define PMD_MASK (~(PMD_SIZE-1)) 250 251 /* PUD_SHIFT determines what a third-level page table entry can map */ 252 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 253 #define PUD_SIZE (1UL << PUD_SHIFT) 254 #define PUD_MASK (~(PUD_SIZE-1)) 255 256 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 257 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 258 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 259 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 260 261 /* Bits to mask out from a PMD to get to the PTE page */ 262 #define PMD_MASKED_BITS 0xc0000000000000ffUL 263 /* Bits to mask out from a PUD to get to the PMD page */ 264 #define PUD_MASKED_BITS 0xc0000000000000ffUL 265 /* Bits to mask out from a PGD to get to the PUD page */ 266 #define PGD_MASKED_BITS 0xc0000000000000ffUL 267 268 extern unsigned long __vmalloc_start; 269 extern unsigned long __vmalloc_end; 270 #define VMALLOC_START __vmalloc_start 271 #define VMALLOC_END __vmalloc_end 272 273 extern unsigned long __kernel_virt_start; 274 extern unsigned long __kernel_virt_size; 275 #define KERN_VIRT_START __kernel_virt_start 276 #define KERN_VIRT_SIZE __kernel_virt_size 277 extern struct page *vmemmap; 278 extern unsigned long ioremap_bot; 279 extern unsigned long pci_io_base; 280 #endif /* __ASSEMBLY__ */ 281 282 #include <asm/book3s/64/hash.h> 283 #include <asm/book3s/64/radix.h> 284 285 #ifdef CONFIG_PPC_64K_PAGES 286 #include <asm/book3s/64/pgtable-64k.h> 287 #else 288 #include <asm/book3s/64/pgtable-4k.h> 289 #endif 290 291 #include <asm/barrier.h> 292 /* 293 * The second half of the kernel virtual space is used for IO mappings, 294 * it's itself carved into the PIO region (ISA and PHB IO space) and 295 * the ioremap space 296 * 297 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 298 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 299 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 300 */ 301 #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1)) 302 #define FULL_IO_SIZE 0x80000000ul 303 #define ISA_IO_BASE (KERN_IO_START) 304 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 305 #define PHB_IO_BASE (ISA_IO_END) 306 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 307 #define IOREMAP_BASE (PHB_IO_END) 308 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 309 310 /* Advertise special mapping type for AGP */ 311 #define HAVE_PAGE_AGP 312 313 /* Advertise support for _PAGE_SPECIAL */ 314 #define __HAVE_ARCH_PTE_SPECIAL 315 316 #ifndef __ASSEMBLY__ 317 318 /* 319 * This is the default implementation of various PTE accessors, it's 320 * used in all cases except Book3S with 64K pages where we have a 321 * concept of sub-pages 322 */ 323 #ifndef __real_pte 324 325 #define __real_pte(e,p) ((real_pte_t){(e)}) 326 #define __rpte_to_pte(r) ((r).pte) 327 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 328 329 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 330 do { \ 331 index = 0; \ 332 shift = mmu_psize_defs[psize].shift; \ 333 334 #define pte_iterate_hashed_end() } while(0) 335 336 /* 337 * We expect this to be called only for user addresses or kernel virtual 338 * addresses other than the linear mapping. 339 */ 340 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 341 342 #endif /* __real_pte */ 343 344 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 345 pte_t *ptep, unsigned long clr, 346 unsigned long set, int huge) 347 { 348 if (radix_enabled()) 349 return radix__pte_update(mm, addr, ptep, clr, set, huge); 350 return hash__pte_update(mm, addr, ptep, clr, set, huge); 351 } 352 /* 353 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 354 * We currently remove entries from the hashtable regardless of whether 355 * the entry was young or dirty. 356 * 357 * We should be more intelligent about this but for the moment we override 358 * these functions and force a tlb flush unconditionally 359 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 360 * function for both hash and radix. 361 */ 362 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 363 unsigned long addr, pte_t *ptep) 364 { 365 unsigned long old; 366 367 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 368 return 0; 369 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 370 return (old & _PAGE_ACCESSED) != 0; 371 } 372 373 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 374 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 375 ({ \ 376 int __r; \ 377 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 378 __r; \ 379 }) 380 381 static inline int __pte_write(pte_t pte) 382 { 383 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 384 } 385 386 #ifdef CONFIG_NUMA_BALANCING 387 #define pte_savedwrite pte_savedwrite 388 static inline bool pte_savedwrite(pte_t pte) 389 { 390 /* 391 * Saved write ptes are prot none ptes that doesn't have 392 * privileged bit sit. We mark prot none as one which has 393 * present and pviliged bit set and RWX cleared. To mark 394 * protnone which used to have _PAGE_WRITE set we clear 395 * the privileged bit. 396 */ 397 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 398 } 399 #else 400 #define pte_savedwrite pte_savedwrite 401 static inline bool pte_savedwrite(pte_t pte) 402 { 403 return false; 404 } 405 #endif 406 407 static inline int pte_write(pte_t pte) 408 { 409 return __pte_write(pte) || pte_savedwrite(pte); 410 } 411 412 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 413 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 414 pte_t *ptep) 415 { 416 if (__pte_write(*ptep)) 417 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 418 else if (unlikely(pte_savedwrite(*ptep))) 419 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 420 } 421 422 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 423 unsigned long addr, pte_t *ptep) 424 { 425 /* 426 * We should not find protnone for hugetlb, but this complete the 427 * interface. 428 */ 429 if (__pte_write(*ptep)) 430 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 431 else if (unlikely(pte_savedwrite(*ptep))) 432 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 433 } 434 435 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 436 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 437 unsigned long addr, pte_t *ptep) 438 { 439 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 440 return __pte(old); 441 } 442 443 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 444 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 445 unsigned long addr, 446 pte_t *ptep, int full) 447 { 448 if (full && radix_enabled()) { 449 /* 450 * Let's skip the DD1 style pte update here. We know that 451 * this is a full mm pte clear and hence can be sure there is 452 * no parallel set_pte. 453 */ 454 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 455 } 456 return ptep_get_and_clear(mm, addr, ptep); 457 } 458 459 460 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 461 pte_t * ptep) 462 { 463 pte_update(mm, addr, ptep, ~0UL, 0, 0); 464 } 465 466 static inline int pte_dirty(pte_t pte) 467 { 468 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 469 } 470 471 static inline int pte_young(pte_t pte) 472 { 473 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 474 } 475 476 static inline int pte_special(pte_t pte) 477 { 478 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 479 } 480 481 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 482 483 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 484 static inline bool pte_soft_dirty(pte_t pte) 485 { 486 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 487 } 488 489 static inline pte_t pte_mksoft_dirty(pte_t pte) 490 { 491 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); 492 } 493 494 static inline pte_t pte_clear_soft_dirty(pte_t pte) 495 { 496 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); 497 } 498 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 499 500 #ifdef CONFIG_NUMA_BALANCING 501 static inline int pte_protnone(pte_t pte) 502 { 503 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 504 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 505 } 506 507 #define pte_mk_savedwrite pte_mk_savedwrite 508 static inline pte_t pte_mk_savedwrite(pte_t pte) 509 { 510 /* 511 * Used by Autonuma subsystem to preserve the write bit 512 * while marking the pte PROT_NONE. Only allow this 513 * on PROT_NONE pte 514 */ 515 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 516 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 517 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED); 518 } 519 520 #define pte_clear_savedwrite pte_clear_savedwrite 521 static inline pte_t pte_clear_savedwrite(pte_t pte) 522 { 523 /* 524 * Used by KSM subsystem to make a protnone pte readonly. 525 */ 526 VM_BUG_ON(!pte_protnone(pte)); 527 return __pte(pte_val(pte) | _PAGE_PRIVILEGED); 528 } 529 #else 530 #define pte_clear_savedwrite pte_clear_savedwrite 531 static inline pte_t pte_clear_savedwrite(pte_t pte) 532 { 533 VM_WARN_ON(1); 534 return __pte(pte_val(pte) & ~_PAGE_WRITE); 535 } 536 #endif /* CONFIG_NUMA_BALANCING */ 537 538 static inline int pte_present(pte_t pte) 539 { 540 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 541 } 542 /* 543 * Conversion functions: convert a page and protection to a page entry, 544 * and a page entry and page directory to the page they refer to. 545 * 546 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 547 * long for now. 548 */ 549 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 550 { 551 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 552 pgprot_val(pgprot)); 553 } 554 555 static inline unsigned long pte_pfn(pte_t pte) 556 { 557 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 558 } 559 560 /* Generic modifiers for PTE bits */ 561 static inline pte_t pte_wrprotect(pte_t pte) 562 { 563 if (unlikely(pte_savedwrite(pte))) 564 return pte_clear_savedwrite(pte); 565 return __pte(pte_val(pte) & ~_PAGE_WRITE); 566 } 567 568 static inline pte_t pte_mkclean(pte_t pte) 569 { 570 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 571 } 572 573 static inline pte_t pte_mkold(pte_t pte) 574 { 575 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 576 } 577 578 static inline pte_t pte_mkwrite(pte_t pte) 579 { 580 /* 581 * write implies read, hence set both 582 */ 583 return __pte(pte_val(pte) | _PAGE_RW); 584 } 585 586 static inline pte_t pte_mkdirty(pte_t pte) 587 { 588 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 589 } 590 591 static inline pte_t pte_mkyoung(pte_t pte) 592 { 593 return __pte(pte_val(pte) | _PAGE_ACCESSED); 594 } 595 596 static inline pte_t pte_mkspecial(pte_t pte) 597 { 598 return __pte(pte_val(pte) | _PAGE_SPECIAL); 599 } 600 601 static inline pte_t pte_mkhuge(pte_t pte) 602 { 603 return pte; 604 } 605 606 static inline pte_t pte_mkdevmap(pte_t pte) 607 { 608 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP); 609 } 610 611 static inline int pte_devmap(pte_t pte) 612 { 613 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DEVMAP)); 614 } 615 616 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 617 { 618 /* FIXME!! check whether this need to be a conditional */ 619 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 620 } 621 622 static inline bool pte_user(pte_t pte) 623 { 624 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 625 } 626 627 /* Encode and de-code a swap entry */ 628 #define MAX_SWAPFILES_CHECK() do { \ 629 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 630 /* \ 631 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 632 * We filter HPTEFLAGS on set_pte. \ 633 */ \ 634 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 635 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 636 } while (0) 637 /* 638 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 639 */ 640 #define SWP_TYPE_BITS 5 641 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 642 & ((1UL << SWP_TYPE_BITS) - 1)) 643 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 644 #define __swp_entry(type, offset) ((swp_entry_t) { \ 645 ((type) << _PAGE_BIT_SWAP_TYPE) \ 646 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 647 /* 648 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 649 * swap type and offset we get from swap and convert that to pte to find a 650 * matching pte in linux page table. 651 * Clear bits not found in swap entries here. 652 */ 653 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 654 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 655 656 #ifdef CONFIG_MEM_SOFT_DIRTY 657 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 658 #else 659 #define _PAGE_SWP_SOFT_DIRTY 0UL 660 #endif /* CONFIG_MEM_SOFT_DIRTY */ 661 662 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 663 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 664 { 665 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); 666 } 667 668 static inline bool pte_swp_soft_dirty(pte_t pte) 669 { 670 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 671 } 672 673 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 674 { 675 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); 676 } 677 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 678 679 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 680 { 681 /* 682 * This check for _PAGE_RWX and _PAGE_PRESENT bits 683 */ 684 if (access & ~ptev) 685 return false; 686 /* 687 * This check for access to privilege space 688 */ 689 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 690 return false; 691 692 return true; 693 } 694 /* 695 * Generic functions with hash/radix callbacks 696 */ 697 698 static inline void __ptep_set_access_flags(struct mm_struct *mm, 699 pte_t *ptep, pte_t entry, 700 unsigned long address) 701 { 702 if (radix_enabled()) 703 return radix__ptep_set_access_flags(mm, ptep, entry, address); 704 return hash__ptep_set_access_flags(ptep, entry); 705 } 706 707 #define __HAVE_ARCH_PTE_SAME 708 static inline int pte_same(pte_t pte_a, pte_t pte_b) 709 { 710 if (radix_enabled()) 711 return radix__pte_same(pte_a, pte_b); 712 return hash__pte_same(pte_a, pte_b); 713 } 714 715 static inline int pte_none(pte_t pte) 716 { 717 if (radix_enabled()) 718 return radix__pte_none(pte); 719 return hash__pte_none(pte); 720 } 721 722 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 723 pte_t *ptep, pte_t pte, int percpu) 724 { 725 if (radix_enabled()) 726 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 727 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 728 } 729 730 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 731 732 #define pgprot_noncached pgprot_noncached 733 static inline pgprot_t pgprot_noncached(pgprot_t prot) 734 { 735 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 736 _PAGE_NON_IDEMPOTENT); 737 } 738 739 #define pgprot_noncached_wc pgprot_noncached_wc 740 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 741 { 742 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 743 _PAGE_TOLERANT); 744 } 745 746 #define pgprot_cached pgprot_cached 747 static inline pgprot_t pgprot_cached(pgprot_t prot) 748 { 749 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 750 } 751 752 #define pgprot_writecombine pgprot_writecombine 753 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 754 { 755 return pgprot_noncached_wc(prot); 756 } 757 /* 758 * check a pte mapping have cache inhibited property 759 */ 760 static inline bool pte_ci(pte_t pte) 761 { 762 unsigned long pte_v = pte_val(pte); 763 764 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || 765 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) 766 return true; 767 return false; 768 } 769 770 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 771 { 772 *pmdp = __pmd(val); 773 } 774 775 static inline void pmd_clear(pmd_t *pmdp) 776 { 777 *pmdp = __pmd(0); 778 } 779 780 static inline int pmd_none(pmd_t pmd) 781 { 782 return !pmd_raw(pmd); 783 } 784 785 static inline int pmd_present(pmd_t pmd) 786 { 787 788 return !pmd_none(pmd); 789 } 790 791 static inline int pmd_bad(pmd_t pmd) 792 { 793 if (radix_enabled()) 794 return radix__pmd_bad(pmd); 795 return hash__pmd_bad(pmd); 796 } 797 798 static inline void pud_set(pud_t *pudp, unsigned long val) 799 { 800 *pudp = __pud(val); 801 } 802 803 static inline void pud_clear(pud_t *pudp) 804 { 805 *pudp = __pud(0); 806 } 807 808 static inline int pud_none(pud_t pud) 809 { 810 return !pud_raw(pud); 811 } 812 813 static inline int pud_present(pud_t pud) 814 { 815 return !pud_none(pud); 816 } 817 818 extern struct page *pud_page(pud_t pud); 819 extern struct page *pmd_page(pmd_t pmd); 820 static inline pte_t pud_pte(pud_t pud) 821 { 822 return __pte_raw(pud_raw(pud)); 823 } 824 825 static inline pud_t pte_pud(pte_t pte) 826 { 827 return __pud_raw(pte_raw(pte)); 828 } 829 #define pud_write(pud) pte_write(pud_pte(pud)) 830 831 static inline int pud_bad(pud_t pud) 832 { 833 if (radix_enabled()) 834 return radix__pud_bad(pud); 835 return hash__pud_bad(pud); 836 } 837 838 839 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 840 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 841 { 842 *pgdp = __pgd(val); 843 } 844 845 static inline void pgd_clear(pgd_t *pgdp) 846 { 847 *pgdp = __pgd(0); 848 } 849 850 static inline int pgd_none(pgd_t pgd) 851 { 852 return !pgd_raw(pgd); 853 } 854 855 static inline int pgd_present(pgd_t pgd) 856 { 857 return !pgd_none(pgd); 858 } 859 860 static inline pte_t pgd_pte(pgd_t pgd) 861 { 862 return __pte_raw(pgd_raw(pgd)); 863 } 864 865 static inline pgd_t pte_pgd(pte_t pte) 866 { 867 return __pgd_raw(pte_raw(pte)); 868 } 869 870 static inline int pgd_bad(pgd_t pgd) 871 { 872 if (radix_enabled()) 873 return radix__pgd_bad(pgd); 874 return hash__pgd_bad(pgd); 875 } 876 877 extern struct page *pgd_page(pgd_t pgd); 878 879 /* Pointers in the page table tree are physical addresses */ 880 #define __pgtable_ptr_val(ptr) __pa(ptr) 881 882 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 883 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 884 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 885 886 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 887 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 888 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 889 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 890 891 /* 892 * Find an entry in a page-table-directory. We combine the address region 893 * (the high order N bits) and the pgd portion of the address. 894 */ 895 896 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 897 898 #define pud_offset(pgdp, addr) \ 899 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 900 #define pmd_offset(pudp,addr) \ 901 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 902 #define pte_offset_kernel(dir,addr) \ 903 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 904 905 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 906 #define pte_unmap(pte) do { } while(0) 907 908 /* to find an entry in a kernel page-table-directory */ 909 /* This now only contains the vmalloc pages */ 910 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 911 912 #define pte_ERROR(e) \ 913 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 914 #define pmd_ERROR(e) \ 915 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 916 #define pud_ERROR(e) \ 917 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 918 #define pgd_ERROR(e) \ 919 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 920 921 static inline int map_kernel_page(unsigned long ea, unsigned long pa, 922 unsigned long flags) 923 { 924 if (radix_enabled()) { 925 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 926 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 927 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 928 #endif 929 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); 930 } 931 return hash__map_kernel_page(ea, pa, flags); 932 } 933 934 static inline int __meminit vmemmap_create_mapping(unsigned long start, 935 unsigned long page_size, 936 unsigned long phys) 937 { 938 if (radix_enabled()) 939 return radix__vmemmap_create_mapping(start, page_size, phys); 940 return hash__vmemmap_create_mapping(start, page_size, phys); 941 } 942 943 #ifdef CONFIG_MEMORY_HOTPLUG 944 static inline void vmemmap_remove_mapping(unsigned long start, 945 unsigned long page_size) 946 { 947 if (radix_enabled()) 948 return radix__vmemmap_remove_mapping(start, page_size); 949 return hash__vmemmap_remove_mapping(start, page_size); 950 } 951 #endif 952 struct page *realmode_pfn_to_page(unsigned long pfn); 953 954 static inline pte_t pmd_pte(pmd_t pmd) 955 { 956 return __pte_raw(pmd_raw(pmd)); 957 } 958 959 static inline pmd_t pte_pmd(pte_t pte) 960 { 961 return __pmd_raw(pte_raw(pte)); 962 } 963 964 static inline pte_t *pmdp_ptep(pmd_t *pmd) 965 { 966 return (pte_t *)pmd; 967 } 968 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 969 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 970 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 971 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 972 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 973 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 974 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 975 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 976 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 977 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 978 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 979 980 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 981 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 982 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 983 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 984 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 985 986 #ifdef CONFIG_NUMA_BALANCING 987 static inline int pmd_protnone(pmd_t pmd) 988 { 989 return pte_protnone(pmd_pte(pmd)); 990 } 991 #endif /* CONFIG_NUMA_BALANCING */ 992 993 #define __HAVE_ARCH_PMD_WRITE 994 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 995 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 996 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 997 998 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 999 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1000 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1001 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1002 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1003 pmd_t *pmdp, pmd_t pmd); 1004 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1005 pmd_t *pmd); 1006 extern int hash__has_transparent_hugepage(void); 1007 static inline int has_transparent_hugepage(void) 1008 { 1009 if (radix_enabled()) 1010 return radix__has_transparent_hugepage(); 1011 return hash__has_transparent_hugepage(); 1012 } 1013 #define has_transparent_hugepage has_transparent_hugepage 1014 1015 static inline unsigned long 1016 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1017 unsigned long clr, unsigned long set) 1018 { 1019 if (radix_enabled()) 1020 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1021 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1022 } 1023 1024 static inline int pmd_large(pmd_t pmd) 1025 { 1026 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1027 } 1028 1029 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1030 { 1031 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1032 } 1033 /* 1034 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1035 * the below will work for radix too 1036 */ 1037 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1038 unsigned long addr, pmd_t *pmdp) 1039 { 1040 unsigned long old; 1041 1042 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1043 return 0; 1044 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1045 return ((old & _PAGE_ACCESSED) != 0); 1046 } 1047 1048 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1049 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1050 pmd_t *pmdp) 1051 { 1052 if (__pmd_write((*pmdp))) 1053 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1054 else if (unlikely(pmd_savedwrite(*pmdp))) 1055 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1056 } 1057 1058 static inline int pmd_trans_huge(pmd_t pmd) 1059 { 1060 if (radix_enabled()) 1061 return radix__pmd_trans_huge(pmd); 1062 return hash__pmd_trans_huge(pmd); 1063 } 1064 1065 #define __HAVE_ARCH_PMD_SAME 1066 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1067 { 1068 if (radix_enabled()) 1069 return radix__pmd_same(pmd_a, pmd_b); 1070 return hash__pmd_same(pmd_a, pmd_b); 1071 } 1072 1073 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1074 { 1075 if (radix_enabled()) 1076 return radix__pmd_mkhuge(pmd); 1077 return hash__pmd_mkhuge(pmd); 1078 } 1079 1080 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1081 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1082 unsigned long address, pmd_t *pmdp, 1083 pmd_t entry, int dirty); 1084 1085 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1086 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1087 unsigned long address, pmd_t *pmdp); 1088 1089 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1090 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1091 unsigned long addr, pmd_t *pmdp) 1092 { 1093 if (radix_enabled()) 1094 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1095 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1096 } 1097 1098 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1099 unsigned long address, pmd_t *pmdp) 1100 { 1101 if (radix_enabled()) 1102 return radix__pmdp_collapse_flush(vma, address, pmdp); 1103 return hash__pmdp_collapse_flush(vma, address, pmdp); 1104 } 1105 #define pmdp_collapse_flush pmdp_collapse_flush 1106 1107 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1108 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1109 pmd_t *pmdp, pgtable_t pgtable) 1110 { 1111 if (radix_enabled()) 1112 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1113 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1114 } 1115 1116 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1117 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1118 pmd_t *pmdp) 1119 { 1120 if (radix_enabled()) 1121 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1122 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1123 } 1124 1125 #define __HAVE_ARCH_PMDP_INVALIDATE 1126 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1127 pmd_t *pmdp); 1128 1129 #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE 1130 static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma, 1131 unsigned long address, pmd_t *pmdp) 1132 { 1133 if (radix_enabled()) 1134 return radix__pmdp_huge_split_prepare(vma, address, pmdp); 1135 return hash__pmdp_huge_split_prepare(vma, address, pmdp); 1136 } 1137 1138 #define pmd_move_must_withdraw pmd_move_must_withdraw 1139 struct spinlock; 1140 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1141 struct spinlock *old_pmd_ptl, 1142 struct vm_area_struct *vma) 1143 { 1144 if (radix_enabled()) 1145 return false; 1146 /* 1147 * Archs like ppc64 use pgtable to store per pmd 1148 * specific information. So when we switch the pmd, 1149 * we should also withdraw and deposit the pgtable 1150 */ 1151 return true; 1152 } 1153 1154 1155 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1156 static inline bool arch_needs_pgtable_deposit(void) 1157 { 1158 if (radix_enabled()) 1159 return false; 1160 return true; 1161 } 1162 1163 1164 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1165 { 1166 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1167 } 1168 1169 static inline int pmd_devmap(pmd_t pmd) 1170 { 1171 return pte_devmap(pmd_pte(pmd)); 1172 } 1173 1174 static inline int pud_devmap(pud_t pud) 1175 { 1176 return 0; 1177 } 1178 1179 static inline int pgd_devmap(pgd_t pgd) 1180 { 1181 return 0; 1182 } 1183 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1184 1185 static inline const int pud_pfn(pud_t pud) 1186 { 1187 /* 1188 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1189 * check so this should never be used. If it grows another user we 1190 * want to know about it. 1191 */ 1192 BUILD_BUG(); 1193 return 0; 1194 } 1195 1196 #endif /* __ASSEMBLY__ */ 1197 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1198