1 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 2 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 4 #include <asm-generic/5level-fixup.h> 5 6 #ifndef __ASSEMBLY__ 7 #include <linux/mmdebug.h> 8 #include <linux/bug.h> 9 #endif 10 11 /* 12 * Common bits between hash and Radix page table 13 */ 14 #define _PAGE_BIT_SWAP_TYPE 0 15 16 #define _PAGE_RO 0 17 #define _PAGE_SHARED 0 18 19 #define _PAGE_EXEC 0x00001 /* execute permission */ 20 #define _PAGE_WRITE 0x00002 /* write access allowed */ 21 #define _PAGE_READ 0x00004 /* read access allowed */ 22 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 23 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 24 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 25 #define _PAGE_SAO 0x00010 /* Strong access order */ 26 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 27 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 28 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 29 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 30 /* 31 * Software bits 32 */ 33 #define _RPAGE_SW0 0x2000000000000000UL 34 #define _RPAGE_SW1 0x00800 35 #define _RPAGE_SW2 0x00400 36 #define _RPAGE_SW3 0x00200 37 #define _RPAGE_RSV1 0x1000000000000000UL 38 #define _RPAGE_RSV2 0x0800000000000000UL 39 #define _RPAGE_RSV3 0x0400000000000000UL 40 #define _RPAGE_RSV4 0x0200000000000000UL 41 42 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 43 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 44 45 /* 46 * Top and bottom bits of RPN which can be used by hash 47 * translation mode, because we expect them to be zero 48 * otherwise. 49 */ 50 #define _RPAGE_RPN0 0x01000 51 #define _RPAGE_RPN1 0x02000 52 #define _RPAGE_RPN44 0x0100000000000000UL 53 #define _RPAGE_RPN43 0x0080000000000000UL 54 #define _RPAGE_RPN42 0x0040000000000000UL 55 #define _RPAGE_RPN41 0x0020000000000000UL 56 57 /* Max physical address bit as per radix table */ 58 #define _RPAGE_PA_MAX 57 59 60 /* 61 * Max physical address bit we will use for now. 62 * 63 * This is mostly a hardware limitation and for now Power9 has 64 * a 51 bit limit. 65 * 66 * This is different from the number of physical bit required to address 67 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 68 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 69 * number of sections we can support (SECTIONS_SHIFT). 70 * 71 * This is different from Radix page table limitation above and 72 * should always be less than that. The limit is done such that 73 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 74 * for hash linux page table specific bits. 75 * 76 * In order to be compatible with future hardware generations we keep 77 * some offsets and limit this for now to 53 78 */ 79 #define _PAGE_PA_MAX 53 80 81 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 82 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 83 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 84 #define __HAVE_ARCH_PTE_DEVMAP 85 86 /* 87 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 88 * Instead of fixing all of them, add an alternate define which 89 * maps CI pte mapping. 90 */ 91 #define _PAGE_NO_CACHE _PAGE_TOLERANT 92 /* 93 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 94 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 95 * and every thing below PAGE_SHIFT; 96 */ 97 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 98 /* 99 * set of bits not changed in pmd_modify. Even though we have hash specific bits 100 * in here, on radix we expect them to be zero. 101 */ 102 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 103 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 104 _PAGE_SOFT_DIRTY) 105 /* 106 * user access blocked by key 107 */ 108 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 109 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 110 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 111 _PAGE_RW | _PAGE_EXEC) 112 /* 113 * No page size encoding in the linux PTE 114 */ 115 #define _PAGE_PSIZE 0 116 /* 117 * _PAGE_CHG_MASK masks of bits that are to be preserved across 118 * pgprot changes 119 */ 120 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 121 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 122 _PAGE_SOFT_DIRTY) 123 /* 124 * Mask of bits returned by pte_pgprot() 125 */ 126 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ 127 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ 128 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ 129 _PAGE_SOFT_DIRTY) 130 /* 131 * We define 2 sets of base prot bits, one for basic pages (ie, 132 * cacheable kernel and user pages) and one for non cacheable 133 * pages. We always set _PAGE_COHERENT when SMP is enabled or 134 * the processor might need it for DMA coherency. 135 */ 136 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 137 #define _PAGE_BASE (_PAGE_BASE_NC) 138 139 /* Permission masks used to generate the __P and __S table, 140 * 141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 142 * 143 * Write permissions imply read permissions for now (we could make write-only 144 * pages on BookE but we don't bother for now). Execute permission control is 145 * possible on platforms that define _PAGE_EXEC 146 * 147 * Note due to the way vm flags are laid out, the bits are XWR 148 */ 149 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 150 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 151 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 152 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 153 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 154 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 155 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 156 157 #define __P000 PAGE_NONE 158 #define __P001 PAGE_READONLY 159 #define __P010 PAGE_COPY 160 #define __P011 PAGE_COPY 161 #define __P100 PAGE_READONLY_X 162 #define __P101 PAGE_READONLY_X 163 #define __P110 PAGE_COPY_X 164 #define __P111 PAGE_COPY_X 165 166 #define __S000 PAGE_NONE 167 #define __S001 PAGE_READONLY 168 #define __S010 PAGE_SHARED 169 #define __S011 PAGE_SHARED 170 #define __S100 PAGE_READONLY_X 171 #define __S101 PAGE_READONLY_X 172 #define __S110 PAGE_SHARED_X 173 #define __S111 PAGE_SHARED_X 174 175 /* Permission masks used for kernel mappings */ 176 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 177 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 178 _PAGE_TOLERANT) 179 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 180 _PAGE_NON_IDEMPOTENT) 181 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 182 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 183 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 184 185 /* 186 * Protection used for kernel text. We want the debuggers to be able to 187 * set breakpoints anywhere, so don't write protect the kernel text 188 * on platforms where such control is possible. 189 */ 190 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 191 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 192 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 193 #else 194 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 195 #endif 196 197 /* Make modules code happy. We don't set RO yet */ 198 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 199 #define PAGE_AGP (PAGE_KERNEL_NC) 200 201 #ifndef __ASSEMBLY__ 202 /* 203 * page table defines 204 */ 205 extern unsigned long __pte_index_size; 206 extern unsigned long __pmd_index_size; 207 extern unsigned long __pud_index_size; 208 extern unsigned long __pgd_index_size; 209 extern unsigned long __pmd_cache_index; 210 #define PTE_INDEX_SIZE __pte_index_size 211 #define PMD_INDEX_SIZE __pmd_index_size 212 #define PUD_INDEX_SIZE __pud_index_size 213 #define PGD_INDEX_SIZE __pgd_index_size 214 #define PMD_CACHE_INDEX __pmd_cache_index 215 /* 216 * Because of use of pte fragments and THP, size of page table 217 * are not always derived out of index size above. 218 */ 219 extern unsigned long __pte_table_size; 220 extern unsigned long __pmd_table_size; 221 extern unsigned long __pud_table_size; 222 extern unsigned long __pgd_table_size; 223 #define PTE_TABLE_SIZE __pte_table_size 224 #define PMD_TABLE_SIZE __pmd_table_size 225 #define PUD_TABLE_SIZE __pud_table_size 226 #define PGD_TABLE_SIZE __pgd_table_size 227 228 extern unsigned long __pmd_val_bits; 229 extern unsigned long __pud_val_bits; 230 extern unsigned long __pgd_val_bits; 231 #define PMD_VAL_BITS __pmd_val_bits 232 #define PUD_VAL_BITS __pud_val_bits 233 #define PGD_VAL_BITS __pgd_val_bits 234 235 extern unsigned long __pte_frag_nr; 236 #define PTE_FRAG_NR __pte_frag_nr 237 extern unsigned long __pte_frag_size_shift; 238 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 239 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 240 241 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 242 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 243 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 244 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 245 246 /* PMD_SHIFT determines what a second-level page table entry can map */ 247 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 248 #define PMD_SIZE (1UL << PMD_SHIFT) 249 #define PMD_MASK (~(PMD_SIZE-1)) 250 251 /* PUD_SHIFT determines what a third-level page table entry can map */ 252 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 253 #define PUD_SIZE (1UL << PUD_SHIFT) 254 #define PUD_MASK (~(PUD_SIZE-1)) 255 256 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 257 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 258 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 259 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 260 261 /* Bits to mask out from a PMD to get to the PTE page */ 262 #define PMD_MASKED_BITS 0xc0000000000000ffUL 263 /* Bits to mask out from a PUD to get to the PMD page */ 264 #define PUD_MASKED_BITS 0xc0000000000000ffUL 265 /* Bits to mask out from a PGD to get to the PUD page */ 266 #define PGD_MASKED_BITS 0xc0000000000000ffUL 267 268 extern unsigned long __vmalloc_start; 269 extern unsigned long __vmalloc_end; 270 #define VMALLOC_START __vmalloc_start 271 #define VMALLOC_END __vmalloc_end 272 273 extern unsigned long __kernel_virt_start; 274 extern unsigned long __kernel_virt_size; 275 extern unsigned long __kernel_io_start; 276 #define KERN_VIRT_START __kernel_virt_start 277 #define KERN_VIRT_SIZE __kernel_virt_size 278 #define KERN_IO_START __kernel_io_start 279 extern struct page *vmemmap; 280 extern unsigned long ioremap_bot; 281 extern unsigned long pci_io_base; 282 #endif /* __ASSEMBLY__ */ 283 284 #include <asm/book3s/64/hash.h> 285 #include <asm/book3s/64/radix.h> 286 287 #ifdef CONFIG_PPC_64K_PAGES 288 #include <asm/book3s/64/pgtable-64k.h> 289 #else 290 #include <asm/book3s/64/pgtable-4k.h> 291 #endif 292 293 #include <asm/barrier.h> 294 /* 295 * The second half of the kernel virtual space is used for IO mappings, 296 * it's itself carved into the PIO region (ISA and PHB IO space) and 297 * the ioremap space 298 * 299 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 300 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 301 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 302 */ 303 #define FULL_IO_SIZE 0x80000000ul 304 #define ISA_IO_BASE (KERN_IO_START) 305 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 306 #define PHB_IO_BASE (ISA_IO_END) 307 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 308 #define IOREMAP_BASE (PHB_IO_END) 309 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 310 311 /* Advertise special mapping type for AGP */ 312 #define HAVE_PAGE_AGP 313 314 /* Advertise support for _PAGE_SPECIAL */ 315 #define __HAVE_ARCH_PTE_SPECIAL 316 317 #ifndef __ASSEMBLY__ 318 319 /* 320 * This is the default implementation of various PTE accessors, it's 321 * used in all cases except Book3S with 64K pages where we have a 322 * concept of sub-pages 323 */ 324 #ifndef __real_pte 325 326 #define __real_pte(e,p) ((real_pte_t){(e)}) 327 #define __rpte_to_pte(r) ((r).pte) 328 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 329 330 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 331 do { \ 332 index = 0; \ 333 shift = mmu_psize_defs[psize].shift; \ 334 335 #define pte_iterate_hashed_end() } while(0) 336 337 /* 338 * We expect this to be called only for user addresses or kernel virtual 339 * addresses other than the linear mapping. 340 */ 341 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 342 343 #endif /* __real_pte */ 344 345 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 346 pte_t *ptep, unsigned long clr, 347 unsigned long set, int huge) 348 { 349 if (radix_enabled()) 350 return radix__pte_update(mm, addr, ptep, clr, set, huge); 351 return hash__pte_update(mm, addr, ptep, clr, set, huge); 352 } 353 /* 354 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 355 * We currently remove entries from the hashtable regardless of whether 356 * the entry was young or dirty. 357 * 358 * We should be more intelligent about this but for the moment we override 359 * these functions and force a tlb flush unconditionally 360 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 361 * function for both hash and radix. 362 */ 363 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 364 unsigned long addr, pte_t *ptep) 365 { 366 unsigned long old; 367 368 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 369 return 0; 370 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 371 return (old & _PAGE_ACCESSED) != 0; 372 } 373 374 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 375 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 376 ({ \ 377 int __r; \ 378 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 379 __r; \ 380 }) 381 382 static inline int __pte_write(pte_t pte) 383 { 384 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 385 } 386 387 #ifdef CONFIG_NUMA_BALANCING 388 #define pte_savedwrite pte_savedwrite 389 static inline bool pte_savedwrite(pte_t pte) 390 { 391 /* 392 * Saved write ptes are prot none ptes that doesn't have 393 * privileged bit sit. We mark prot none as one which has 394 * present and pviliged bit set and RWX cleared. To mark 395 * protnone which used to have _PAGE_WRITE set we clear 396 * the privileged bit. 397 */ 398 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 399 } 400 #else 401 #define pte_savedwrite pte_savedwrite 402 static inline bool pte_savedwrite(pte_t pte) 403 { 404 return false; 405 } 406 #endif 407 408 static inline int pte_write(pte_t pte) 409 { 410 return __pte_write(pte) || pte_savedwrite(pte); 411 } 412 413 static inline int pte_read(pte_t pte) 414 { 415 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 416 } 417 418 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 419 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 420 pte_t *ptep) 421 { 422 if (__pte_write(*ptep)) 423 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 424 else if (unlikely(pte_savedwrite(*ptep))) 425 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 426 } 427 428 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 429 unsigned long addr, pte_t *ptep) 430 { 431 /* 432 * We should not find protnone for hugetlb, but this complete the 433 * interface. 434 */ 435 if (__pte_write(*ptep)) 436 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 437 else if (unlikely(pte_savedwrite(*ptep))) 438 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 439 } 440 441 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 442 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 443 unsigned long addr, pte_t *ptep) 444 { 445 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 446 return __pte(old); 447 } 448 449 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 450 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 451 unsigned long addr, 452 pte_t *ptep, int full) 453 { 454 if (full && radix_enabled()) { 455 /* 456 * Let's skip the DD1 style pte update here. We know that 457 * this is a full mm pte clear and hence can be sure there is 458 * no parallel set_pte. 459 */ 460 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 461 } 462 return ptep_get_and_clear(mm, addr, ptep); 463 } 464 465 466 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 467 pte_t * ptep) 468 { 469 pte_update(mm, addr, ptep, ~0UL, 0, 0); 470 } 471 472 static inline int pte_dirty(pte_t pte) 473 { 474 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 475 } 476 477 static inline int pte_young(pte_t pte) 478 { 479 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 480 } 481 482 static inline int pte_special(pte_t pte) 483 { 484 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 485 } 486 487 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 488 489 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 490 static inline bool pte_soft_dirty(pte_t pte) 491 { 492 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 493 } 494 495 static inline pte_t pte_mksoft_dirty(pte_t pte) 496 { 497 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); 498 } 499 500 static inline pte_t pte_clear_soft_dirty(pte_t pte) 501 { 502 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); 503 } 504 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 505 506 #ifdef CONFIG_NUMA_BALANCING 507 static inline int pte_protnone(pte_t pte) 508 { 509 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 510 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 511 } 512 513 #define pte_mk_savedwrite pte_mk_savedwrite 514 static inline pte_t pte_mk_savedwrite(pte_t pte) 515 { 516 /* 517 * Used by Autonuma subsystem to preserve the write bit 518 * while marking the pte PROT_NONE. Only allow this 519 * on PROT_NONE pte 520 */ 521 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 522 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 523 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED); 524 } 525 526 #define pte_clear_savedwrite pte_clear_savedwrite 527 static inline pte_t pte_clear_savedwrite(pte_t pte) 528 { 529 /* 530 * Used by KSM subsystem to make a protnone pte readonly. 531 */ 532 VM_BUG_ON(!pte_protnone(pte)); 533 return __pte(pte_val(pte) | _PAGE_PRIVILEGED); 534 } 535 #else 536 #define pte_clear_savedwrite pte_clear_savedwrite 537 static inline pte_t pte_clear_savedwrite(pte_t pte) 538 { 539 VM_WARN_ON(1); 540 return __pte(pte_val(pte) & ~_PAGE_WRITE); 541 } 542 #endif /* CONFIG_NUMA_BALANCING */ 543 544 static inline int pte_present(pte_t pte) 545 { 546 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 547 } 548 /* 549 * Conversion functions: convert a page and protection to a page entry, 550 * and a page entry and page directory to the page they refer to. 551 * 552 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 553 * long for now. 554 */ 555 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 556 { 557 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 558 pgprot_val(pgprot)); 559 } 560 561 static inline unsigned long pte_pfn(pte_t pte) 562 { 563 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 564 } 565 566 /* Generic modifiers for PTE bits */ 567 static inline pte_t pte_wrprotect(pte_t pte) 568 { 569 if (unlikely(pte_savedwrite(pte))) 570 return pte_clear_savedwrite(pte); 571 return __pte(pte_val(pte) & ~_PAGE_WRITE); 572 } 573 574 static inline pte_t pte_mkclean(pte_t pte) 575 { 576 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 577 } 578 579 static inline pte_t pte_mkold(pte_t pte) 580 { 581 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 582 } 583 584 static inline pte_t pte_mkwrite(pte_t pte) 585 { 586 /* 587 * write implies read, hence set both 588 */ 589 return __pte(pte_val(pte) | _PAGE_RW); 590 } 591 592 static inline pte_t pte_mkdirty(pte_t pte) 593 { 594 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 595 } 596 597 static inline pte_t pte_mkyoung(pte_t pte) 598 { 599 return __pte(pte_val(pte) | _PAGE_ACCESSED); 600 } 601 602 static inline pte_t pte_mkspecial(pte_t pte) 603 { 604 return __pte(pte_val(pte) | _PAGE_SPECIAL); 605 } 606 607 static inline pte_t pte_mkhuge(pte_t pte) 608 { 609 return pte; 610 } 611 612 static inline pte_t pte_mkdevmap(pte_t pte) 613 { 614 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP); 615 } 616 617 /* 618 * This is potentially called with a pmd as the argument, in which case it's not 619 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 620 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 621 * use in page directory entries (ie. non-ptes). 622 */ 623 static inline int pte_devmap(pte_t pte) 624 { 625 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 626 627 return (pte_raw(pte) & mask) == mask; 628 } 629 630 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 631 { 632 /* FIXME!! check whether this need to be a conditional */ 633 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 634 } 635 636 static inline bool pte_user(pte_t pte) 637 { 638 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 639 } 640 641 /* Encode and de-code a swap entry */ 642 #define MAX_SWAPFILES_CHECK() do { \ 643 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 644 /* \ 645 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 646 * We filter HPTEFLAGS on set_pte. \ 647 */ \ 648 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 649 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 650 } while (0) 651 /* 652 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 653 */ 654 #define SWP_TYPE_BITS 5 655 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 656 & ((1UL << SWP_TYPE_BITS) - 1)) 657 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 658 #define __swp_entry(type, offset) ((swp_entry_t) { \ 659 ((type) << _PAGE_BIT_SWAP_TYPE) \ 660 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 661 /* 662 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 663 * swap type and offset we get from swap and convert that to pte to find a 664 * matching pte in linux page table. 665 * Clear bits not found in swap entries here. 666 */ 667 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 668 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 669 670 #ifdef CONFIG_MEM_SOFT_DIRTY 671 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 672 #else 673 #define _PAGE_SWP_SOFT_DIRTY 0UL 674 #endif /* CONFIG_MEM_SOFT_DIRTY */ 675 676 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 677 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 678 { 679 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); 680 } 681 682 static inline bool pte_swp_soft_dirty(pte_t pte) 683 { 684 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 685 } 686 687 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 688 { 689 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); 690 } 691 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 692 693 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 694 { 695 /* 696 * This check for _PAGE_RWX and _PAGE_PRESENT bits 697 */ 698 if (access & ~ptev) 699 return false; 700 /* 701 * This check for access to privilege space 702 */ 703 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 704 return false; 705 706 return true; 707 } 708 /* 709 * Generic functions with hash/radix callbacks 710 */ 711 712 static inline void __ptep_set_access_flags(struct mm_struct *mm, 713 pte_t *ptep, pte_t entry, 714 unsigned long address) 715 { 716 if (radix_enabled()) 717 return radix__ptep_set_access_flags(mm, ptep, entry, address); 718 return hash__ptep_set_access_flags(ptep, entry); 719 } 720 721 #define __HAVE_ARCH_PTE_SAME 722 static inline int pte_same(pte_t pte_a, pte_t pte_b) 723 { 724 if (radix_enabled()) 725 return radix__pte_same(pte_a, pte_b); 726 return hash__pte_same(pte_a, pte_b); 727 } 728 729 static inline int pte_none(pte_t pte) 730 { 731 if (radix_enabled()) 732 return radix__pte_none(pte); 733 return hash__pte_none(pte); 734 } 735 736 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 737 pte_t *ptep, pte_t pte, int percpu) 738 { 739 if (radix_enabled()) 740 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 741 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 742 } 743 744 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 745 746 #define pgprot_noncached pgprot_noncached 747 static inline pgprot_t pgprot_noncached(pgprot_t prot) 748 { 749 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 750 _PAGE_NON_IDEMPOTENT); 751 } 752 753 #define pgprot_noncached_wc pgprot_noncached_wc 754 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 755 { 756 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 757 _PAGE_TOLERANT); 758 } 759 760 #define pgprot_cached pgprot_cached 761 static inline pgprot_t pgprot_cached(pgprot_t prot) 762 { 763 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 764 } 765 766 #define pgprot_writecombine pgprot_writecombine 767 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 768 { 769 return pgprot_noncached_wc(prot); 770 } 771 /* 772 * check a pte mapping have cache inhibited property 773 */ 774 static inline bool pte_ci(pte_t pte) 775 { 776 unsigned long pte_v = pte_val(pte); 777 778 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || 779 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) 780 return true; 781 return false; 782 } 783 784 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 785 { 786 *pmdp = __pmd(val); 787 } 788 789 static inline void pmd_clear(pmd_t *pmdp) 790 { 791 *pmdp = __pmd(0); 792 } 793 794 static inline int pmd_none(pmd_t pmd) 795 { 796 return !pmd_raw(pmd); 797 } 798 799 static inline int pmd_present(pmd_t pmd) 800 { 801 802 return !pmd_none(pmd); 803 } 804 805 static inline int pmd_bad(pmd_t pmd) 806 { 807 if (radix_enabled()) 808 return radix__pmd_bad(pmd); 809 return hash__pmd_bad(pmd); 810 } 811 812 static inline void pud_set(pud_t *pudp, unsigned long val) 813 { 814 *pudp = __pud(val); 815 } 816 817 static inline void pud_clear(pud_t *pudp) 818 { 819 *pudp = __pud(0); 820 } 821 822 static inline int pud_none(pud_t pud) 823 { 824 return !pud_raw(pud); 825 } 826 827 static inline int pud_present(pud_t pud) 828 { 829 return !pud_none(pud); 830 } 831 832 extern struct page *pud_page(pud_t pud); 833 extern struct page *pmd_page(pmd_t pmd); 834 static inline pte_t pud_pte(pud_t pud) 835 { 836 return __pte_raw(pud_raw(pud)); 837 } 838 839 static inline pud_t pte_pud(pte_t pte) 840 { 841 return __pud_raw(pte_raw(pte)); 842 } 843 #define pud_write(pud) pte_write(pud_pte(pud)) 844 845 static inline int pud_bad(pud_t pud) 846 { 847 if (radix_enabled()) 848 return radix__pud_bad(pud); 849 return hash__pud_bad(pud); 850 } 851 852 853 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 854 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 855 { 856 *pgdp = __pgd(val); 857 } 858 859 static inline void pgd_clear(pgd_t *pgdp) 860 { 861 *pgdp = __pgd(0); 862 } 863 864 static inline int pgd_none(pgd_t pgd) 865 { 866 return !pgd_raw(pgd); 867 } 868 869 static inline int pgd_present(pgd_t pgd) 870 { 871 return !pgd_none(pgd); 872 } 873 874 static inline pte_t pgd_pte(pgd_t pgd) 875 { 876 return __pte_raw(pgd_raw(pgd)); 877 } 878 879 static inline pgd_t pte_pgd(pte_t pte) 880 { 881 return __pgd_raw(pte_raw(pte)); 882 } 883 884 static inline int pgd_bad(pgd_t pgd) 885 { 886 if (radix_enabled()) 887 return radix__pgd_bad(pgd); 888 return hash__pgd_bad(pgd); 889 } 890 891 extern struct page *pgd_page(pgd_t pgd); 892 893 /* Pointers in the page table tree are physical addresses */ 894 #define __pgtable_ptr_val(ptr) __pa(ptr) 895 896 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 897 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 898 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 899 900 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 901 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 902 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 903 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 904 905 /* 906 * Find an entry in a page-table-directory. We combine the address region 907 * (the high order N bits) and the pgd portion of the address. 908 */ 909 910 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 911 912 #define pud_offset(pgdp, addr) \ 913 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 914 #define pmd_offset(pudp,addr) \ 915 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 916 #define pte_offset_kernel(dir,addr) \ 917 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 918 919 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 920 #define pte_unmap(pte) do { } while(0) 921 922 /* to find an entry in a kernel page-table-directory */ 923 /* This now only contains the vmalloc pages */ 924 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 925 926 #define pte_ERROR(e) \ 927 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 928 #define pmd_ERROR(e) \ 929 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 930 #define pud_ERROR(e) \ 931 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 932 #define pgd_ERROR(e) \ 933 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 934 935 static inline int map_kernel_page(unsigned long ea, unsigned long pa, 936 unsigned long flags) 937 { 938 if (radix_enabled()) { 939 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 940 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 941 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 942 #endif 943 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); 944 } 945 return hash__map_kernel_page(ea, pa, flags); 946 } 947 948 static inline int __meminit vmemmap_create_mapping(unsigned long start, 949 unsigned long page_size, 950 unsigned long phys) 951 { 952 if (radix_enabled()) 953 return radix__vmemmap_create_mapping(start, page_size, phys); 954 return hash__vmemmap_create_mapping(start, page_size, phys); 955 } 956 957 #ifdef CONFIG_MEMORY_HOTPLUG 958 static inline void vmemmap_remove_mapping(unsigned long start, 959 unsigned long page_size) 960 { 961 if (radix_enabled()) 962 return radix__vmemmap_remove_mapping(start, page_size); 963 return hash__vmemmap_remove_mapping(start, page_size); 964 } 965 #endif 966 struct page *realmode_pfn_to_page(unsigned long pfn); 967 968 static inline pte_t pmd_pte(pmd_t pmd) 969 { 970 return __pte_raw(pmd_raw(pmd)); 971 } 972 973 static inline pmd_t pte_pmd(pte_t pte) 974 { 975 return __pmd_raw(pte_raw(pte)); 976 } 977 978 static inline pte_t *pmdp_ptep(pmd_t *pmd) 979 { 980 return (pte_t *)pmd; 981 } 982 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 983 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 984 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 985 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 986 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 987 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 988 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 989 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 990 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 991 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 992 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 993 994 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 995 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 996 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 997 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 998 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 999 1000 #ifdef CONFIG_NUMA_BALANCING 1001 static inline int pmd_protnone(pmd_t pmd) 1002 { 1003 return pte_protnone(pmd_pte(pmd)); 1004 } 1005 #endif /* CONFIG_NUMA_BALANCING */ 1006 1007 #define __HAVE_ARCH_PMD_WRITE 1008 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1009 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1010 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1011 1012 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1013 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1014 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1015 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1016 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1017 pmd_t *pmdp, pmd_t pmd); 1018 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1019 pmd_t *pmd); 1020 extern int hash__has_transparent_hugepage(void); 1021 static inline int has_transparent_hugepage(void) 1022 { 1023 if (radix_enabled()) 1024 return radix__has_transparent_hugepage(); 1025 return hash__has_transparent_hugepage(); 1026 } 1027 #define has_transparent_hugepage has_transparent_hugepage 1028 1029 static inline unsigned long 1030 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1031 unsigned long clr, unsigned long set) 1032 { 1033 if (radix_enabled()) 1034 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1035 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1036 } 1037 1038 static inline int pmd_large(pmd_t pmd) 1039 { 1040 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1041 } 1042 1043 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1044 { 1045 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1046 } 1047 /* 1048 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1049 * the below will work for radix too 1050 */ 1051 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1052 unsigned long addr, pmd_t *pmdp) 1053 { 1054 unsigned long old; 1055 1056 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1057 return 0; 1058 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1059 return ((old & _PAGE_ACCESSED) != 0); 1060 } 1061 1062 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1063 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1064 pmd_t *pmdp) 1065 { 1066 if (__pmd_write((*pmdp))) 1067 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1068 else if (unlikely(pmd_savedwrite(*pmdp))) 1069 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1070 } 1071 1072 static inline int pmd_trans_huge(pmd_t pmd) 1073 { 1074 if (radix_enabled()) 1075 return radix__pmd_trans_huge(pmd); 1076 return hash__pmd_trans_huge(pmd); 1077 } 1078 1079 #define __HAVE_ARCH_PMD_SAME 1080 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1081 { 1082 if (radix_enabled()) 1083 return radix__pmd_same(pmd_a, pmd_b); 1084 return hash__pmd_same(pmd_a, pmd_b); 1085 } 1086 1087 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1088 { 1089 if (radix_enabled()) 1090 return radix__pmd_mkhuge(pmd); 1091 return hash__pmd_mkhuge(pmd); 1092 } 1093 1094 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1095 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1096 unsigned long address, pmd_t *pmdp, 1097 pmd_t entry, int dirty); 1098 1099 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1100 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1101 unsigned long address, pmd_t *pmdp); 1102 1103 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1104 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1105 unsigned long addr, pmd_t *pmdp) 1106 { 1107 if (radix_enabled()) 1108 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1109 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1110 } 1111 1112 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1113 unsigned long address, pmd_t *pmdp) 1114 { 1115 if (radix_enabled()) 1116 return radix__pmdp_collapse_flush(vma, address, pmdp); 1117 return hash__pmdp_collapse_flush(vma, address, pmdp); 1118 } 1119 #define pmdp_collapse_flush pmdp_collapse_flush 1120 1121 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1122 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1123 pmd_t *pmdp, pgtable_t pgtable) 1124 { 1125 if (radix_enabled()) 1126 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1127 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1128 } 1129 1130 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1131 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1132 pmd_t *pmdp) 1133 { 1134 if (radix_enabled()) 1135 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1136 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1137 } 1138 1139 #define __HAVE_ARCH_PMDP_INVALIDATE 1140 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1141 pmd_t *pmdp); 1142 1143 #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE 1144 static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma, 1145 unsigned long address, pmd_t *pmdp) 1146 { 1147 if (radix_enabled()) 1148 return radix__pmdp_huge_split_prepare(vma, address, pmdp); 1149 return hash__pmdp_huge_split_prepare(vma, address, pmdp); 1150 } 1151 1152 #define pmd_move_must_withdraw pmd_move_must_withdraw 1153 struct spinlock; 1154 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1155 struct spinlock *old_pmd_ptl, 1156 struct vm_area_struct *vma) 1157 { 1158 if (radix_enabled()) 1159 return false; 1160 /* 1161 * Archs like ppc64 use pgtable to store per pmd 1162 * specific information. So when we switch the pmd, 1163 * we should also withdraw and deposit the pgtable 1164 */ 1165 return true; 1166 } 1167 1168 1169 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1170 static inline bool arch_needs_pgtable_deposit(void) 1171 { 1172 if (radix_enabled()) 1173 return false; 1174 return true; 1175 } 1176 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1177 1178 1179 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1180 { 1181 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1182 } 1183 1184 static inline int pmd_devmap(pmd_t pmd) 1185 { 1186 return pte_devmap(pmd_pte(pmd)); 1187 } 1188 1189 static inline int pud_devmap(pud_t pud) 1190 { 1191 return 0; 1192 } 1193 1194 static inline int pgd_devmap(pgd_t pgd) 1195 { 1196 return 0; 1197 } 1198 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1199 1200 static inline const int pud_pfn(pud_t pud) 1201 { 1202 /* 1203 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1204 * check so this should never be used. If it grows another user we 1205 * want to know about it. 1206 */ 1207 BUILD_BUG(); 1208 return 0; 1209 } 1210 1211 #endif /* __ASSEMBLY__ */ 1212 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1213