1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/5level-fixup.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x1000000000000000UL 36 #define _RPAGE_RSV2 0x0800000000000000UL 37 #define _RPAGE_RSV3 0x0400000000000000UL 38 #define _RPAGE_RSV4 0x0200000000000000UL 39 #define _RPAGE_RSV5 0x00040UL 40 41 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 43 /* 44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 46 * differentiate between two use a SW field when invalidating. 47 * 48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 49 * 50 * This is used only when _PAGE_PRESENT is cleared. 51 */ 52 #define _PAGE_INVALID _RPAGE_SW0 53 54 /* 55 * Top and bottom bits of RPN which can be used by hash 56 * translation mode, because we expect them to be zero 57 * otherwise. 58 */ 59 #define _RPAGE_RPN0 0x01000 60 #define _RPAGE_RPN1 0x02000 61 #define _RPAGE_RPN44 0x0100000000000000UL 62 #define _RPAGE_RPN43 0x0080000000000000UL 63 #define _RPAGE_RPN42 0x0040000000000000UL 64 #define _RPAGE_RPN41 0x0020000000000000UL 65 66 /* Max physical address bit as per radix table */ 67 #define _RPAGE_PA_MAX 57 68 69 /* 70 * Max physical address bit we will use for now. 71 * 72 * This is mostly a hardware limitation and for now Power9 has 73 * a 51 bit limit. 74 * 75 * This is different from the number of physical bit required to address 76 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 77 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 78 * number of sections we can support (SECTIONS_SHIFT). 79 * 80 * This is different from Radix page table limitation above and 81 * should always be less than that. The limit is done such that 82 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 83 * for hash linux page table specific bits. 84 * 85 * In order to be compatible with future hardware generations we keep 86 * some offsets and limit this for now to 53 87 */ 88 #define _PAGE_PA_MAX 53 89 90 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 91 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 92 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 93 #define __HAVE_ARCH_PTE_DEVMAP 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 120 _PAGE_RW | _PAGE_EXEC) 121 /* 122 * _PAGE_CHG_MASK masks of bits that are to be preserved across 123 * pgprot changes 124 */ 125 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 126 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 127 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 128 129 #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \ 130 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4) 131 /* 132 * We define 2 sets of base prot bits, one for basic pages (ie, 133 * cacheable kernel and user pages) and one for non cacheable 134 * pages. We always set _PAGE_COHERENT when SMP is enabled or 135 * the processor might need it for DMA coherency. 136 */ 137 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 138 #define _PAGE_BASE (_PAGE_BASE_NC) 139 140 /* Permission masks used to generate the __P and __S table, 141 * 142 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 143 * 144 * Write permissions imply read permissions for now (we could make write-only 145 * pages on BookE but we don't bother for now). Execute permission control is 146 * possible on platforms that define _PAGE_EXEC 147 */ 148 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 149 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 150 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 151 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 152 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 153 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 154 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 155 156 /* Permission masks used for kernel mappings */ 157 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 158 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 159 _PAGE_TOLERANT) 160 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 161 _PAGE_NON_IDEMPOTENT) 162 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 163 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 164 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 165 166 /* 167 * Protection used for kernel text. We want the debuggers to be able to 168 * set breakpoints anywhere, so don't write protect the kernel text 169 * on platforms where such control is possible. 170 */ 171 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 172 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 173 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 174 #else 175 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 176 #endif 177 178 /* Make modules code happy. We don't set RO yet */ 179 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 180 #define PAGE_AGP (PAGE_KERNEL_NC) 181 182 #ifndef __ASSEMBLY__ 183 /* 184 * page table defines 185 */ 186 extern unsigned long __pte_index_size; 187 extern unsigned long __pmd_index_size; 188 extern unsigned long __pud_index_size; 189 extern unsigned long __pgd_index_size; 190 extern unsigned long __pud_cache_index; 191 #define PTE_INDEX_SIZE __pte_index_size 192 #define PMD_INDEX_SIZE __pmd_index_size 193 #define PUD_INDEX_SIZE __pud_index_size 194 #define PGD_INDEX_SIZE __pgd_index_size 195 /* pmd table use page table fragments */ 196 #define PMD_CACHE_INDEX 0 197 #define PUD_CACHE_INDEX __pud_cache_index 198 /* 199 * Because of use of pte fragments and THP, size of page table 200 * are not always derived out of index size above. 201 */ 202 extern unsigned long __pte_table_size; 203 extern unsigned long __pmd_table_size; 204 extern unsigned long __pud_table_size; 205 extern unsigned long __pgd_table_size; 206 #define PTE_TABLE_SIZE __pte_table_size 207 #define PMD_TABLE_SIZE __pmd_table_size 208 #define PUD_TABLE_SIZE __pud_table_size 209 #define PGD_TABLE_SIZE __pgd_table_size 210 211 extern unsigned long __pmd_val_bits; 212 extern unsigned long __pud_val_bits; 213 extern unsigned long __pgd_val_bits; 214 #define PMD_VAL_BITS __pmd_val_bits 215 #define PUD_VAL_BITS __pud_val_bits 216 #define PGD_VAL_BITS __pgd_val_bits 217 218 extern unsigned long __pte_frag_nr; 219 #define PTE_FRAG_NR __pte_frag_nr 220 extern unsigned long __pte_frag_size_shift; 221 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 222 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 223 224 extern unsigned long __pmd_frag_nr; 225 #define PMD_FRAG_NR __pmd_frag_nr 226 extern unsigned long __pmd_frag_size_shift; 227 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 228 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 229 230 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 231 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 232 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 233 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 234 235 /* PMD_SHIFT determines what a second-level page table entry can map */ 236 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 237 #define PMD_SIZE (1UL << PMD_SHIFT) 238 #define PMD_MASK (~(PMD_SIZE-1)) 239 240 /* PUD_SHIFT determines what a third-level page table entry can map */ 241 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 242 #define PUD_SIZE (1UL << PUD_SHIFT) 243 #define PUD_MASK (~(PUD_SIZE-1)) 244 245 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 246 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 247 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 248 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 249 250 /* Bits to mask out from a PMD to get to the PTE page */ 251 #define PMD_MASKED_BITS 0xc0000000000000ffUL 252 /* Bits to mask out from a PUD to get to the PMD page */ 253 #define PUD_MASKED_BITS 0xc0000000000000ffUL 254 /* Bits to mask out from a PGD to get to the PUD page */ 255 #define PGD_MASKED_BITS 0xc0000000000000ffUL 256 257 /* 258 * Used as an indicator for rcu callback functions 259 */ 260 enum pgtable_index { 261 PTE_INDEX = 0, 262 PMD_INDEX, 263 PUD_INDEX, 264 PGD_INDEX, 265 /* 266 * Below are used with 4k page size and hugetlb 267 */ 268 HTLB_16M_INDEX, 269 HTLB_16G_INDEX, 270 }; 271 272 extern unsigned long __vmalloc_start; 273 extern unsigned long __vmalloc_end; 274 #define VMALLOC_START __vmalloc_start 275 #define VMALLOC_END __vmalloc_end 276 277 static inline unsigned int ioremap_max_order(void) 278 { 279 if (radix_enabled()) 280 return PUD_SHIFT; 281 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 282 } 283 #define IOREMAP_MAX_ORDER ioremap_max_order() 284 285 extern unsigned long __kernel_virt_start; 286 extern unsigned long __kernel_io_start; 287 extern unsigned long __kernel_io_end; 288 #define KERN_VIRT_START __kernel_virt_start 289 #define KERN_IO_START __kernel_io_start 290 #define KERN_IO_END __kernel_io_end 291 292 extern struct page *vmemmap; 293 extern unsigned long ioremap_bot; 294 extern unsigned long pci_io_base; 295 #endif /* __ASSEMBLY__ */ 296 297 #include <asm/book3s/64/hash.h> 298 #include <asm/book3s/64/radix.h> 299 300 #ifdef CONFIG_PPC_64K_PAGES 301 #include <asm/book3s/64/pgtable-64k.h> 302 #else 303 #include <asm/book3s/64/pgtable-4k.h> 304 #endif 305 306 #include <asm/barrier.h> 307 /* 308 * IO space itself carved into the PIO region (ISA and PHB IO space) and 309 * the ioremap space 310 * 311 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 312 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 313 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 314 */ 315 #define FULL_IO_SIZE 0x80000000ul 316 #define ISA_IO_BASE (KERN_IO_START) 317 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 318 #define PHB_IO_BASE (ISA_IO_END) 319 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 320 #define IOREMAP_BASE (PHB_IO_END) 321 #define IOREMAP_END (KERN_IO_END) 322 323 /* Advertise special mapping type for AGP */ 324 #define HAVE_PAGE_AGP 325 326 #ifndef __ASSEMBLY__ 327 328 /* 329 * This is the default implementation of various PTE accessors, it's 330 * used in all cases except Book3S with 64K pages where we have a 331 * concept of sub-pages 332 */ 333 #ifndef __real_pte 334 335 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 336 #define __rpte_to_pte(r) ((r).pte) 337 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 338 339 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 340 do { \ 341 index = 0; \ 342 shift = mmu_psize_defs[psize].shift; \ 343 344 #define pte_iterate_hashed_end() } while(0) 345 346 /* 347 * We expect this to be called only for user addresses or kernel virtual 348 * addresses other than the linear mapping. 349 */ 350 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 351 352 #endif /* __real_pte */ 353 354 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 355 pte_t *ptep, unsigned long clr, 356 unsigned long set, int huge) 357 { 358 if (radix_enabled()) 359 return radix__pte_update(mm, addr, ptep, clr, set, huge); 360 return hash__pte_update(mm, addr, ptep, clr, set, huge); 361 } 362 /* 363 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 364 * We currently remove entries from the hashtable regardless of whether 365 * the entry was young or dirty. 366 * 367 * We should be more intelligent about this but for the moment we override 368 * these functions and force a tlb flush unconditionally 369 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 370 * function for both hash and radix. 371 */ 372 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 373 unsigned long addr, pte_t *ptep) 374 { 375 unsigned long old; 376 377 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 378 return 0; 379 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 380 return (old & _PAGE_ACCESSED) != 0; 381 } 382 383 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 384 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 385 ({ \ 386 int __r; \ 387 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 388 __r; \ 389 }) 390 391 static inline int __pte_write(pte_t pte) 392 { 393 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 394 } 395 396 #ifdef CONFIG_NUMA_BALANCING 397 #define pte_savedwrite pte_savedwrite 398 static inline bool pte_savedwrite(pte_t pte) 399 { 400 /* 401 * Saved write ptes are prot none ptes that doesn't have 402 * privileged bit sit. We mark prot none as one which has 403 * present and pviliged bit set and RWX cleared. To mark 404 * protnone which used to have _PAGE_WRITE set we clear 405 * the privileged bit. 406 */ 407 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 408 } 409 #else 410 #define pte_savedwrite pte_savedwrite 411 static inline bool pte_savedwrite(pte_t pte) 412 { 413 return false; 414 } 415 #endif 416 417 static inline int pte_write(pte_t pte) 418 { 419 return __pte_write(pte) || pte_savedwrite(pte); 420 } 421 422 static inline int pte_read(pte_t pte) 423 { 424 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 425 } 426 427 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 428 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 429 pte_t *ptep) 430 { 431 if (__pte_write(*ptep)) 432 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 433 else if (unlikely(pte_savedwrite(*ptep))) 434 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 435 } 436 437 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 438 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 439 unsigned long addr, pte_t *ptep) 440 { 441 /* 442 * We should not find protnone for hugetlb, but this complete the 443 * interface. 444 */ 445 if (__pte_write(*ptep)) 446 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 447 else if (unlikely(pte_savedwrite(*ptep))) 448 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 449 } 450 451 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 452 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 453 unsigned long addr, pte_t *ptep) 454 { 455 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 456 return __pte(old); 457 } 458 459 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 460 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 461 unsigned long addr, 462 pte_t *ptep, int full) 463 { 464 if (full && radix_enabled()) { 465 /* 466 * We know that this is a full mm pte clear and 467 * hence can be sure there is no parallel set_pte. 468 */ 469 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 470 } 471 return ptep_get_and_clear(mm, addr, ptep); 472 } 473 474 475 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 476 pte_t * ptep) 477 { 478 pte_update(mm, addr, ptep, ~0UL, 0, 0); 479 } 480 481 static inline int pte_dirty(pte_t pte) 482 { 483 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 484 } 485 486 static inline int pte_young(pte_t pte) 487 { 488 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 489 } 490 491 static inline int pte_special(pte_t pte) 492 { 493 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 494 } 495 496 static inline bool pte_exec(pte_t pte) 497 { 498 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 499 } 500 501 502 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 503 static inline bool pte_soft_dirty(pte_t pte) 504 { 505 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 506 } 507 508 static inline pte_t pte_mksoft_dirty(pte_t pte) 509 { 510 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 511 } 512 513 static inline pte_t pte_clear_soft_dirty(pte_t pte) 514 { 515 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 516 } 517 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 518 519 #ifdef CONFIG_NUMA_BALANCING 520 static inline int pte_protnone(pte_t pte) 521 { 522 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 523 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 524 } 525 526 #define pte_mk_savedwrite pte_mk_savedwrite 527 static inline pte_t pte_mk_savedwrite(pte_t pte) 528 { 529 /* 530 * Used by Autonuma subsystem to preserve the write bit 531 * while marking the pte PROT_NONE. Only allow this 532 * on PROT_NONE pte 533 */ 534 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 535 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 536 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 537 } 538 539 #define pte_clear_savedwrite pte_clear_savedwrite 540 static inline pte_t pte_clear_savedwrite(pte_t pte) 541 { 542 /* 543 * Used by KSM subsystem to make a protnone pte readonly. 544 */ 545 VM_BUG_ON(!pte_protnone(pte)); 546 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 547 } 548 #else 549 #define pte_clear_savedwrite pte_clear_savedwrite 550 static inline pte_t pte_clear_savedwrite(pte_t pte) 551 { 552 VM_WARN_ON(1); 553 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 554 } 555 #endif /* CONFIG_NUMA_BALANCING */ 556 557 static inline int pte_present(pte_t pte) 558 { 559 /* 560 * A pte is considerent present if _PAGE_PRESENT is set. 561 * We also need to consider the pte present which is marked 562 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 563 * if we find _PAGE_PRESENT cleared. 564 */ 565 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)); 566 } 567 568 static inline bool pte_hw_valid(pte_t pte) 569 { 570 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 571 } 572 573 #ifdef CONFIG_PPC_MEM_KEYS 574 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 575 #else 576 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 577 { 578 return true; 579 } 580 #endif /* CONFIG_PPC_MEM_KEYS */ 581 582 static inline bool pte_user(pte_t pte) 583 { 584 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 585 } 586 587 #define pte_access_permitted pte_access_permitted 588 static inline bool pte_access_permitted(pte_t pte, bool write) 589 { 590 /* 591 * _PAGE_READ is needed for any access and will be 592 * cleared for PROT_NONE 593 */ 594 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 595 return false; 596 597 if (write && !pte_write(pte)) 598 return false; 599 600 return arch_pte_access_permitted(pte_val(pte), write, 0); 601 } 602 603 /* 604 * Conversion functions: convert a page and protection to a page entry, 605 * and a page entry and page directory to the page they refer to. 606 * 607 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 608 * long for now. 609 */ 610 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 611 { 612 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 613 pgprot_val(pgprot)); 614 } 615 616 static inline unsigned long pte_pfn(pte_t pte) 617 { 618 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 619 } 620 621 /* Generic modifiers for PTE bits */ 622 static inline pte_t pte_wrprotect(pte_t pte) 623 { 624 if (unlikely(pte_savedwrite(pte))) 625 return pte_clear_savedwrite(pte); 626 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 627 } 628 629 static inline pte_t pte_exprotect(pte_t pte) 630 { 631 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 632 } 633 634 static inline pte_t pte_mkclean(pte_t pte) 635 { 636 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 637 } 638 639 static inline pte_t pte_mkold(pte_t pte) 640 { 641 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 642 } 643 644 static inline pte_t pte_mkexec(pte_t pte) 645 { 646 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 647 } 648 649 static inline pte_t pte_mkpte(pte_t pte) 650 { 651 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 652 } 653 654 static inline pte_t pte_mkwrite(pte_t pte) 655 { 656 /* 657 * write implies read, hence set both 658 */ 659 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 660 } 661 662 static inline pte_t pte_mkdirty(pte_t pte) 663 { 664 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 665 } 666 667 static inline pte_t pte_mkyoung(pte_t pte) 668 { 669 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 670 } 671 672 static inline pte_t pte_mkspecial(pte_t pte) 673 { 674 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 675 } 676 677 static inline pte_t pte_mkhuge(pte_t pte) 678 { 679 return pte; 680 } 681 682 static inline pte_t pte_mkdevmap(pte_t pte) 683 { 684 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 685 } 686 687 static inline pte_t pte_mkprivileged(pte_t pte) 688 { 689 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 690 } 691 692 static inline pte_t pte_mkuser(pte_t pte) 693 { 694 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 695 } 696 697 /* 698 * This is potentially called with a pmd as the argument, in which case it's not 699 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 700 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 701 * use in page directory entries (ie. non-ptes). 702 */ 703 static inline int pte_devmap(pte_t pte) 704 { 705 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 706 707 return (pte_raw(pte) & mask) == mask; 708 } 709 710 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 711 { 712 /* FIXME!! check whether this need to be a conditional */ 713 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 714 cpu_to_be64(pgprot_val(newprot))); 715 } 716 717 /* Encode and de-code a swap entry */ 718 #define MAX_SWAPFILES_CHECK() do { \ 719 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 720 /* \ 721 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 722 * We filter HPTEFLAGS on set_pte. \ 723 */ \ 724 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 725 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 726 } while (0) 727 728 #define SWP_TYPE_BITS 5 729 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 730 & ((1UL << SWP_TYPE_BITS) - 1)) 731 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 732 #define __swp_entry(type, offset) ((swp_entry_t) { \ 733 ((type) << _PAGE_BIT_SWAP_TYPE) \ 734 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 735 /* 736 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 737 * swap type and offset we get from swap and convert that to pte to find a 738 * matching pte in linux page table. 739 * Clear bits not found in swap entries here. 740 */ 741 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 742 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 743 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 744 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 745 746 #ifdef CONFIG_MEM_SOFT_DIRTY 747 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 748 #else 749 #define _PAGE_SWP_SOFT_DIRTY 0UL 750 #endif /* CONFIG_MEM_SOFT_DIRTY */ 751 752 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 753 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 754 { 755 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 756 } 757 758 static inline bool pte_swp_soft_dirty(pte_t pte) 759 { 760 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 761 } 762 763 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 764 { 765 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 766 } 767 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 768 769 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 770 { 771 /* 772 * This check for _PAGE_RWX and _PAGE_PRESENT bits 773 */ 774 if (access & ~ptev) 775 return false; 776 /* 777 * This check for access to privilege space 778 */ 779 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 780 return false; 781 782 return true; 783 } 784 /* 785 * Generic functions with hash/radix callbacks 786 */ 787 788 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 789 pte_t *ptep, pte_t entry, 790 unsigned long address, 791 int psize) 792 { 793 if (radix_enabled()) 794 return radix__ptep_set_access_flags(vma, ptep, entry, 795 address, psize); 796 return hash__ptep_set_access_flags(ptep, entry); 797 } 798 799 #define __HAVE_ARCH_PTE_SAME 800 static inline int pte_same(pte_t pte_a, pte_t pte_b) 801 { 802 if (radix_enabled()) 803 return radix__pte_same(pte_a, pte_b); 804 return hash__pte_same(pte_a, pte_b); 805 } 806 807 static inline int pte_none(pte_t pte) 808 { 809 if (radix_enabled()) 810 return radix__pte_none(pte); 811 return hash__pte_none(pte); 812 } 813 814 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 815 pte_t *ptep, pte_t pte, int percpu) 816 { 817 if (radix_enabled()) 818 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 819 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 820 } 821 822 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 823 824 #define pgprot_noncached pgprot_noncached 825 static inline pgprot_t pgprot_noncached(pgprot_t prot) 826 { 827 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 828 _PAGE_NON_IDEMPOTENT); 829 } 830 831 #define pgprot_noncached_wc pgprot_noncached_wc 832 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 833 { 834 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 835 _PAGE_TOLERANT); 836 } 837 838 #define pgprot_cached pgprot_cached 839 static inline pgprot_t pgprot_cached(pgprot_t prot) 840 { 841 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 842 } 843 844 #define pgprot_writecombine pgprot_writecombine 845 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 846 { 847 return pgprot_noncached_wc(prot); 848 } 849 /* 850 * check a pte mapping have cache inhibited property 851 */ 852 static inline bool pte_ci(pte_t pte) 853 { 854 __be64 pte_v = pte_raw(pte); 855 856 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 857 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 858 return true; 859 return false; 860 } 861 862 static inline void pmd_clear(pmd_t *pmdp) 863 { 864 *pmdp = __pmd(0); 865 } 866 867 static inline int pmd_none(pmd_t pmd) 868 { 869 return !pmd_raw(pmd); 870 } 871 872 static inline int pmd_present(pmd_t pmd) 873 { 874 /* 875 * A pmd is considerent present if _PAGE_PRESENT is set. 876 * We also need to consider the pmd present which is marked 877 * invalid during a split. Hence we look for _PAGE_INVALID 878 * if we find _PAGE_PRESENT cleared. 879 */ 880 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 881 return true; 882 883 return false; 884 } 885 886 static inline int pmd_is_serializing(pmd_t pmd) 887 { 888 /* 889 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 890 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 891 * 892 * This condition may also occur when flushing a pmd while flushing 893 * it (see ptep_modify_prot_start), so callers must ensure this 894 * case is fine as well. 895 */ 896 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 897 cpu_to_be64(_PAGE_INVALID)) 898 return true; 899 900 return false; 901 } 902 903 static inline int pmd_bad(pmd_t pmd) 904 { 905 if (radix_enabled()) 906 return radix__pmd_bad(pmd); 907 return hash__pmd_bad(pmd); 908 } 909 910 static inline void pud_clear(pud_t *pudp) 911 { 912 *pudp = __pud(0); 913 } 914 915 static inline int pud_none(pud_t pud) 916 { 917 return !pud_raw(pud); 918 } 919 920 static inline int pud_present(pud_t pud) 921 { 922 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 923 } 924 925 extern struct page *pud_page(pud_t pud); 926 extern struct page *pmd_page(pmd_t pmd); 927 static inline pte_t pud_pte(pud_t pud) 928 { 929 return __pte_raw(pud_raw(pud)); 930 } 931 932 static inline pud_t pte_pud(pte_t pte) 933 { 934 return __pud_raw(pte_raw(pte)); 935 } 936 #define pud_write(pud) pte_write(pud_pte(pud)) 937 938 static inline int pud_bad(pud_t pud) 939 { 940 if (radix_enabled()) 941 return radix__pud_bad(pud); 942 return hash__pud_bad(pud); 943 } 944 945 #define pud_access_permitted pud_access_permitted 946 static inline bool pud_access_permitted(pud_t pud, bool write) 947 { 948 return pte_access_permitted(pud_pte(pud), write); 949 } 950 951 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 952 953 static inline void pgd_clear(pgd_t *pgdp) 954 { 955 *pgdp = __pgd(0); 956 } 957 958 static inline int pgd_none(pgd_t pgd) 959 { 960 return !pgd_raw(pgd); 961 } 962 963 static inline int pgd_present(pgd_t pgd) 964 { 965 return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT)); 966 } 967 968 static inline pte_t pgd_pte(pgd_t pgd) 969 { 970 return __pte_raw(pgd_raw(pgd)); 971 } 972 973 static inline pgd_t pte_pgd(pte_t pte) 974 { 975 return __pgd_raw(pte_raw(pte)); 976 } 977 978 static inline int pgd_bad(pgd_t pgd) 979 { 980 if (radix_enabled()) 981 return radix__pgd_bad(pgd); 982 return hash__pgd_bad(pgd); 983 } 984 985 #define pgd_access_permitted pgd_access_permitted 986 static inline bool pgd_access_permitted(pgd_t pgd, bool write) 987 { 988 return pte_access_permitted(pgd_pte(pgd), write); 989 } 990 991 extern struct page *pgd_page(pgd_t pgd); 992 993 /* Pointers in the page table tree are physical addresses */ 994 #define __pgtable_ptr_val(ptr) __pa(ptr) 995 996 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 997 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 998 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 999 1000 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 1001 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 1002 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 1003 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 1004 1005 /* 1006 * Find an entry in a page-table-directory. We combine the address region 1007 * (the high order N bits) and the pgd portion of the address. 1008 */ 1009 1010 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1011 1012 #define pud_offset(pgdp, addr) \ 1013 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 1014 #define pmd_offset(pudp,addr) \ 1015 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 1016 #define pte_offset_kernel(dir,addr) \ 1017 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 1018 1019 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 1020 1021 static inline void pte_unmap(pte_t *pte) { } 1022 1023 /* to find an entry in a kernel page-table-directory */ 1024 /* This now only contains the vmalloc pages */ 1025 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1026 1027 #define pte_ERROR(e) \ 1028 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1029 #define pmd_ERROR(e) \ 1030 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1031 #define pud_ERROR(e) \ 1032 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1033 #define pgd_ERROR(e) \ 1034 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1035 1036 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1037 { 1038 if (radix_enabled()) { 1039 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1040 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1041 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1042 #endif 1043 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1044 } 1045 return hash__map_kernel_page(ea, pa, prot); 1046 } 1047 1048 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1049 unsigned long page_size, 1050 unsigned long phys) 1051 { 1052 if (radix_enabled()) 1053 return radix__vmemmap_create_mapping(start, page_size, phys); 1054 return hash__vmemmap_create_mapping(start, page_size, phys); 1055 } 1056 1057 #ifdef CONFIG_MEMORY_HOTPLUG 1058 static inline void vmemmap_remove_mapping(unsigned long start, 1059 unsigned long page_size) 1060 { 1061 if (radix_enabled()) 1062 return radix__vmemmap_remove_mapping(start, page_size); 1063 return hash__vmemmap_remove_mapping(start, page_size); 1064 } 1065 #endif 1066 1067 static inline pte_t pmd_pte(pmd_t pmd) 1068 { 1069 return __pte_raw(pmd_raw(pmd)); 1070 } 1071 1072 static inline pmd_t pte_pmd(pte_t pte) 1073 { 1074 return __pmd_raw(pte_raw(pte)); 1075 } 1076 1077 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1078 { 1079 return (pte_t *)pmd; 1080 } 1081 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1082 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1083 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1084 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1085 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1086 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1087 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1088 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1089 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1090 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1091 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1092 1093 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1094 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1095 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1096 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1097 1098 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1099 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1100 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1101 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1102 #endif 1103 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1104 1105 #ifdef CONFIG_NUMA_BALANCING 1106 static inline int pmd_protnone(pmd_t pmd) 1107 { 1108 return pte_protnone(pmd_pte(pmd)); 1109 } 1110 #endif /* CONFIG_NUMA_BALANCING */ 1111 1112 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1113 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1114 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1115 1116 #define pmd_access_permitted pmd_access_permitted 1117 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1118 { 1119 /* 1120 * pmdp_invalidate sets this combination (which is not caught by 1121 * !pte_present() check in pte_access_permitted), to prevent 1122 * lock-free lookups, as part of the serialize_against_pte_lookup() 1123 * synchronisation. 1124 * 1125 * This also catches the case where the PTE's hardware PRESENT bit is 1126 * cleared while TLB is flushed, which is suboptimal but should not 1127 * be frequent. 1128 */ 1129 if (pmd_is_serializing(pmd)) 1130 return false; 1131 1132 return pte_access_permitted(pmd_pte(pmd), write); 1133 } 1134 1135 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1136 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1137 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1138 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1139 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1140 pmd_t *pmdp, pmd_t pmd); 1141 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1142 pmd_t *pmd); 1143 extern int hash__has_transparent_hugepage(void); 1144 static inline int has_transparent_hugepage(void) 1145 { 1146 if (radix_enabled()) 1147 return radix__has_transparent_hugepage(); 1148 return hash__has_transparent_hugepage(); 1149 } 1150 #define has_transparent_hugepage has_transparent_hugepage 1151 1152 static inline unsigned long 1153 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1154 unsigned long clr, unsigned long set) 1155 { 1156 if (radix_enabled()) 1157 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1158 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1159 } 1160 1161 /* 1162 * returns true for pmd migration entries, THP, devmap, hugetlb 1163 * But compile time dependent on THP config 1164 */ 1165 static inline int pmd_large(pmd_t pmd) 1166 { 1167 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1168 } 1169 1170 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1171 { 1172 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1173 } 1174 /* 1175 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1176 * the below will work for radix too 1177 */ 1178 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1179 unsigned long addr, pmd_t *pmdp) 1180 { 1181 unsigned long old; 1182 1183 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1184 return 0; 1185 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1186 return ((old & _PAGE_ACCESSED) != 0); 1187 } 1188 1189 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1190 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1191 pmd_t *pmdp) 1192 { 1193 if (__pmd_write((*pmdp))) 1194 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1195 else if (unlikely(pmd_savedwrite(*pmdp))) 1196 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1197 } 1198 1199 /* 1200 * Only returns true for a THP. False for pmd migration entry. 1201 * We also need to return true when we come across a pte that 1202 * in between a thp split. While splitting THP, we mark the pmd 1203 * invalid (pmdp_invalidate()) before we set it with pte page 1204 * address. A pmd_trans_huge() check against a pmd entry during that time 1205 * should return true. 1206 * We should not call this on a hugetlb entry. We should check for HugeTLB 1207 * entry using vma->vm_flags 1208 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1209 */ 1210 static inline int pmd_trans_huge(pmd_t pmd) 1211 { 1212 if (!pmd_present(pmd)) 1213 return false; 1214 1215 if (radix_enabled()) 1216 return radix__pmd_trans_huge(pmd); 1217 return hash__pmd_trans_huge(pmd); 1218 } 1219 1220 #define __HAVE_ARCH_PMD_SAME 1221 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1222 { 1223 if (radix_enabled()) 1224 return radix__pmd_same(pmd_a, pmd_b); 1225 return hash__pmd_same(pmd_a, pmd_b); 1226 } 1227 1228 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1229 { 1230 if (radix_enabled()) 1231 return radix__pmd_mkhuge(pmd); 1232 return hash__pmd_mkhuge(pmd); 1233 } 1234 1235 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1236 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1237 unsigned long address, pmd_t *pmdp, 1238 pmd_t entry, int dirty); 1239 1240 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1241 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1242 unsigned long address, pmd_t *pmdp); 1243 1244 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1245 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1246 unsigned long addr, pmd_t *pmdp) 1247 { 1248 if (radix_enabled()) 1249 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1250 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1251 } 1252 1253 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1254 unsigned long address, pmd_t *pmdp) 1255 { 1256 if (radix_enabled()) 1257 return radix__pmdp_collapse_flush(vma, address, pmdp); 1258 return hash__pmdp_collapse_flush(vma, address, pmdp); 1259 } 1260 #define pmdp_collapse_flush pmdp_collapse_flush 1261 1262 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1263 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1264 pmd_t *pmdp, pgtable_t pgtable) 1265 { 1266 if (radix_enabled()) 1267 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1268 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1269 } 1270 1271 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1272 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1273 pmd_t *pmdp) 1274 { 1275 if (radix_enabled()) 1276 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1277 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1278 } 1279 1280 #define __HAVE_ARCH_PMDP_INVALIDATE 1281 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1282 pmd_t *pmdp); 1283 1284 #define pmd_move_must_withdraw pmd_move_must_withdraw 1285 struct spinlock; 1286 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1287 struct spinlock *old_pmd_ptl, 1288 struct vm_area_struct *vma); 1289 /* 1290 * Hash translation mode use the deposited table to store hash pte 1291 * slot information. 1292 */ 1293 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1294 static inline bool arch_needs_pgtable_deposit(void) 1295 { 1296 if (radix_enabled()) 1297 return false; 1298 return true; 1299 } 1300 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1301 1302 1303 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1304 { 1305 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1306 } 1307 1308 static inline int pmd_devmap(pmd_t pmd) 1309 { 1310 return pte_devmap(pmd_pte(pmd)); 1311 } 1312 1313 static inline int pud_devmap(pud_t pud) 1314 { 1315 return 0; 1316 } 1317 1318 static inline int pgd_devmap(pgd_t pgd) 1319 { 1320 return 0; 1321 } 1322 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1323 1324 static inline int pud_pfn(pud_t pud) 1325 { 1326 /* 1327 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1328 * check so this should never be used. If it grows another user we 1329 * want to know about it. 1330 */ 1331 BUILD_BUG(); 1332 return 0; 1333 } 1334 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1335 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1336 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1337 pte_t *, pte_t, pte_t); 1338 1339 /* 1340 * Returns true for a R -> RW upgrade of pte 1341 */ 1342 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1343 { 1344 if (!(old_val & _PAGE_READ)) 1345 return false; 1346 1347 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1348 return true; 1349 1350 return false; 1351 } 1352 1353 /* 1354 * Like pmd_huge() and pmd_large(), but works regardless of config options 1355 */ 1356 #define pmd_is_leaf pmd_is_leaf 1357 static inline bool pmd_is_leaf(pmd_t pmd) 1358 { 1359 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1360 } 1361 1362 #define pud_is_leaf pud_is_leaf 1363 static inline bool pud_is_leaf(pud_t pud) 1364 { 1365 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1366 } 1367 1368 #define pgd_is_leaf pgd_is_leaf 1369 static inline bool pgd_is_leaf(pgd_t pgd) 1370 { 1371 return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PTE)); 1372 } 1373 1374 #endif /* __ASSEMBLY__ */ 1375 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1376