1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/5level-fixup.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x1000000000000000UL 36 #define _RPAGE_RSV2 0x0800000000000000UL 37 #define _RPAGE_RSV3 0x0400000000000000UL 38 #define _RPAGE_RSV4 0x0200000000000000UL 39 #define _RPAGE_RSV5 0x00040UL 40 41 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 43 /* 44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 46 * differentiate between two use a SW field when invalidating. 47 * 48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 49 * 50 * This is used only when _PAGE_PRESENT is cleared. 51 */ 52 #define _PAGE_INVALID _RPAGE_SW0 53 54 /* 55 * Top and bottom bits of RPN which can be used by hash 56 * translation mode, because we expect them to be zero 57 * otherwise. 58 */ 59 #define _RPAGE_RPN0 0x01000 60 #define _RPAGE_RPN1 0x02000 61 #define _RPAGE_RPN44 0x0100000000000000UL 62 #define _RPAGE_RPN43 0x0080000000000000UL 63 #define _RPAGE_RPN42 0x0040000000000000UL 64 #define _RPAGE_RPN41 0x0020000000000000UL 65 66 /* Max physical address bit as per radix table */ 67 #define _RPAGE_PA_MAX 57 68 69 /* 70 * Max physical address bit we will use for now. 71 * 72 * This is mostly a hardware limitation and for now Power9 has 73 * a 51 bit limit. 74 * 75 * This is different from the number of physical bit required to address 76 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 77 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 78 * number of sections we can support (SECTIONS_SHIFT). 79 * 80 * This is different from Radix page table limitation above and 81 * should always be less than that. The limit is done such that 82 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 83 * for hash linux page table specific bits. 84 * 85 * In order to be compatible with future hardware generations we keep 86 * some offsets and limit this for now to 53 87 */ 88 #define _PAGE_PA_MAX 53 89 90 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 91 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 92 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 93 #define __HAVE_ARCH_PTE_DEVMAP 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 120 _PAGE_RW | _PAGE_EXEC) 121 /* 122 * _PAGE_CHG_MASK masks of bits that are to be preserved across 123 * pgprot changes 124 */ 125 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 126 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 127 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 128 129 #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \ 130 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4) 131 /* 132 * We define 2 sets of base prot bits, one for basic pages (ie, 133 * cacheable kernel and user pages) and one for non cacheable 134 * pages. We always set _PAGE_COHERENT when SMP is enabled or 135 * the processor might need it for DMA coherency. 136 */ 137 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 138 #define _PAGE_BASE (_PAGE_BASE_NC) 139 140 /* Permission masks used to generate the __P and __S table, 141 * 142 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 143 * 144 * Write permissions imply read permissions for now (we could make write-only 145 * pages on BookE but we don't bother for now). Execute permission control is 146 * possible on platforms that define _PAGE_EXEC 147 */ 148 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 149 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 150 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 151 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 152 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 153 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 154 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 155 156 /* Permission masks used for kernel mappings */ 157 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 158 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 159 _PAGE_TOLERANT) 160 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 161 _PAGE_NON_IDEMPOTENT) 162 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 163 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 164 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 165 166 /* 167 * Protection used for kernel text. We want the debuggers to be able to 168 * set breakpoints anywhere, so don't write protect the kernel text 169 * on platforms where such control is possible. 170 */ 171 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 172 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 173 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 174 #else 175 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 176 #endif 177 178 /* Make modules code happy. We don't set RO yet */ 179 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 180 #define PAGE_AGP (PAGE_KERNEL_NC) 181 182 #ifndef __ASSEMBLY__ 183 /* 184 * page table defines 185 */ 186 extern unsigned long __pte_index_size; 187 extern unsigned long __pmd_index_size; 188 extern unsigned long __pud_index_size; 189 extern unsigned long __pgd_index_size; 190 extern unsigned long __pud_cache_index; 191 #define PTE_INDEX_SIZE __pte_index_size 192 #define PMD_INDEX_SIZE __pmd_index_size 193 #define PUD_INDEX_SIZE __pud_index_size 194 #define PGD_INDEX_SIZE __pgd_index_size 195 /* pmd table use page table fragments */ 196 #define PMD_CACHE_INDEX 0 197 #define PUD_CACHE_INDEX __pud_cache_index 198 /* 199 * Because of use of pte fragments and THP, size of page table 200 * are not always derived out of index size above. 201 */ 202 extern unsigned long __pte_table_size; 203 extern unsigned long __pmd_table_size; 204 extern unsigned long __pud_table_size; 205 extern unsigned long __pgd_table_size; 206 #define PTE_TABLE_SIZE __pte_table_size 207 #define PMD_TABLE_SIZE __pmd_table_size 208 #define PUD_TABLE_SIZE __pud_table_size 209 #define PGD_TABLE_SIZE __pgd_table_size 210 211 extern unsigned long __pmd_val_bits; 212 extern unsigned long __pud_val_bits; 213 extern unsigned long __pgd_val_bits; 214 #define PMD_VAL_BITS __pmd_val_bits 215 #define PUD_VAL_BITS __pud_val_bits 216 #define PGD_VAL_BITS __pgd_val_bits 217 218 extern unsigned long __pte_frag_nr; 219 #define PTE_FRAG_NR __pte_frag_nr 220 extern unsigned long __pte_frag_size_shift; 221 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 222 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 223 224 extern unsigned long __pmd_frag_nr; 225 #define PMD_FRAG_NR __pmd_frag_nr 226 extern unsigned long __pmd_frag_size_shift; 227 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 228 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 229 230 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 231 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 232 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 233 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 234 235 /* PMD_SHIFT determines what a second-level page table entry can map */ 236 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 237 #define PMD_SIZE (1UL << PMD_SHIFT) 238 #define PMD_MASK (~(PMD_SIZE-1)) 239 240 /* PUD_SHIFT determines what a third-level page table entry can map */ 241 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 242 #define PUD_SIZE (1UL << PUD_SHIFT) 243 #define PUD_MASK (~(PUD_SIZE-1)) 244 245 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 246 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 247 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 248 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 249 250 /* Bits to mask out from a PMD to get to the PTE page */ 251 #define PMD_MASKED_BITS 0xc0000000000000ffUL 252 /* Bits to mask out from a PUD to get to the PMD page */ 253 #define PUD_MASKED_BITS 0xc0000000000000ffUL 254 /* Bits to mask out from a PGD to get to the PUD page */ 255 #define PGD_MASKED_BITS 0xc0000000000000ffUL 256 257 /* 258 * Used as an indicator for rcu callback functions 259 */ 260 enum pgtable_index { 261 PTE_INDEX = 0, 262 PMD_INDEX, 263 PUD_INDEX, 264 PGD_INDEX, 265 /* 266 * Below are used with 4k page size and hugetlb 267 */ 268 HTLB_16M_INDEX, 269 HTLB_16G_INDEX, 270 }; 271 272 extern unsigned long __vmalloc_start; 273 extern unsigned long __vmalloc_end; 274 #define VMALLOC_START __vmalloc_start 275 #define VMALLOC_END __vmalloc_end 276 277 static inline unsigned int ioremap_max_order(void) 278 { 279 if (radix_enabled()) 280 return PUD_SHIFT; 281 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 282 } 283 #define IOREMAP_MAX_ORDER ioremap_max_order() 284 285 extern unsigned long __kernel_virt_start; 286 extern unsigned long __kernel_virt_size; 287 extern unsigned long __kernel_io_start; 288 extern unsigned long __kernel_io_end; 289 #define KERN_VIRT_START __kernel_virt_start 290 #define KERN_IO_START __kernel_io_start 291 #define KERN_IO_END __kernel_io_end 292 293 extern struct page *vmemmap; 294 extern unsigned long ioremap_bot; 295 extern unsigned long pci_io_base; 296 #endif /* __ASSEMBLY__ */ 297 298 #include <asm/book3s/64/hash.h> 299 #include <asm/book3s/64/radix.h> 300 301 #ifdef CONFIG_PPC_64K_PAGES 302 #include <asm/book3s/64/pgtable-64k.h> 303 #else 304 #include <asm/book3s/64/pgtable-4k.h> 305 #endif 306 307 #include <asm/barrier.h> 308 /* 309 * IO space itself carved into the PIO region (ISA and PHB IO space) and 310 * the ioremap space 311 * 312 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 313 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 314 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 315 */ 316 #define FULL_IO_SIZE 0x80000000ul 317 #define ISA_IO_BASE (KERN_IO_START) 318 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 319 #define PHB_IO_BASE (ISA_IO_END) 320 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 321 #define IOREMAP_BASE (PHB_IO_END) 322 #define IOREMAP_END (KERN_IO_END) 323 324 /* Advertise special mapping type for AGP */ 325 #define HAVE_PAGE_AGP 326 327 #ifndef __ASSEMBLY__ 328 329 /* 330 * This is the default implementation of various PTE accessors, it's 331 * used in all cases except Book3S with 64K pages where we have a 332 * concept of sub-pages 333 */ 334 #ifndef __real_pte 335 336 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 337 #define __rpte_to_pte(r) ((r).pte) 338 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 339 340 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 341 do { \ 342 index = 0; \ 343 shift = mmu_psize_defs[psize].shift; \ 344 345 #define pte_iterate_hashed_end() } while(0) 346 347 /* 348 * We expect this to be called only for user addresses or kernel virtual 349 * addresses other than the linear mapping. 350 */ 351 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 352 353 #endif /* __real_pte */ 354 355 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 356 pte_t *ptep, unsigned long clr, 357 unsigned long set, int huge) 358 { 359 if (radix_enabled()) 360 return radix__pte_update(mm, addr, ptep, clr, set, huge); 361 return hash__pte_update(mm, addr, ptep, clr, set, huge); 362 } 363 /* 364 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 365 * We currently remove entries from the hashtable regardless of whether 366 * the entry was young or dirty. 367 * 368 * We should be more intelligent about this but for the moment we override 369 * these functions and force a tlb flush unconditionally 370 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 371 * function for both hash and radix. 372 */ 373 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 374 unsigned long addr, pte_t *ptep) 375 { 376 unsigned long old; 377 378 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 379 return 0; 380 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 381 return (old & _PAGE_ACCESSED) != 0; 382 } 383 384 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 385 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 386 ({ \ 387 int __r; \ 388 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 389 __r; \ 390 }) 391 392 static inline int __pte_write(pte_t pte) 393 { 394 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 395 } 396 397 #ifdef CONFIG_NUMA_BALANCING 398 #define pte_savedwrite pte_savedwrite 399 static inline bool pte_savedwrite(pte_t pte) 400 { 401 /* 402 * Saved write ptes are prot none ptes that doesn't have 403 * privileged bit sit. We mark prot none as one which has 404 * present and pviliged bit set and RWX cleared. To mark 405 * protnone which used to have _PAGE_WRITE set we clear 406 * the privileged bit. 407 */ 408 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 409 } 410 #else 411 #define pte_savedwrite pte_savedwrite 412 static inline bool pte_savedwrite(pte_t pte) 413 { 414 return false; 415 } 416 #endif 417 418 static inline int pte_write(pte_t pte) 419 { 420 return __pte_write(pte) || pte_savedwrite(pte); 421 } 422 423 static inline int pte_read(pte_t pte) 424 { 425 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 426 } 427 428 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 429 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 430 pte_t *ptep) 431 { 432 if (__pte_write(*ptep)) 433 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 434 else if (unlikely(pte_savedwrite(*ptep))) 435 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 436 } 437 438 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 439 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 440 unsigned long addr, pte_t *ptep) 441 { 442 /* 443 * We should not find protnone for hugetlb, but this complete the 444 * interface. 445 */ 446 if (__pte_write(*ptep)) 447 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 448 else if (unlikely(pte_savedwrite(*ptep))) 449 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 450 } 451 452 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 453 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 454 unsigned long addr, pte_t *ptep) 455 { 456 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 457 return __pte(old); 458 } 459 460 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 461 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 462 unsigned long addr, 463 pte_t *ptep, int full) 464 { 465 if (full && radix_enabled()) { 466 /* 467 * We know that this is a full mm pte clear and 468 * hence can be sure there is no parallel set_pte. 469 */ 470 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 471 } 472 return ptep_get_and_clear(mm, addr, ptep); 473 } 474 475 476 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 477 pte_t * ptep) 478 { 479 pte_update(mm, addr, ptep, ~0UL, 0, 0); 480 } 481 482 static inline int pte_dirty(pte_t pte) 483 { 484 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 485 } 486 487 static inline int pte_young(pte_t pte) 488 { 489 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 490 } 491 492 static inline int pte_special(pte_t pte) 493 { 494 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 495 } 496 497 static inline bool pte_exec(pte_t pte) 498 { 499 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 500 } 501 502 503 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 504 static inline bool pte_soft_dirty(pte_t pte) 505 { 506 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 507 } 508 509 static inline pte_t pte_mksoft_dirty(pte_t pte) 510 { 511 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 512 } 513 514 static inline pte_t pte_clear_soft_dirty(pte_t pte) 515 { 516 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 517 } 518 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 519 520 #ifdef CONFIG_NUMA_BALANCING 521 static inline int pte_protnone(pte_t pte) 522 { 523 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 524 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 525 } 526 527 #define pte_mk_savedwrite pte_mk_savedwrite 528 static inline pte_t pte_mk_savedwrite(pte_t pte) 529 { 530 /* 531 * Used by Autonuma subsystem to preserve the write bit 532 * while marking the pte PROT_NONE. Only allow this 533 * on PROT_NONE pte 534 */ 535 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 536 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 537 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 538 } 539 540 #define pte_clear_savedwrite pte_clear_savedwrite 541 static inline pte_t pte_clear_savedwrite(pte_t pte) 542 { 543 /* 544 * Used by KSM subsystem to make a protnone pte readonly. 545 */ 546 VM_BUG_ON(!pte_protnone(pte)); 547 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 548 } 549 #else 550 #define pte_clear_savedwrite pte_clear_savedwrite 551 static inline pte_t pte_clear_savedwrite(pte_t pte) 552 { 553 VM_WARN_ON(1); 554 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 555 } 556 #endif /* CONFIG_NUMA_BALANCING */ 557 558 static inline int pte_present(pte_t pte) 559 { 560 /* 561 * A pte is considerent present if _PAGE_PRESENT is set. 562 * We also need to consider the pte present which is marked 563 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 564 * if we find _PAGE_PRESENT cleared. 565 */ 566 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)); 567 } 568 569 static inline bool pte_hw_valid(pte_t pte) 570 { 571 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 572 } 573 574 #ifdef CONFIG_PPC_MEM_KEYS 575 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 576 #else 577 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 578 { 579 return true; 580 } 581 #endif /* CONFIG_PPC_MEM_KEYS */ 582 583 static inline bool pte_user(pte_t pte) 584 { 585 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 586 } 587 588 #define pte_access_permitted pte_access_permitted 589 static inline bool pte_access_permitted(pte_t pte, bool write) 590 { 591 /* 592 * _PAGE_READ is needed for any access and will be 593 * cleared for PROT_NONE 594 */ 595 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 596 return false; 597 598 if (write && !pte_write(pte)) 599 return false; 600 601 return arch_pte_access_permitted(pte_val(pte), write, 0); 602 } 603 604 /* 605 * Conversion functions: convert a page and protection to a page entry, 606 * and a page entry and page directory to the page they refer to. 607 * 608 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 609 * long for now. 610 */ 611 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 612 { 613 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 614 pgprot_val(pgprot)); 615 } 616 617 static inline unsigned long pte_pfn(pte_t pte) 618 { 619 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 620 } 621 622 /* Generic modifiers for PTE bits */ 623 static inline pte_t pte_wrprotect(pte_t pte) 624 { 625 if (unlikely(pte_savedwrite(pte))) 626 return pte_clear_savedwrite(pte); 627 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 628 } 629 630 static inline pte_t pte_exprotect(pte_t pte) 631 { 632 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 633 } 634 635 static inline pte_t pte_mkclean(pte_t pte) 636 { 637 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 638 } 639 640 static inline pte_t pte_mkold(pte_t pte) 641 { 642 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 643 } 644 645 static inline pte_t pte_mkexec(pte_t pte) 646 { 647 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 648 } 649 650 static inline pte_t pte_mkpte(pte_t pte) 651 { 652 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 653 } 654 655 static inline pte_t pte_mkwrite(pte_t pte) 656 { 657 /* 658 * write implies read, hence set both 659 */ 660 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 661 } 662 663 static inline pte_t pte_mkdirty(pte_t pte) 664 { 665 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 666 } 667 668 static inline pte_t pte_mkyoung(pte_t pte) 669 { 670 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 671 } 672 673 static inline pte_t pte_mkspecial(pte_t pte) 674 { 675 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 676 } 677 678 static inline pte_t pte_mkhuge(pte_t pte) 679 { 680 return pte; 681 } 682 683 static inline pte_t pte_mkdevmap(pte_t pte) 684 { 685 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 686 } 687 688 static inline pte_t pte_mkprivileged(pte_t pte) 689 { 690 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 691 } 692 693 static inline pte_t pte_mkuser(pte_t pte) 694 { 695 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 696 } 697 698 /* 699 * This is potentially called with a pmd as the argument, in which case it's not 700 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 701 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 702 * use in page directory entries (ie. non-ptes). 703 */ 704 static inline int pte_devmap(pte_t pte) 705 { 706 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 707 708 return (pte_raw(pte) & mask) == mask; 709 } 710 711 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 712 { 713 /* FIXME!! check whether this need to be a conditional */ 714 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 715 cpu_to_be64(pgprot_val(newprot))); 716 } 717 718 /* Encode and de-code a swap entry */ 719 #define MAX_SWAPFILES_CHECK() do { \ 720 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 721 /* \ 722 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 723 * We filter HPTEFLAGS on set_pte. \ 724 */ \ 725 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 726 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 727 } while (0) 728 729 #define SWP_TYPE_BITS 5 730 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 731 & ((1UL << SWP_TYPE_BITS) - 1)) 732 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 733 #define __swp_entry(type, offset) ((swp_entry_t) { \ 734 ((type) << _PAGE_BIT_SWAP_TYPE) \ 735 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 736 /* 737 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 738 * swap type and offset we get from swap and convert that to pte to find a 739 * matching pte in linux page table. 740 * Clear bits not found in swap entries here. 741 */ 742 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 743 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 744 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 745 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 746 747 #ifdef CONFIG_MEM_SOFT_DIRTY 748 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 749 #else 750 #define _PAGE_SWP_SOFT_DIRTY 0UL 751 #endif /* CONFIG_MEM_SOFT_DIRTY */ 752 753 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 754 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 755 { 756 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 757 } 758 759 static inline bool pte_swp_soft_dirty(pte_t pte) 760 { 761 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 762 } 763 764 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 765 { 766 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 767 } 768 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 769 770 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 771 { 772 /* 773 * This check for _PAGE_RWX and _PAGE_PRESENT bits 774 */ 775 if (access & ~ptev) 776 return false; 777 /* 778 * This check for access to privilege space 779 */ 780 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 781 return false; 782 783 return true; 784 } 785 /* 786 * Generic functions with hash/radix callbacks 787 */ 788 789 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 790 pte_t *ptep, pte_t entry, 791 unsigned long address, 792 int psize) 793 { 794 if (radix_enabled()) 795 return radix__ptep_set_access_flags(vma, ptep, entry, 796 address, psize); 797 return hash__ptep_set_access_flags(ptep, entry); 798 } 799 800 #define __HAVE_ARCH_PTE_SAME 801 static inline int pte_same(pte_t pte_a, pte_t pte_b) 802 { 803 if (radix_enabled()) 804 return radix__pte_same(pte_a, pte_b); 805 return hash__pte_same(pte_a, pte_b); 806 } 807 808 static inline int pte_none(pte_t pte) 809 { 810 if (radix_enabled()) 811 return radix__pte_none(pte); 812 return hash__pte_none(pte); 813 } 814 815 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 816 pte_t *ptep, pte_t pte, int percpu) 817 { 818 if (radix_enabled()) 819 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 820 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 821 } 822 823 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 824 825 #define pgprot_noncached pgprot_noncached 826 static inline pgprot_t pgprot_noncached(pgprot_t prot) 827 { 828 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 829 _PAGE_NON_IDEMPOTENT); 830 } 831 832 #define pgprot_noncached_wc pgprot_noncached_wc 833 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 834 { 835 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 836 _PAGE_TOLERANT); 837 } 838 839 #define pgprot_cached pgprot_cached 840 static inline pgprot_t pgprot_cached(pgprot_t prot) 841 { 842 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 843 } 844 845 #define pgprot_writecombine pgprot_writecombine 846 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 847 { 848 return pgprot_noncached_wc(prot); 849 } 850 /* 851 * check a pte mapping have cache inhibited property 852 */ 853 static inline bool pte_ci(pte_t pte) 854 { 855 __be64 pte_v = pte_raw(pte); 856 857 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 858 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 859 return true; 860 return false; 861 } 862 863 static inline void pmd_clear(pmd_t *pmdp) 864 { 865 *pmdp = __pmd(0); 866 } 867 868 static inline int pmd_none(pmd_t pmd) 869 { 870 return !pmd_raw(pmd); 871 } 872 873 static inline int pmd_present(pmd_t pmd) 874 { 875 /* 876 * A pmd is considerent present if _PAGE_PRESENT is set. 877 * We also need to consider the pmd present which is marked 878 * invalid during a split. Hence we look for _PAGE_INVALID 879 * if we find _PAGE_PRESENT cleared. 880 */ 881 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 882 return true; 883 884 return false; 885 } 886 887 static inline int pmd_is_serializing(pmd_t pmd) 888 { 889 /* 890 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 891 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 892 * 893 * This condition may also occur when flushing a pmd while flushing 894 * it (see ptep_modify_prot_start), so callers must ensure this 895 * case is fine as well. 896 */ 897 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 898 cpu_to_be64(_PAGE_INVALID)) 899 return true; 900 901 return false; 902 } 903 904 static inline int pmd_bad(pmd_t pmd) 905 { 906 if (radix_enabled()) 907 return radix__pmd_bad(pmd); 908 return hash__pmd_bad(pmd); 909 } 910 911 static inline void pud_clear(pud_t *pudp) 912 { 913 *pudp = __pud(0); 914 } 915 916 static inline int pud_none(pud_t pud) 917 { 918 return !pud_raw(pud); 919 } 920 921 static inline int pud_present(pud_t pud) 922 { 923 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 924 } 925 926 extern struct page *pud_page(pud_t pud); 927 extern struct page *pmd_page(pmd_t pmd); 928 static inline pte_t pud_pte(pud_t pud) 929 { 930 return __pte_raw(pud_raw(pud)); 931 } 932 933 static inline pud_t pte_pud(pte_t pte) 934 { 935 return __pud_raw(pte_raw(pte)); 936 } 937 #define pud_write(pud) pte_write(pud_pte(pud)) 938 939 static inline int pud_bad(pud_t pud) 940 { 941 if (radix_enabled()) 942 return radix__pud_bad(pud); 943 return hash__pud_bad(pud); 944 } 945 946 #define pud_access_permitted pud_access_permitted 947 static inline bool pud_access_permitted(pud_t pud, bool write) 948 { 949 return pte_access_permitted(pud_pte(pud), write); 950 } 951 952 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 953 954 static inline void pgd_clear(pgd_t *pgdp) 955 { 956 *pgdp = __pgd(0); 957 } 958 959 static inline int pgd_none(pgd_t pgd) 960 { 961 return !pgd_raw(pgd); 962 } 963 964 static inline int pgd_present(pgd_t pgd) 965 { 966 return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT)); 967 } 968 969 static inline pte_t pgd_pte(pgd_t pgd) 970 { 971 return __pte_raw(pgd_raw(pgd)); 972 } 973 974 static inline pgd_t pte_pgd(pte_t pte) 975 { 976 return __pgd_raw(pte_raw(pte)); 977 } 978 979 static inline int pgd_bad(pgd_t pgd) 980 { 981 if (radix_enabled()) 982 return radix__pgd_bad(pgd); 983 return hash__pgd_bad(pgd); 984 } 985 986 #define pgd_access_permitted pgd_access_permitted 987 static inline bool pgd_access_permitted(pgd_t pgd, bool write) 988 { 989 return pte_access_permitted(pgd_pte(pgd), write); 990 } 991 992 extern struct page *pgd_page(pgd_t pgd); 993 994 /* Pointers in the page table tree are physical addresses */ 995 #define __pgtable_ptr_val(ptr) __pa(ptr) 996 997 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 998 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 999 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 1000 1001 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 1002 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 1003 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 1004 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 1005 1006 /* 1007 * Find an entry in a page-table-directory. We combine the address region 1008 * (the high order N bits) and the pgd portion of the address. 1009 */ 1010 1011 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1012 1013 #define pud_offset(pgdp, addr) \ 1014 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 1015 #define pmd_offset(pudp,addr) \ 1016 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 1017 #define pte_offset_kernel(dir,addr) \ 1018 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 1019 1020 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 1021 1022 static inline void pte_unmap(pte_t *pte) { } 1023 1024 /* to find an entry in a kernel page-table-directory */ 1025 /* This now only contains the vmalloc pages */ 1026 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1027 1028 #define pte_ERROR(e) \ 1029 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1030 #define pmd_ERROR(e) \ 1031 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1032 #define pud_ERROR(e) \ 1033 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1034 #define pgd_ERROR(e) \ 1035 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1036 1037 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1038 { 1039 if (radix_enabled()) { 1040 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1041 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1042 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1043 #endif 1044 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1045 } 1046 return hash__map_kernel_page(ea, pa, prot); 1047 } 1048 1049 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1050 unsigned long page_size, 1051 unsigned long phys) 1052 { 1053 if (radix_enabled()) 1054 return radix__vmemmap_create_mapping(start, page_size, phys); 1055 return hash__vmemmap_create_mapping(start, page_size, phys); 1056 } 1057 1058 #ifdef CONFIG_MEMORY_HOTPLUG 1059 static inline void vmemmap_remove_mapping(unsigned long start, 1060 unsigned long page_size) 1061 { 1062 if (radix_enabled()) 1063 return radix__vmemmap_remove_mapping(start, page_size); 1064 return hash__vmemmap_remove_mapping(start, page_size); 1065 } 1066 #endif 1067 1068 static inline pte_t pmd_pte(pmd_t pmd) 1069 { 1070 return __pte_raw(pmd_raw(pmd)); 1071 } 1072 1073 static inline pmd_t pte_pmd(pte_t pte) 1074 { 1075 return __pmd_raw(pte_raw(pte)); 1076 } 1077 1078 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1079 { 1080 return (pte_t *)pmd; 1081 } 1082 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1083 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1084 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1085 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1086 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1087 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1088 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1089 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1090 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1091 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1092 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1093 1094 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1095 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1096 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1097 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1098 1099 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1100 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1101 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1102 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1103 #endif 1104 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1105 1106 #ifdef CONFIG_NUMA_BALANCING 1107 static inline int pmd_protnone(pmd_t pmd) 1108 { 1109 return pte_protnone(pmd_pte(pmd)); 1110 } 1111 #endif /* CONFIG_NUMA_BALANCING */ 1112 1113 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1114 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1115 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1116 1117 #define pmd_access_permitted pmd_access_permitted 1118 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1119 { 1120 /* 1121 * pmdp_invalidate sets this combination (which is not caught by 1122 * !pte_present() check in pte_access_permitted), to prevent 1123 * lock-free lookups, as part of the serialize_against_pte_lookup() 1124 * synchronisation. 1125 * 1126 * This also catches the case where the PTE's hardware PRESENT bit is 1127 * cleared while TLB is flushed, which is suboptimal but should not 1128 * be frequent. 1129 */ 1130 if (pmd_is_serializing(pmd)) 1131 return false; 1132 1133 return pte_access_permitted(pmd_pte(pmd), write); 1134 } 1135 1136 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1137 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1138 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1139 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1140 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1141 pmd_t *pmdp, pmd_t pmd); 1142 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1143 pmd_t *pmd); 1144 extern int hash__has_transparent_hugepage(void); 1145 static inline int has_transparent_hugepage(void) 1146 { 1147 if (radix_enabled()) 1148 return radix__has_transparent_hugepage(); 1149 return hash__has_transparent_hugepage(); 1150 } 1151 #define has_transparent_hugepage has_transparent_hugepage 1152 1153 static inline unsigned long 1154 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1155 unsigned long clr, unsigned long set) 1156 { 1157 if (radix_enabled()) 1158 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1159 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1160 } 1161 1162 /* 1163 * returns true for pmd migration entries, THP, devmap, hugetlb 1164 * But compile time dependent on THP config 1165 */ 1166 static inline int pmd_large(pmd_t pmd) 1167 { 1168 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1169 } 1170 1171 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1172 { 1173 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1174 } 1175 /* 1176 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1177 * the below will work for radix too 1178 */ 1179 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1180 unsigned long addr, pmd_t *pmdp) 1181 { 1182 unsigned long old; 1183 1184 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1185 return 0; 1186 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1187 return ((old & _PAGE_ACCESSED) != 0); 1188 } 1189 1190 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1191 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1192 pmd_t *pmdp) 1193 { 1194 if (__pmd_write((*pmdp))) 1195 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1196 else if (unlikely(pmd_savedwrite(*pmdp))) 1197 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1198 } 1199 1200 /* 1201 * Only returns true for a THP. False for pmd migration entry. 1202 * We also need to return true when we come across a pte that 1203 * in between a thp split. While splitting THP, we mark the pmd 1204 * invalid (pmdp_invalidate()) before we set it with pte page 1205 * address. A pmd_trans_huge() check against a pmd entry during that time 1206 * should return true. 1207 * We should not call this on a hugetlb entry. We should check for HugeTLB 1208 * entry using vma->vm_flags 1209 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1210 */ 1211 static inline int pmd_trans_huge(pmd_t pmd) 1212 { 1213 if (!pmd_present(pmd)) 1214 return false; 1215 1216 if (radix_enabled()) 1217 return radix__pmd_trans_huge(pmd); 1218 return hash__pmd_trans_huge(pmd); 1219 } 1220 1221 #define __HAVE_ARCH_PMD_SAME 1222 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1223 { 1224 if (radix_enabled()) 1225 return radix__pmd_same(pmd_a, pmd_b); 1226 return hash__pmd_same(pmd_a, pmd_b); 1227 } 1228 1229 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1230 { 1231 if (radix_enabled()) 1232 return radix__pmd_mkhuge(pmd); 1233 return hash__pmd_mkhuge(pmd); 1234 } 1235 1236 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1237 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1238 unsigned long address, pmd_t *pmdp, 1239 pmd_t entry, int dirty); 1240 1241 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1242 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1243 unsigned long address, pmd_t *pmdp); 1244 1245 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1246 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1247 unsigned long addr, pmd_t *pmdp) 1248 { 1249 if (radix_enabled()) 1250 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1251 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1252 } 1253 1254 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1255 unsigned long address, pmd_t *pmdp) 1256 { 1257 if (radix_enabled()) 1258 return radix__pmdp_collapse_flush(vma, address, pmdp); 1259 return hash__pmdp_collapse_flush(vma, address, pmdp); 1260 } 1261 #define pmdp_collapse_flush pmdp_collapse_flush 1262 1263 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1264 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1265 pmd_t *pmdp, pgtable_t pgtable) 1266 { 1267 if (radix_enabled()) 1268 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1269 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1270 } 1271 1272 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1273 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1274 pmd_t *pmdp) 1275 { 1276 if (radix_enabled()) 1277 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1278 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1279 } 1280 1281 #define __HAVE_ARCH_PMDP_INVALIDATE 1282 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1283 pmd_t *pmdp); 1284 1285 #define pmd_move_must_withdraw pmd_move_must_withdraw 1286 struct spinlock; 1287 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1288 struct spinlock *old_pmd_ptl, 1289 struct vm_area_struct *vma); 1290 /* 1291 * Hash translation mode use the deposited table to store hash pte 1292 * slot information. 1293 */ 1294 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1295 static inline bool arch_needs_pgtable_deposit(void) 1296 { 1297 if (radix_enabled()) 1298 return false; 1299 return true; 1300 } 1301 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1302 1303 1304 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1305 { 1306 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1307 } 1308 1309 static inline int pmd_devmap(pmd_t pmd) 1310 { 1311 return pte_devmap(pmd_pte(pmd)); 1312 } 1313 1314 static inline int pud_devmap(pud_t pud) 1315 { 1316 return 0; 1317 } 1318 1319 static inline int pgd_devmap(pgd_t pgd) 1320 { 1321 return 0; 1322 } 1323 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1324 1325 static inline int pud_pfn(pud_t pud) 1326 { 1327 /* 1328 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1329 * check so this should never be used. If it grows another user we 1330 * want to know about it. 1331 */ 1332 BUILD_BUG(); 1333 return 0; 1334 } 1335 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1336 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1337 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1338 pte_t *, pte_t, pte_t); 1339 1340 /* 1341 * Returns true for a R -> RW upgrade of pte 1342 */ 1343 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1344 { 1345 if (!(old_val & _PAGE_READ)) 1346 return false; 1347 1348 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1349 return true; 1350 1351 return false; 1352 } 1353 1354 #endif /* __ASSEMBLY__ */ 1355 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1356