1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x00040UL 36 37 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 38 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 39 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 40 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 41 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 42 43 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 44 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 45 /* 46 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 47 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 48 * differentiate between two use a SW field when invalidating. 49 * 50 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 51 * 52 * This is used only when _PAGE_PRESENT is cleared. 53 */ 54 #define _PAGE_INVALID _RPAGE_SW0 55 56 /* 57 * Top and bottom bits of RPN which can be used by hash 58 * translation mode, because we expect them to be zero 59 * otherwise. 60 */ 61 #define _RPAGE_RPN0 0x01000 62 #define _RPAGE_RPN1 0x02000 63 #define _RPAGE_RPN43 0x0080000000000000UL 64 #define _RPAGE_RPN42 0x0040000000000000UL 65 #define _RPAGE_RPN41 0x0020000000000000UL 66 67 /* Max physical address bit as per radix table */ 68 #define _RPAGE_PA_MAX 56 69 70 /* 71 * Max physical address bit we will use for now. 72 * 73 * This is mostly a hardware limitation and for now Power9 has 74 * a 51 bit limit. 75 * 76 * This is different from the number of physical bit required to address 77 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 78 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 79 * number of sections we can support (SECTIONS_SHIFT). 80 * 81 * This is different from Radix page table limitation above and 82 * should always be less than that. The limit is done such that 83 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 84 * for hash linux page table specific bits. 85 * 86 * In order to be compatible with future hardware generations we keep 87 * some offsets and limit this for now to 53 88 */ 89 #define _PAGE_PA_MAX 53 90 91 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 92 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 93 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 120 _PAGE_RW | _PAGE_EXEC) 121 /* 122 * _PAGE_CHG_MASK masks of bits that are to be preserved across 123 * pgprot changes 124 */ 125 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 126 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 127 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 128 129 /* 130 * We define 2 sets of base prot bits, one for basic pages (ie, 131 * cacheable kernel and user pages) and one for non cacheable 132 * pages. We always set _PAGE_COHERENT when SMP is enabled or 133 * the processor might need it for DMA coherency. 134 */ 135 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 136 #define _PAGE_BASE (_PAGE_BASE_NC) 137 138 /* Permission masks used to generate the __P and __S table, 139 * 140 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 141 * 142 * Write permissions imply read permissions for now (we could make write-only 143 * pages on BookE but we don't bother for now). Execute permission control is 144 * possible on platforms that define _PAGE_EXEC 145 */ 146 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 147 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 148 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 149 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 150 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 151 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 152 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 153 154 /* Permission masks used for kernel mappings */ 155 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 156 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 157 _PAGE_TOLERANT) 158 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 159 _PAGE_NON_IDEMPOTENT) 160 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 161 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 162 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 163 164 /* 165 * Protection used for kernel text. We want the debuggers to be able to 166 * set breakpoints anywhere, so don't write protect the kernel text 167 * on platforms where such control is possible. 168 */ 169 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 170 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 171 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 172 #else 173 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 174 #endif 175 176 /* Make modules code happy. We don't set RO yet */ 177 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 178 #define PAGE_AGP (PAGE_KERNEL_NC) 179 180 #ifndef __ASSEMBLY__ 181 /* 182 * page table defines 183 */ 184 extern unsigned long __pte_index_size; 185 extern unsigned long __pmd_index_size; 186 extern unsigned long __pud_index_size; 187 extern unsigned long __pgd_index_size; 188 extern unsigned long __pud_cache_index; 189 #define PTE_INDEX_SIZE __pte_index_size 190 #define PMD_INDEX_SIZE __pmd_index_size 191 #define PUD_INDEX_SIZE __pud_index_size 192 #define PGD_INDEX_SIZE __pgd_index_size 193 /* pmd table use page table fragments */ 194 #define PMD_CACHE_INDEX 0 195 #define PUD_CACHE_INDEX __pud_cache_index 196 /* 197 * Because of use of pte fragments and THP, size of page table 198 * are not always derived out of index size above. 199 */ 200 extern unsigned long __pte_table_size; 201 extern unsigned long __pmd_table_size; 202 extern unsigned long __pud_table_size; 203 extern unsigned long __pgd_table_size; 204 #define PTE_TABLE_SIZE __pte_table_size 205 #define PMD_TABLE_SIZE __pmd_table_size 206 #define PUD_TABLE_SIZE __pud_table_size 207 #define PGD_TABLE_SIZE __pgd_table_size 208 209 extern unsigned long __pmd_val_bits; 210 extern unsigned long __pud_val_bits; 211 extern unsigned long __pgd_val_bits; 212 #define PMD_VAL_BITS __pmd_val_bits 213 #define PUD_VAL_BITS __pud_val_bits 214 #define PGD_VAL_BITS __pgd_val_bits 215 216 extern unsigned long __pte_frag_nr; 217 #define PTE_FRAG_NR __pte_frag_nr 218 extern unsigned long __pte_frag_size_shift; 219 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 220 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 221 222 extern unsigned long __pmd_frag_nr; 223 #define PMD_FRAG_NR __pmd_frag_nr 224 extern unsigned long __pmd_frag_size_shift; 225 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 226 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 227 228 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 229 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 230 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 231 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 232 233 /* PMD_SHIFT determines what a second-level page table entry can map */ 234 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 235 #define PMD_SIZE (1UL << PMD_SHIFT) 236 #define PMD_MASK (~(PMD_SIZE-1)) 237 238 /* PUD_SHIFT determines what a third-level page table entry can map */ 239 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 240 #define PUD_SIZE (1UL << PUD_SHIFT) 241 #define PUD_MASK (~(PUD_SIZE-1)) 242 243 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 244 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 245 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 246 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 247 248 /* Bits to mask out from a PMD to get to the PTE page */ 249 #define PMD_MASKED_BITS 0xc0000000000000ffUL 250 /* Bits to mask out from a PUD to get to the PMD page */ 251 #define PUD_MASKED_BITS 0xc0000000000000ffUL 252 /* Bits to mask out from a PGD to get to the PUD page */ 253 #define P4D_MASKED_BITS 0xc0000000000000ffUL 254 255 /* 256 * Used as an indicator for rcu callback functions 257 */ 258 enum pgtable_index { 259 PTE_INDEX = 0, 260 PMD_INDEX, 261 PUD_INDEX, 262 PGD_INDEX, 263 /* 264 * Below are used with 4k page size and hugetlb 265 */ 266 HTLB_16M_INDEX, 267 HTLB_16G_INDEX, 268 }; 269 270 extern unsigned long __vmalloc_start; 271 extern unsigned long __vmalloc_end; 272 #define VMALLOC_START __vmalloc_start 273 #define VMALLOC_END __vmalloc_end 274 275 static inline unsigned int ioremap_max_order(void) 276 { 277 if (radix_enabled()) 278 return PUD_SHIFT; 279 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 280 } 281 #define IOREMAP_MAX_ORDER ioremap_max_order() 282 283 extern unsigned long __kernel_virt_start; 284 extern unsigned long __kernel_io_start; 285 extern unsigned long __kernel_io_end; 286 #define KERN_VIRT_START __kernel_virt_start 287 #define KERN_IO_START __kernel_io_start 288 #define KERN_IO_END __kernel_io_end 289 290 extern struct page *vmemmap; 291 extern unsigned long pci_io_base; 292 #endif /* __ASSEMBLY__ */ 293 294 #include <asm/book3s/64/hash.h> 295 #include <asm/book3s/64/radix.h> 296 297 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 298 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 299 #else 300 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 301 #endif 302 303 304 #ifdef CONFIG_PPC_64K_PAGES 305 #include <asm/book3s/64/pgtable-64k.h> 306 #else 307 #include <asm/book3s/64/pgtable-4k.h> 308 #endif 309 310 #include <asm/barrier.h> 311 /* 312 * IO space itself carved into the PIO region (ISA and PHB IO space) and 313 * the ioremap space 314 * 315 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 316 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 317 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 318 */ 319 #define FULL_IO_SIZE 0x80000000ul 320 #define ISA_IO_BASE (KERN_IO_START) 321 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 322 #define PHB_IO_BASE (ISA_IO_END) 323 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 324 #define IOREMAP_BASE (PHB_IO_END) 325 #define IOREMAP_START (ioremap_bot) 326 #define IOREMAP_END (KERN_IO_END) 327 328 /* Advertise special mapping type for AGP */ 329 #define HAVE_PAGE_AGP 330 331 #ifndef __ASSEMBLY__ 332 333 /* 334 * This is the default implementation of various PTE accessors, it's 335 * used in all cases except Book3S with 64K pages where we have a 336 * concept of sub-pages 337 */ 338 #ifndef __real_pte 339 340 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 341 #define __rpte_to_pte(r) ((r).pte) 342 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 343 344 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 345 do { \ 346 index = 0; \ 347 shift = mmu_psize_defs[psize].shift; \ 348 349 #define pte_iterate_hashed_end() } while(0) 350 351 /* 352 * We expect this to be called only for user addresses or kernel virtual 353 * addresses other than the linear mapping. 354 */ 355 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 356 357 #endif /* __real_pte */ 358 359 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 360 pte_t *ptep, unsigned long clr, 361 unsigned long set, int huge) 362 { 363 if (radix_enabled()) 364 return radix__pte_update(mm, addr, ptep, clr, set, huge); 365 return hash__pte_update(mm, addr, ptep, clr, set, huge); 366 } 367 /* 368 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 369 * We currently remove entries from the hashtable regardless of whether 370 * the entry was young or dirty. 371 * 372 * We should be more intelligent about this but for the moment we override 373 * these functions and force a tlb flush unconditionally 374 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 375 * function for both hash and radix. 376 */ 377 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 378 unsigned long addr, pte_t *ptep) 379 { 380 unsigned long old; 381 382 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 383 return 0; 384 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 385 return (old & _PAGE_ACCESSED) != 0; 386 } 387 388 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 389 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 390 ({ \ 391 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 392 }) 393 394 /* 395 * On Book3S CPUs, clearing the accessed bit without a TLB flush 396 * doesn't cause data corruption. [ It could cause incorrect 397 * page aging and the (mistaken) reclaim of hot pages, but the 398 * chance of that should be relatively low. ] 399 * 400 * So as a performance optimization don't flush the TLB when 401 * clearing the accessed bit, it will eventually be flushed by 402 * a context switch or a VM operation anyway. [ In the rare 403 * event of it not getting flushed for a long time the delay 404 * shouldn't really matter because there's no real memory 405 * pressure for swapout to react to. ] 406 */ 407 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 408 #define ptep_clear_flush_young ptep_test_and_clear_young 409 410 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 411 #define pmdp_clear_flush_young pmdp_test_and_clear_young 412 413 static inline int __pte_write(pte_t pte) 414 { 415 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 416 } 417 418 #ifdef CONFIG_NUMA_BALANCING 419 #define pte_savedwrite pte_savedwrite 420 static inline bool pte_savedwrite(pte_t pte) 421 { 422 /* 423 * Saved write ptes are prot none ptes that doesn't have 424 * privileged bit sit. We mark prot none as one which has 425 * present and pviliged bit set and RWX cleared. To mark 426 * protnone which used to have _PAGE_WRITE set we clear 427 * the privileged bit. 428 */ 429 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 430 } 431 #else 432 #define pte_savedwrite pte_savedwrite 433 static inline bool pte_savedwrite(pte_t pte) 434 { 435 return false; 436 } 437 #endif 438 439 static inline int pte_write(pte_t pte) 440 { 441 return __pte_write(pte) || pte_savedwrite(pte); 442 } 443 444 static inline int pte_read(pte_t pte) 445 { 446 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 447 } 448 449 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 450 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 451 pte_t *ptep) 452 { 453 if (__pte_write(*ptep)) 454 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 455 else if (unlikely(pte_savedwrite(*ptep))) 456 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 457 } 458 459 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 460 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 461 unsigned long addr, pte_t *ptep) 462 { 463 /* 464 * We should not find protnone for hugetlb, but this complete the 465 * interface. 466 */ 467 if (__pte_write(*ptep)) 468 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 469 else if (unlikely(pte_savedwrite(*ptep))) 470 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 471 } 472 473 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 474 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 475 unsigned long addr, pte_t *ptep) 476 { 477 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 478 return __pte(old); 479 } 480 481 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 482 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 483 unsigned long addr, 484 pte_t *ptep, int full) 485 { 486 if (full && radix_enabled()) { 487 /* 488 * We know that this is a full mm pte clear and 489 * hence can be sure there is no parallel set_pte. 490 */ 491 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 492 } 493 return ptep_get_and_clear(mm, addr, ptep); 494 } 495 496 497 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 498 pte_t * ptep) 499 { 500 pte_update(mm, addr, ptep, ~0UL, 0, 0); 501 } 502 503 static inline int pte_dirty(pte_t pte) 504 { 505 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 506 } 507 508 static inline int pte_young(pte_t pte) 509 { 510 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 511 } 512 513 static inline int pte_special(pte_t pte) 514 { 515 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 516 } 517 518 static inline bool pte_exec(pte_t pte) 519 { 520 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 521 } 522 523 524 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 525 static inline bool pte_soft_dirty(pte_t pte) 526 { 527 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 528 } 529 530 static inline pte_t pte_mksoft_dirty(pte_t pte) 531 { 532 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 533 } 534 535 static inline pte_t pte_clear_soft_dirty(pte_t pte) 536 { 537 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 538 } 539 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 540 541 #ifdef CONFIG_NUMA_BALANCING 542 static inline int pte_protnone(pte_t pte) 543 { 544 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 545 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 546 } 547 548 #define pte_mk_savedwrite pte_mk_savedwrite 549 static inline pte_t pte_mk_savedwrite(pte_t pte) 550 { 551 /* 552 * Used by Autonuma subsystem to preserve the write bit 553 * while marking the pte PROT_NONE. Only allow this 554 * on PROT_NONE pte 555 */ 556 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 557 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 558 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 559 } 560 561 #define pte_clear_savedwrite pte_clear_savedwrite 562 static inline pte_t pte_clear_savedwrite(pte_t pte) 563 { 564 /* 565 * Used by KSM subsystem to make a protnone pte readonly. 566 */ 567 VM_BUG_ON(!pte_protnone(pte)); 568 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 569 } 570 #else 571 #define pte_clear_savedwrite pte_clear_savedwrite 572 static inline pte_t pte_clear_savedwrite(pte_t pte) 573 { 574 VM_WARN_ON(1); 575 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 576 } 577 #endif /* CONFIG_NUMA_BALANCING */ 578 579 static inline bool pte_hw_valid(pte_t pte) 580 { 581 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 582 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 583 } 584 585 static inline int pte_present(pte_t pte) 586 { 587 /* 588 * A pte is considerent present if _PAGE_PRESENT is set. 589 * We also need to consider the pte present which is marked 590 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 591 * if we find _PAGE_PRESENT cleared. 592 */ 593 594 if (pte_hw_valid(pte)) 595 return true; 596 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 597 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 598 } 599 600 #ifdef CONFIG_PPC_MEM_KEYS 601 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 602 #else 603 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 604 { 605 return true; 606 } 607 #endif /* CONFIG_PPC_MEM_KEYS */ 608 609 static inline bool pte_user(pte_t pte) 610 { 611 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 612 } 613 614 #define pte_access_permitted pte_access_permitted 615 static inline bool pte_access_permitted(pte_t pte, bool write) 616 { 617 /* 618 * _PAGE_READ is needed for any access and will be 619 * cleared for PROT_NONE 620 */ 621 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 622 return false; 623 624 if (write && !pte_write(pte)) 625 return false; 626 627 return arch_pte_access_permitted(pte_val(pte), write, 0); 628 } 629 630 /* 631 * Conversion functions: convert a page and protection to a page entry, 632 * and a page entry and page directory to the page they refer to. 633 * 634 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 635 * long for now. 636 */ 637 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 638 { 639 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 640 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 641 642 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 643 } 644 645 static inline unsigned long pte_pfn(pte_t pte) 646 { 647 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 648 } 649 650 /* Generic modifiers for PTE bits */ 651 static inline pte_t pte_wrprotect(pte_t pte) 652 { 653 if (unlikely(pte_savedwrite(pte))) 654 return pte_clear_savedwrite(pte); 655 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 656 } 657 658 static inline pte_t pte_exprotect(pte_t pte) 659 { 660 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 661 } 662 663 static inline pte_t pte_mkclean(pte_t pte) 664 { 665 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 666 } 667 668 static inline pte_t pte_mkold(pte_t pte) 669 { 670 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 671 } 672 673 static inline pte_t pte_mkexec(pte_t pte) 674 { 675 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 676 } 677 678 static inline pte_t pte_mkwrite(pte_t pte) 679 { 680 /* 681 * write implies read, hence set both 682 */ 683 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 684 } 685 686 static inline pte_t pte_mkdirty(pte_t pte) 687 { 688 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 689 } 690 691 static inline pte_t pte_mkyoung(pte_t pte) 692 { 693 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 694 } 695 696 static inline pte_t pte_mkspecial(pte_t pte) 697 { 698 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 699 } 700 701 static inline pte_t pte_mkhuge(pte_t pte) 702 { 703 return pte; 704 } 705 706 static inline pte_t pte_mkdevmap(pte_t pte) 707 { 708 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 709 } 710 711 static inline pte_t pte_mkprivileged(pte_t pte) 712 { 713 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 714 } 715 716 static inline pte_t pte_mkuser(pte_t pte) 717 { 718 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 719 } 720 721 /* 722 * This is potentially called with a pmd as the argument, in which case it's not 723 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 724 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 725 * use in page directory entries (ie. non-ptes). 726 */ 727 static inline int pte_devmap(pte_t pte) 728 { 729 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 730 731 return (pte_raw(pte) & mask) == mask; 732 } 733 734 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 735 { 736 /* FIXME!! check whether this need to be a conditional */ 737 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 738 cpu_to_be64(pgprot_val(newprot))); 739 } 740 741 /* Encode and de-code a swap entry */ 742 #define MAX_SWAPFILES_CHECK() do { \ 743 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 744 /* \ 745 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 746 * We filter HPTEFLAGS on set_pte. \ 747 */ \ 748 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 749 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 750 } while (0) 751 752 #define SWP_TYPE_BITS 5 753 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 754 & ((1UL << SWP_TYPE_BITS) - 1)) 755 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 756 #define __swp_entry(type, offset) ((swp_entry_t) { \ 757 ((type) << _PAGE_BIT_SWAP_TYPE) \ 758 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 759 /* 760 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 761 * swap type and offset we get from swap and convert that to pte to find a 762 * matching pte in linux page table. 763 * Clear bits not found in swap entries here. 764 */ 765 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 766 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 767 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 768 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 769 770 #ifdef CONFIG_MEM_SOFT_DIRTY 771 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 772 #else 773 #define _PAGE_SWP_SOFT_DIRTY 0UL 774 #endif /* CONFIG_MEM_SOFT_DIRTY */ 775 776 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 777 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 778 { 779 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 780 } 781 782 static inline bool pte_swp_soft_dirty(pte_t pte) 783 { 784 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 785 } 786 787 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 788 { 789 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 790 } 791 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 792 793 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 794 { 795 /* 796 * This check for _PAGE_RWX and _PAGE_PRESENT bits 797 */ 798 if (access & ~ptev) 799 return false; 800 /* 801 * This check for access to privilege space 802 */ 803 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 804 return false; 805 806 return true; 807 } 808 /* 809 * Generic functions with hash/radix callbacks 810 */ 811 812 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 813 pte_t *ptep, pte_t entry, 814 unsigned long address, 815 int psize) 816 { 817 if (radix_enabled()) 818 return radix__ptep_set_access_flags(vma, ptep, entry, 819 address, psize); 820 return hash__ptep_set_access_flags(ptep, entry); 821 } 822 823 #define __HAVE_ARCH_PTE_SAME 824 static inline int pte_same(pte_t pte_a, pte_t pte_b) 825 { 826 if (radix_enabled()) 827 return radix__pte_same(pte_a, pte_b); 828 return hash__pte_same(pte_a, pte_b); 829 } 830 831 static inline int pte_none(pte_t pte) 832 { 833 if (radix_enabled()) 834 return radix__pte_none(pte); 835 return hash__pte_none(pte); 836 } 837 838 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 839 pte_t *ptep, pte_t pte, int percpu) 840 { 841 842 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 843 /* 844 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 845 * in all the callers. 846 */ 847 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 848 849 if (radix_enabled()) 850 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 851 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 852 } 853 854 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 855 856 #define pgprot_noncached pgprot_noncached 857 static inline pgprot_t pgprot_noncached(pgprot_t prot) 858 { 859 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 860 _PAGE_NON_IDEMPOTENT); 861 } 862 863 #define pgprot_noncached_wc pgprot_noncached_wc 864 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 865 { 866 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 867 _PAGE_TOLERANT); 868 } 869 870 #define pgprot_cached pgprot_cached 871 static inline pgprot_t pgprot_cached(pgprot_t prot) 872 { 873 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 874 } 875 876 #define pgprot_writecombine pgprot_writecombine 877 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 878 { 879 return pgprot_noncached_wc(prot); 880 } 881 /* 882 * check a pte mapping have cache inhibited property 883 */ 884 static inline bool pte_ci(pte_t pte) 885 { 886 __be64 pte_v = pte_raw(pte); 887 888 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 889 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 890 return true; 891 return false; 892 } 893 894 static inline void pmd_clear(pmd_t *pmdp) 895 { 896 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 897 /* 898 * Don't use this if we can possibly have a hash page table 899 * entry mapping this. 900 */ 901 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 902 } 903 *pmdp = __pmd(0); 904 } 905 906 static inline int pmd_none(pmd_t pmd) 907 { 908 return !pmd_raw(pmd); 909 } 910 911 static inline int pmd_present(pmd_t pmd) 912 { 913 /* 914 * A pmd is considerent present if _PAGE_PRESENT is set. 915 * We also need to consider the pmd present which is marked 916 * invalid during a split. Hence we look for _PAGE_INVALID 917 * if we find _PAGE_PRESENT cleared. 918 */ 919 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 920 return true; 921 922 return false; 923 } 924 925 static inline int pmd_is_serializing(pmd_t pmd) 926 { 927 /* 928 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 929 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 930 * 931 * This condition may also occur when flushing a pmd while flushing 932 * it (see ptep_modify_prot_start), so callers must ensure this 933 * case is fine as well. 934 */ 935 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 936 cpu_to_be64(_PAGE_INVALID)) 937 return true; 938 939 return false; 940 } 941 942 static inline int pmd_bad(pmd_t pmd) 943 { 944 if (radix_enabled()) 945 return radix__pmd_bad(pmd); 946 return hash__pmd_bad(pmd); 947 } 948 949 static inline void pud_clear(pud_t *pudp) 950 { 951 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 952 /* 953 * Don't use this if we can possibly have a hash page table 954 * entry mapping this. 955 */ 956 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 957 } 958 *pudp = __pud(0); 959 } 960 961 static inline int pud_none(pud_t pud) 962 { 963 return !pud_raw(pud); 964 } 965 966 static inline int pud_present(pud_t pud) 967 { 968 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 969 } 970 971 extern struct page *pud_page(pud_t pud); 972 extern struct page *pmd_page(pmd_t pmd); 973 static inline pte_t pud_pte(pud_t pud) 974 { 975 return __pte_raw(pud_raw(pud)); 976 } 977 978 static inline pud_t pte_pud(pte_t pte) 979 { 980 return __pud_raw(pte_raw(pte)); 981 } 982 #define pud_write(pud) pte_write(pud_pte(pud)) 983 984 static inline int pud_bad(pud_t pud) 985 { 986 if (radix_enabled()) 987 return radix__pud_bad(pud); 988 return hash__pud_bad(pud); 989 } 990 991 #define pud_access_permitted pud_access_permitted 992 static inline bool pud_access_permitted(pud_t pud, bool write) 993 { 994 return pte_access_permitted(pud_pte(pud), write); 995 } 996 997 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 998 static inline __be64 p4d_raw(p4d_t x) 999 { 1000 return pgd_raw(x.pgd); 1001 } 1002 1003 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 1004 1005 static inline void p4d_clear(p4d_t *p4dp) 1006 { 1007 *p4dp = __p4d(0); 1008 } 1009 1010 static inline int p4d_none(p4d_t p4d) 1011 { 1012 return !p4d_raw(p4d); 1013 } 1014 1015 static inline int p4d_present(p4d_t p4d) 1016 { 1017 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 1018 } 1019 1020 static inline pte_t p4d_pte(p4d_t p4d) 1021 { 1022 return __pte_raw(p4d_raw(p4d)); 1023 } 1024 1025 static inline p4d_t pte_p4d(pte_t pte) 1026 { 1027 return __p4d_raw(pte_raw(pte)); 1028 } 1029 1030 static inline int p4d_bad(p4d_t p4d) 1031 { 1032 if (radix_enabled()) 1033 return radix__p4d_bad(p4d); 1034 return hash__p4d_bad(p4d); 1035 } 1036 1037 #define p4d_access_permitted p4d_access_permitted 1038 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 1039 { 1040 return pte_access_permitted(p4d_pte(p4d), write); 1041 } 1042 1043 extern struct page *p4d_page(p4d_t p4d); 1044 1045 /* Pointers in the page table tree are physical addresses */ 1046 #define __pgtable_ptr_val(ptr) __pa(ptr) 1047 1048 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 1049 #define p4d_page_vaddr(p4d) __va(p4d_val(p4d) & ~P4D_MASKED_BITS) 1050 1051 #define pte_ERROR(e) \ 1052 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1053 #define pmd_ERROR(e) \ 1054 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1055 #define pud_ERROR(e) \ 1056 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1057 #define pgd_ERROR(e) \ 1058 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1059 1060 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1061 { 1062 if (radix_enabled()) { 1063 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1064 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1065 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1066 #endif 1067 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1068 } 1069 return hash__map_kernel_page(ea, pa, prot); 1070 } 1071 1072 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1073 unsigned long page_size, 1074 unsigned long phys) 1075 { 1076 if (radix_enabled()) 1077 return radix__vmemmap_create_mapping(start, page_size, phys); 1078 return hash__vmemmap_create_mapping(start, page_size, phys); 1079 } 1080 1081 #ifdef CONFIG_MEMORY_HOTPLUG 1082 static inline void vmemmap_remove_mapping(unsigned long start, 1083 unsigned long page_size) 1084 { 1085 if (radix_enabled()) 1086 return radix__vmemmap_remove_mapping(start, page_size); 1087 return hash__vmemmap_remove_mapping(start, page_size); 1088 } 1089 #endif 1090 1091 static inline pte_t pmd_pte(pmd_t pmd) 1092 { 1093 return __pte_raw(pmd_raw(pmd)); 1094 } 1095 1096 static inline pmd_t pte_pmd(pte_t pte) 1097 { 1098 return __pmd_raw(pte_raw(pte)); 1099 } 1100 1101 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1102 { 1103 return (pte_t *)pmd; 1104 } 1105 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1106 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1107 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1108 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1109 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1110 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1111 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1112 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1113 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1114 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1115 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1116 1117 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1118 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1119 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1120 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1121 1122 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1123 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1124 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1125 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1126 #endif 1127 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1128 1129 #ifdef CONFIG_NUMA_BALANCING 1130 static inline int pmd_protnone(pmd_t pmd) 1131 { 1132 return pte_protnone(pmd_pte(pmd)); 1133 } 1134 #endif /* CONFIG_NUMA_BALANCING */ 1135 1136 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1137 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1138 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1139 1140 #define pmd_access_permitted pmd_access_permitted 1141 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1142 { 1143 /* 1144 * pmdp_invalidate sets this combination (which is not caught by 1145 * !pte_present() check in pte_access_permitted), to prevent 1146 * lock-free lookups, as part of the serialize_against_pte_lookup() 1147 * synchronisation. 1148 * 1149 * This also catches the case where the PTE's hardware PRESENT bit is 1150 * cleared while TLB is flushed, which is suboptimal but should not 1151 * be frequent. 1152 */ 1153 if (pmd_is_serializing(pmd)) 1154 return false; 1155 1156 return pte_access_permitted(pmd_pte(pmd), write); 1157 } 1158 1159 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1160 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1161 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1162 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1163 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1164 pmd_t *pmdp, pmd_t pmd); 1165 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1166 unsigned long addr, pmd_t *pmd) 1167 { 1168 } 1169 1170 extern int hash__has_transparent_hugepage(void); 1171 static inline int has_transparent_hugepage(void) 1172 { 1173 if (radix_enabled()) 1174 return radix__has_transparent_hugepage(); 1175 return hash__has_transparent_hugepage(); 1176 } 1177 #define has_transparent_hugepage has_transparent_hugepage 1178 1179 static inline unsigned long 1180 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1181 unsigned long clr, unsigned long set) 1182 { 1183 if (radix_enabled()) 1184 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1185 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1186 } 1187 1188 /* 1189 * returns true for pmd migration entries, THP, devmap, hugetlb 1190 * But compile time dependent on THP config 1191 */ 1192 static inline int pmd_large(pmd_t pmd) 1193 { 1194 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1195 } 1196 1197 /* 1198 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1199 * the below will work for radix too 1200 */ 1201 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1202 unsigned long addr, pmd_t *pmdp) 1203 { 1204 unsigned long old; 1205 1206 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1207 return 0; 1208 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1209 return ((old & _PAGE_ACCESSED) != 0); 1210 } 1211 1212 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1213 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1214 pmd_t *pmdp) 1215 { 1216 if (__pmd_write((*pmdp))) 1217 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1218 else if (unlikely(pmd_savedwrite(*pmdp))) 1219 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1220 } 1221 1222 /* 1223 * Only returns true for a THP. False for pmd migration entry. 1224 * We also need to return true when we come across a pte that 1225 * in between a thp split. While splitting THP, we mark the pmd 1226 * invalid (pmdp_invalidate()) before we set it with pte page 1227 * address. A pmd_trans_huge() check against a pmd entry during that time 1228 * should return true. 1229 * We should not call this on a hugetlb entry. We should check for HugeTLB 1230 * entry using vma->vm_flags 1231 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1232 */ 1233 static inline int pmd_trans_huge(pmd_t pmd) 1234 { 1235 if (!pmd_present(pmd)) 1236 return false; 1237 1238 if (radix_enabled()) 1239 return radix__pmd_trans_huge(pmd); 1240 return hash__pmd_trans_huge(pmd); 1241 } 1242 1243 #define __HAVE_ARCH_PMD_SAME 1244 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1245 { 1246 if (radix_enabled()) 1247 return radix__pmd_same(pmd_a, pmd_b); 1248 return hash__pmd_same(pmd_a, pmd_b); 1249 } 1250 1251 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1252 { 1253 if (radix_enabled()) 1254 return radix__pmd_mkhuge(pmd); 1255 return hash__pmd_mkhuge(pmd); 1256 } 1257 1258 /* 1259 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1260 */ 1261 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1262 { 1263 #ifdef CONFIG_DEBUG_VM 1264 if (radix_enabled()) 1265 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1266 else 1267 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1268 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1269 #endif 1270 return pmd; 1271 } 1272 1273 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1274 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1275 unsigned long address, pmd_t *pmdp, 1276 pmd_t entry, int dirty); 1277 1278 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1279 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1280 unsigned long address, pmd_t *pmdp); 1281 1282 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1283 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1284 unsigned long addr, pmd_t *pmdp) 1285 { 1286 if (radix_enabled()) 1287 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1288 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1289 } 1290 1291 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1292 unsigned long address, pmd_t *pmdp) 1293 { 1294 if (radix_enabled()) 1295 return radix__pmdp_collapse_flush(vma, address, pmdp); 1296 return hash__pmdp_collapse_flush(vma, address, pmdp); 1297 } 1298 #define pmdp_collapse_flush pmdp_collapse_flush 1299 1300 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1301 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1302 unsigned long addr, 1303 pmd_t *pmdp, int full); 1304 1305 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1306 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1307 pmd_t *pmdp, pgtable_t pgtable) 1308 { 1309 if (radix_enabled()) 1310 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1311 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1312 } 1313 1314 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1315 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1316 pmd_t *pmdp) 1317 { 1318 if (radix_enabled()) 1319 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1320 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1321 } 1322 1323 #define __HAVE_ARCH_PMDP_INVALIDATE 1324 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1325 pmd_t *pmdp); 1326 1327 #define pmd_move_must_withdraw pmd_move_must_withdraw 1328 struct spinlock; 1329 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1330 struct spinlock *old_pmd_ptl, 1331 struct vm_area_struct *vma); 1332 /* 1333 * Hash translation mode use the deposited table to store hash pte 1334 * slot information. 1335 */ 1336 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1337 static inline bool arch_needs_pgtable_deposit(void) 1338 { 1339 if (radix_enabled()) 1340 return false; 1341 return true; 1342 } 1343 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1344 1345 1346 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1347 { 1348 if (radix_enabled()) 1349 return radix__pmd_mkdevmap(pmd); 1350 return hash__pmd_mkdevmap(pmd); 1351 } 1352 1353 static inline int pmd_devmap(pmd_t pmd) 1354 { 1355 return pte_devmap(pmd_pte(pmd)); 1356 } 1357 1358 static inline int pud_devmap(pud_t pud) 1359 { 1360 return 0; 1361 } 1362 1363 static inline int pgd_devmap(pgd_t pgd) 1364 { 1365 return 0; 1366 } 1367 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1368 1369 static inline int pud_pfn(pud_t pud) 1370 { 1371 /* 1372 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1373 * check so this should never be used. If it grows another user we 1374 * want to know about it. 1375 */ 1376 BUILD_BUG(); 1377 return 0; 1378 } 1379 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1380 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1381 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1382 pte_t *, pte_t, pte_t); 1383 1384 /* 1385 * Returns true for a R -> RW upgrade of pte 1386 */ 1387 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1388 { 1389 if (!(old_val & _PAGE_READ)) 1390 return false; 1391 1392 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1393 return true; 1394 1395 return false; 1396 } 1397 1398 /* 1399 * Like pmd_huge() and pmd_large(), but works regardless of config options 1400 */ 1401 #define pmd_is_leaf pmd_is_leaf 1402 #define pmd_leaf pmd_is_leaf 1403 static inline bool pmd_is_leaf(pmd_t pmd) 1404 { 1405 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1406 } 1407 1408 #define pud_is_leaf pud_is_leaf 1409 #define pud_leaf pud_is_leaf 1410 static inline bool pud_is_leaf(pud_t pud) 1411 { 1412 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1413 } 1414 1415 #define p4d_is_leaf p4d_is_leaf 1416 #define p4d_leaf p4d_is_leaf 1417 static inline bool p4d_is_leaf(p4d_t p4d) 1418 { 1419 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PTE)); 1420 } 1421 1422 #endif /* __ASSEMBLY__ */ 1423 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1424