1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #include <linux/sizes.h> 11 #endif 12 13 /* 14 * Common bits between hash and Radix page table 15 */ 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x00040UL 36 37 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 38 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 39 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 40 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 41 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 42 43 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 44 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 45 /* 46 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 47 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 48 * differentiate between two use a SW field when invalidating. 49 * 50 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 51 * 52 * This is used only when _PAGE_PRESENT is cleared. 53 */ 54 #define _PAGE_INVALID _RPAGE_SW0 55 56 /* 57 * Top and bottom bits of RPN which can be used by hash 58 * translation mode, because we expect them to be zero 59 * otherwise. 60 */ 61 #define _RPAGE_RPN0 0x01000 62 #define _RPAGE_RPN1 0x02000 63 #define _RPAGE_RPN43 0x0080000000000000UL 64 #define _RPAGE_RPN42 0x0040000000000000UL 65 #define _RPAGE_RPN41 0x0020000000000000UL 66 67 /* Max physical address bit as per radix table */ 68 #define _RPAGE_PA_MAX 56 69 70 /* 71 * Max physical address bit we will use for now. 72 * 73 * This is mostly a hardware limitation and for now Power9 has 74 * a 51 bit limit. 75 * 76 * This is different from the number of physical bit required to address 77 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 78 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 79 * number of sections we can support (SECTIONS_SHIFT). 80 * 81 * This is different from Radix page table limitation above and 82 * should always be less than that. The limit is done such that 83 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 84 * for hash linux page table specific bits. 85 * 86 * In order to be compatible with future hardware generations we keep 87 * some offsets and limit this for now to 53 88 */ 89 #define _PAGE_PA_MAX 53 90 91 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 92 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 93 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) 120 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 121 _PAGE_RW | _PAGE_EXEC) 122 /* 123 * _PAGE_CHG_MASK masks of bits that are to be preserved across 124 * pgprot changes 125 */ 126 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 127 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 128 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 129 130 /* 131 * We define 2 sets of base prot bits, one for basic pages (ie, 132 * cacheable kernel and user pages) and one for non cacheable 133 * pages. We always set _PAGE_COHERENT when SMP is enabled or 134 * the processor might need it for DMA coherency. 135 */ 136 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 137 #define _PAGE_BASE (_PAGE_BASE_NC) 138 139 /* Permission masks used to generate the __P and __S table, 140 * 141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 142 * 143 * Write permissions imply read permissions for now (we could make write-only 144 * pages on BookE but we don't bother for now). Execute permission control is 145 * possible on platforms that define _PAGE_EXEC 146 */ 147 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 148 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 149 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 150 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 151 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 152 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 153 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 154 155 /* Permission masks used for kernel mappings */ 156 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 157 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 158 _PAGE_TOLERANT) 159 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 160 _PAGE_NON_IDEMPOTENT) 161 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 162 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 163 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 164 165 /* 166 * Protection used for kernel text. We want the debuggers to be able to 167 * set breakpoints anywhere, so don't write protect the kernel text 168 * on platforms where such control is possible. 169 */ 170 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 171 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 172 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 173 #else 174 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 175 #endif 176 177 /* Make modules code happy. We don't set RO yet */ 178 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 179 #define PAGE_AGP (PAGE_KERNEL_NC) 180 181 #ifndef __ASSEMBLY__ 182 /* 183 * page table defines 184 */ 185 extern unsigned long __pte_index_size; 186 extern unsigned long __pmd_index_size; 187 extern unsigned long __pud_index_size; 188 extern unsigned long __pgd_index_size; 189 extern unsigned long __pud_cache_index; 190 #define PTE_INDEX_SIZE __pte_index_size 191 #define PMD_INDEX_SIZE __pmd_index_size 192 #define PUD_INDEX_SIZE __pud_index_size 193 #define PGD_INDEX_SIZE __pgd_index_size 194 /* pmd table use page table fragments */ 195 #define PMD_CACHE_INDEX 0 196 #define PUD_CACHE_INDEX __pud_cache_index 197 /* 198 * Because of use of pte fragments and THP, size of page table 199 * are not always derived out of index size above. 200 */ 201 extern unsigned long __pte_table_size; 202 extern unsigned long __pmd_table_size; 203 extern unsigned long __pud_table_size; 204 extern unsigned long __pgd_table_size; 205 #define PTE_TABLE_SIZE __pte_table_size 206 #define PMD_TABLE_SIZE __pmd_table_size 207 #define PUD_TABLE_SIZE __pud_table_size 208 #define PGD_TABLE_SIZE __pgd_table_size 209 210 extern unsigned long __pmd_val_bits; 211 extern unsigned long __pud_val_bits; 212 extern unsigned long __pgd_val_bits; 213 #define PMD_VAL_BITS __pmd_val_bits 214 #define PUD_VAL_BITS __pud_val_bits 215 #define PGD_VAL_BITS __pgd_val_bits 216 217 extern unsigned long __pte_frag_nr; 218 #define PTE_FRAG_NR __pte_frag_nr 219 extern unsigned long __pte_frag_size_shift; 220 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 221 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 222 223 extern unsigned long __pmd_frag_nr; 224 #define PMD_FRAG_NR __pmd_frag_nr 225 extern unsigned long __pmd_frag_size_shift; 226 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 227 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 228 229 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 230 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 231 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 232 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 233 234 #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ 235 H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) 236 237 /* PMD_SHIFT determines what a second-level page table entry can map */ 238 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 239 #define PMD_SIZE (1UL << PMD_SHIFT) 240 #define PMD_MASK (~(PMD_SIZE-1)) 241 242 /* PUD_SHIFT determines what a third-level page table entry can map */ 243 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 244 #define PUD_SIZE (1UL << PUD_SHIFT) 245 #define PUD_MASK (~(PUD_SIZE-1)) 246 247 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 248 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 249 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 250 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 251 252 /* Bits to mask out from a PMD to get to the PTE page */ 253 #define PMD_MASKED_BITS 0xc0000000000000ffUL 254 /* Bits to mask out from a PUD to get to the PMD page */ 255 #define PUD_MASKED_BITS 0xc0000000000000ffUL 256 /* Bits to mask out from a PGD to get to the PUD page */ 257 #define P4D_MASKED_BITS 0xc0000000000000ffUL 258 259 /* 260 * Used as an indicator for rcu callback functions 261 */ 262 enum pgtable_index { 263 PTE_INDEX = 0, 264 PMD_INDEX, 265 PUD_INDEX, 266 PGD_INDEX, 267 /* 268 * Below are used with 4k page size and hugetlb 269 */ 270 HTLB_16M_INDEX, 271 HTLB_16G_INDEX, 272 }; 273 274 extern unsigned long __vmalloc_start; 275 extern unsigned long __vmalloc_end; 276 #define VMALLOC_START __vmalloc_start 277 #define VMALLOC_END __vmalloc_end 278 279 static inline unsigned int ioremap_max_order(void) 280 { 281 if (radix_enabled()) 282 return PUD_SHIFT; 283 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 284 } 285 #define IOREMAP_MAX_ORDER ioremap_max_order() 286 287 extern unsigned long __kernel_virt_start; 288 extern unsigned long __kernel_io_start; 289 extern unsigned long __kernel_io_end; 290 #define KERN_VIRT_START __kernel_virt_start 291 #define KERN_IO_START __kernel_io_start 292 #define KERN_IO_END __kernel_io_end 293 294 extern struct page *vmemmap; 295 extern unsigned long pci_io_base; 296 #endif /* __ASSEMBLY__ */ 297 298 #include <asm/book3s/64/hash.h> 299 #include <asm/book3s/64/radix.h> 300 301 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 302 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 303 #else 304 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 305 #endif 306 307 308 #ifdef CONFIG_PPC_64K_PAGES 309 #include <asm/book3s/64/pgtable-64k.h> 310 #else 311 #include <asm/book3s/64/pgtable-4k.h> 312 #endif 313 314 #include <asm/barrier.h> 315 /* 316 * IO space itself carved into the PIO region (ISA and PHB IO space) and 317 * the ioremap space 318 * 319 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 320 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 321 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 322 */ 323 #define FULL_IO_SIZE 0x80000000ul 324 #define ISA_IO_BASE (KERN_IO_START) 325 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 326 #define PHB_IO_BASE (ISA_IO_END) 327 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 328 #define IOREMAP_BASE (PHB_IO_END) 329 #define IOREMAP_START (ioremap_bot) 330 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) 331 #define FIXADDR_SIZE SZ_32M 332 333 /* Advertise special mapping type for AGP */ 334 #define HAVE_PAGE_AGP 335 336 #ifndef __ASSEMBLY__ 337 338 /* 339 * This is the default implementation of various PTE accessors, it's 340 * used in all cases except Book3S with 64K pages where we have a 341 * concept of sub-pages 342 */ 343 #ifndef __real_pte 344 345 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 346 #define __rpte_to_pte(r) ((r).pte) 347 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 348 349 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 350 do { \ 351 index = 0; \ 352 shift = mmu_psize_defs[psize].shift; \ 353 354 #define pte_iterate_hashed_end() } while(0) 355 356 /* 357 * We expect this to be called only for user addresses or kernel virtual 358 * addresses other than the linear mapping. 359 */ 360 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 361 362 #endif /* __real_pte */ 363 364 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 365 pte_t *ptep, unsigned long clr, 366 unsigned long set, int huge) 367 { 368 if (radix_enabled()) 369 return radix__pte_update(mm, addr, ptep, clr, set, huge); 370 return hash__pte_update(mm, addr, ptep, clr, set, huge); 371 } 372 /* 373 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 374 * We currently remove entries from the hashtable regardless of whether 375 * the entry was young or dirty. 376 * 377 * We should be more intelligent about this but for the moment we override 378 * these functions and force a tlb flush unconditionally 379 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 380 * function for both hash and radix. 381 */ 382 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 383 unsigned long addr, pte_t *ptep) 384 { 385 unsigned long old; 386 387 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 388 return 0; 389 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 390 return (old & _PAGE_ACCESSED) != 0; 391 } 392 393 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 394 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 395 ({ \ 396 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 397 }) 398 399 /* 400 * On Book3S CPUs, clearing the accessed bit without a TLB flush 401 * doesn't cause data corruption. [ It could cause incorrect 402 * page aging and the (mistaken) reclaim of hot pages, but the 403 * chance of that should be relatively low. ] 404 * 405 * So as a performance optimization don't flush the TLB when 406 * clearing the accessed bit, it will eventually be flushed by 407 * a context switch or a VM operation anyway. [ In the rare 408 * event of it not getting flushed for a long time the delay 409 * shouldn't really matter because there's no real memory 410 * pressure for swapout to react to. ] 411 */ 412 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 413 #define ptep_clear_flush_young ptep_test_and_clear_young 414 415 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 416 #define pmdp_clear_flush_young pmdp_test_and_clear_young 417 418 static inline int __pte_write(pte_t pte) 419 { 420 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 421 } 422 423 #ifdef CONFIG_NUMA_BALANCING 424 #define pte_savedwrite pte_savedwrite 425 static inline bool pte_savedwrite(pte_t pte) 426 { 427 /* 428 * Saved write ptes are prot none ptes that doesn't have 429 * privileged bit sit. We mark prot none as one which has 430 * present and pviliged bit set and RWX cleared. To mark 431 * protnone which used to have _PAGE_WRITE set we clear 432 * the privileged bit. 433 */ 434 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 435 } 436 #else 437 #define pte_savedwrite pte_savedwrite 438 static inline bool pte_savedwrite(pte_t pte) 439 { 440 return false; 441 } 442 #endif 443 444 static inline int pte_write(pte_t pte) 445 { 446 return __pte_write(pte) || pte_savedwrite(pte); 447 } 448 449 static inline int pte_read(pte_t pte) 450 { 451 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 452 } 453 454 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 455 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 456 pte_t *ptep) 457 { 458 if (__pte_write(*ptep)) 459 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 460 else if (unlikely(pte_savedwrite(*ptep))) 461 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 462 } 463 464 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 465 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 466 unsigned long addr, pte_t *ptep) 467 { 468 /* 469 * We should not find protnone for hugetlb, but this complete the 470 * interface. 471 */ 472 if (__pte_write(*ptep)) 473 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 474 else if (unlikely(pte_savedwrite(*ptep))) 475 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 476 } 477 478 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 479 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 480 unsigned long addr, pte_t *ptep) 481 { 482 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 483 return __pte(old); 484 } 485 486 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 487 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 488 unsigned long addr, 489 pte_t *ptep, int full) 490 { 491 if (full && radix_enabled()) { 492 /* 493 * We know that this is a full mm pte clear and 494 * hence can be sure there is no parallel set_pte. 495 */ 496 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 497 } 498 return ptep_get_and_clear(mm, addr, ptep); 499 } 500 501 502 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 503 pte_t * ptep) 504 { 505 pte_update(mm, addr, ptep, ~0UL, 0, 0); 506 } 507 508 static inline int pte_dirty(pte_t pte) 509 { 510 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 511 } 512 513 static inline int pte_young(pte_t pte) 514 { 515 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 516 } 517 518 static inline int pte_special(pte_t pte) 519 { 520 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 521 } 522 523 static inline bool pte_exec(pte_t pte) 524 { 525 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 526 } 527 528 529 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 530 static inline bool pte_soft_dirty(pte_t pte) 531 { 532 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 533 } 534 535 static inline pte_t pte_mksoft_dirty(pte_t pte) 536 { 537 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 538 } 539 540 static inline pte_t pte_clear_soft_dirty(pte_t pte) 541 { 542 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 543 } 544 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 545 546 #ifdef CONFIG_NUMA_BALANCING 547 static inline int pte_protnone(pte_t pte) 548 { 549 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 550 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 551 } 552 553 #define pte_mk_savedwrite pte_mk_savedwrite 554 static inline pte_t pte_mk_savedwrite(pte_t pte) 555 { 556 /* 557 * Used by Autonuma subsystem to preserve the write bit 558 * while marking the pte PROT_NONE. Only allow this 559 * on PROT_NONE pte 560 */ 561 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 562 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 563 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 564 } 565 566 #define pte_clear_savedwrite pte_clear_savedwrite 567 static inline pte_t pte_clear_savedwrite(pte_t pte) 568 { 569 /* 570 * Used by KSM subsystem to make a protnone pte readonly. 571 */ 572 VM_BUG_ON(!pte_protnone(pte)); 573 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 574 } 575 #else 576 #define pte_clear_savedwrite pte_clear_savedwrite 577 static inline pte_t pte_clear_savedwrite(pte_t pte) 578 { 579 VM_WARN_ON(1); 580 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 581 } 582 #endif /* CONFIG_NUMA_BALANCING */ 583 584 static inline bool pte_hw_valid(pte_t pte) 585 { 586 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 587 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 588 } 589 590 static inline int pte_present(pte_t pte) 591 { 592 /* 593 * A pte is considerent present if _PAGE_PRESENT is set. 594 * We also need to consider the pte present which is marked 595 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 596 * if we find _PAGE_PRESENT cleared. 597 */ 598 599 if (pte_hw_valid(pte)) 600 return true; 601 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 602 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 603 } 604 605 #ifdef CONFIG_PPC_MEM_KEYS 606 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 607 #else 608 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 609 { 610 return true; 611 } 612 #endif /* CONFIG_PPC_MEM_KEYS */ 613 614 static inline bool pte_user(pte_t pte) 615 { 616 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 617 } 618 619 #define pte_access_permitted pte_access_permitted 620 static inline bool pte_access_permitted(pte_t pte, bool write) 621 { 622 /* 623 * _PAGE_READ is needed for any access and will be 624 * cleared for PROT_NONE 625 */ 626 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 627 return false; 628 629 if (write && !pte_write(pte)) 630 return false; 631 632 return arch_pte_access_permitted(pte_val(pte), write, 0); 633 } 634 635 /* 636 * Conversion functions: convert a page and protection to a page entry, 637 * and a page entry and page directory to the page they refer to. 638 * 639 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 640 * long for now. 641 */ 642 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 643 { 644 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 645 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 646 647 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 648 } 649 650 static inline unsigned long pte_pfn(pte_t pte) 651 { 652 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 653 } 654 655 /* Generic modifiers for PTE bits */ 656 static inline pte_t pte_wrprotect(pte_t pte) 657 { 658 if (unlikely(pte_savedwrite(pte))) 659 return pte_clear_savedwrite(pte); 660 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 661 } 662 663 static inline pte_t pte_exprotect(pte_t pte) 664 { 665 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 666 } 667 668 static inline pte_t pte_mkclean(pte_t pte) 669 { 670 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 671 } 672 673 static inline pte_t pte_mkold(pte_t pte) 674 { 675 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 676 } 677 678 static inline pte_t pte_mkexec(pte_t pte) 679 { 680 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 681 } 682 683 static inline pte_t pte_mkwrite(pte_t pte) 684 { 685 /* 686 * write implies read, hence set both 687 */ 688 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 689 } 690 691 static inline pte_t pte_mkdirty(pte_t pte) 692 { 693 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 694 } 695 696 static inline pte_t pte_mkyoung(pte_t pte) 697 { 698 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 699 } 700 701 static inline pte_t pte_mkspecial(pte_t pte) 702 { 703 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 704 } 705 706 static inline pte_t pte_mkhuge(pte_t pte) 707 { 708 return pte; 709 } 710 711 static inline pte_t pte_mkdevmap(pte_t pte) 712 { 713 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 714 } 715 716 static inline pte_t pte_mkprivileged(pte_t pte) 717 { 718 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 719 } 720 721 static inline pte_t pte_mkuser(pte_t pte) 722 { 723 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 724 } 725 726 /* 727 * This is potentially called with a pmd as the argument, in which case it's not 728 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 729 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 730 * use in page directory entries (ie. non-ptes). 731 */ 732 static inline int pte_devmap(pte_t pte) 733 { 734 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 735 736 return (pte_raw(pte) & mask) == mask; 737 } 738 739 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 740 { 741 /* FIXME!! check whether this need to be a conditional */ 742 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 743 cpu_to_be64(pgprot_val(newprot))); 744 } 745 746 /* Encode and de-code a swap entry */ 747 #define MAX_SWAPFILES_CHECK() do { \ 748 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 749 /* \ 750 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 751 * We filter HPTEFLAGS on set_pte. \ 752 */ \ 753 BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ 754 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 755 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ 756 } while (0) 757 758 #define SWP_TYPE_BITS 5 759 #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) 760 #define __swp_type(x) ((x).val & SWP_TYPE_MASK) 761 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 762 #define __swp_entry(type, offset) ((swp_entry_t) { \ 763 (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 764 /* 765 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 766 * swap type and offset we get from swap and convert that to pte to find a 767 * matching pte in linux page table. 768 * Clear bits not found in swap entries here. 769 */ 770 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 771 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 772 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 773 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 774 775 #ifdef CONFIG_MEM_SOFT_DIRTY 776 #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY 777 #else 778 #define _PAGE_SWP_SOFT_DIRTY 0UL 779 #endif /* CONFIG_MEM_SOFT_DIRTY */ 780 781 #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT 782 783 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 784 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 785 { 786 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 787 } 788 789 static inline bool pte_swp_soft_dirty(pte_t pte) 790 { 791 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 792 } 793 794 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 795 { 796 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 797 } 798 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 799 800 #define __HAVE_ARCH_PTE_SWP_EXCLUSIVE 801 static inline pte_t pte_swp_mkexclusive(pte_t pte) 802 { 803 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 804 } 805 806 static inline int pte_swp_exclusive(pte_t pte) 807 { 808 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 809 } 810 811 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 812 { 813 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); 814 } 815 816 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 817 { 818 /* 819 * This check for _PAGE_RWX and _PAGE_PRESENT bits 820 */ 821 if (access & ~ptev) 822 return false; 823 /* 824 * This check for access to privilege space 825 */ 826 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 827 return false; 828 829 return true; 830 } 831 /* 832 * Generic functions with hash/radix callbacks 833 */ 834 835 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 836 pte_t *ptep, pte_t entry, 837 unsigned long address, 838 int psize) 839 { 840 if (radix_enabled()) 841 return radix__ptep_set_access_flags(vma, ptep, entry, 842 address, psize); 843 return hash__ptep_set_access_flags(ptep, entry); 844 } 845 846 #define __HAVE_ARCH_PTE_SAME 847 static inline int pte_same(pte_t pte_a, pte_t pte_b) 848 { 849 if (radix_enabled()) 850 return radix__pte_same(pte_a, pte_b); 851 return hash__pte_same(pte_a, pte_b); 852 } 853 854 static inline int pte_none(pte_t pte) 855 { 856 if (radix_enabled()) 857 return radix__pte_none(pte); 858 return hash__pte_none(pte); 859 } 860 861 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 862 pte_t *ptep, pte_t pte, int percpu) 863 { 864 865 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 866 /* 867 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 868 * in all the callers. 869 */ 870 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 871 872 if (radix_enabled()) 873 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 874 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 875 } 876 877 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 878 879 #define pgprot_noncached pgprot_noncached 880 static inline pgprot_t pgprot_noncached(pgprot_t prot) 881 { 882 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 883 _PAGE_NON_IDEMPOTENT); 884 } 885 886 #define pgprot_noncached_wc pgprot_noncached_wc 887 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 888 { 889 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 890 _PAGE_TOLERANT); 891 } 892 893 #define pgprot_cached pgprot_cached 894 static inline pgprot_t pgprot_cached(pgprot_t prot) 895 { 896 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 897 } 898 899 #define pgprot_writecombine pgprot_writecombine 900 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 901 { 902 return pgprot_noncached_wc(prot); 903 } 904 /* 905 * check a pte mapping have cache inhibited property 906 */ 907 static inline bool pte_ci(pte_t pte) 908 { 909 __be64 pte_v = pte_raw(pte); 910 911 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 912 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 913 return true; 914 return false; 915 } 916 917 static inline void pmd_clear(pmd_t *pmdp) 918 { 919 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 920 /* 921 * Don't use this if we can possibly have a hash page table 922 * entry mapping this. 923 */ 924 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 925 } 926 *pmdp = __pmd(0); 927 } 928 929 static inline int pmd_none(pmd_t pmd) 930 { 931 return !pmd_raw(pmd); 932 } 933 934 static inline int pmd_present(pmd_t pmd) 935 { 936 /* 937 * A pmd is considerent present if _PAGE_PRESENT is set. 938 * We also need to consider the pmd present which is marked 939 * invalid during a split. Hence we look for _PAGE_INVALID 940 * if we find _PAGE_PRESENT cleared. 941 */ 942 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 943 return true; 944 945 return false; 946 } 947 948 static inline int pmd_is_serializing(pmd_t pmd) 949 { 950 /* 951 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 952 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 953 * 954 * This condition may also occur when flushing a pmd while flushing 955 * it (see ptep_modify_prot_start), so callers must ensure this 956 * case is fine as well. 957 */ 958 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 959 cpu_to_be64(_PAGE_INVALID)) 960 return true; 961 962 return false; 963 } 964 965 static inline int pmd_bad(pmd_t pmd) 966 { 967 if (radix_enabled()) 968 return radix__pmd_bad(pmd); 969 return hash__pmd_bad(pmd); 970 } 971 972 static inline void pud_clear(pud_t *pudp) 973 { 974 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 975 /* 976 * Don't use this if we can possibly have a hash page table 977 * entry mapping this. 978 */ 979 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 980 } 981 *pudp = __pud(0); 982 } 983 984 static inline int pud_none(pud_t pud) 985 { 986 return !pud_raw(pud); 987 } 988 989 static inline int pud_present(pud_t pud) 990 { 991 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 992 } 993 994 extern struct page *pud_page(pud_t pud); 995 extern struct page *pmd_page(pmd_t pmd); 996 static inline pte_t pud_pte(pud_t pud) 997 { 998 return __pte_raw(pud_raw(pud)); 999 } 1000 1001 static inline pud_t pte_pud(pte_t pte) 1002 { 1003 return __pud_raw(pte_raw(pte)); 1004 } 1005 #define pud_write(pud) pte_write(pud_pte(pud)) 1006 1007 static inline int pud_bad(pud_t pud) 1008 { 1009 if (radix_enabled()) 1010 return radix__pud_bad(pud); 1011 return hash__pud_bad(pud); 1012 } 1013 1014 #define pud_access_permitted pud_access_permitted 1015 static inline bool pud_access_permitted(pud_t pud, bool write) 1016 { 1017 return pte_access_permitted(pud_pte(pud), write); 1018 } 1019 1020 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 1021 static inline __be64 p4d_raw(p4d_t x) 1022 { 1023 return pgd_raw(x.pgd); 1024 } 1025 1026 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 1027 1028 static inline void p4d_clear(p4d_t *p4dp) 1029 { 1030 *p4dp = __p4d(0); 1031 } 1032 1033 static inline int p4d_none(p4d_t p4d) 1034 { 1035 return !p4d_raw(p4d); 1036 } 1037 1038 static inline int p4d_present(p4d_t p4d) 1039 { 1040 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 1041 } 1042 1043 static inline pte_t p4d_pte(p4d_t p4d) 1044 { 1045 return __pte_raw(p4d_raw(p4d)); 1046 } 1047 1048 static inline p4d_t pte_p4d(pte_t pte) 1049 { 1050 return __p4d_raw(pte_raw(pte)); 1051 } 1052 1053 static inline int p4d_bad(p4d_t p4d) 1054 { 1055 if (radix_enabled()) 1056 return radix__p4d_bad(p4d); 1057 return hash__p4d_bad(p4d); 1058 } 1059 1060 #define p4d_access_permitted p4d_access_permitted 1061 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 1062 { 1063 return pte_access_permitted(p4d_pte(p4d), write); 1064 } 1065 1066 extern struct page *p4d_page(p4d_t p4d); 1067 1068 /* Pointers in the page table tree are physical addresses */ 1069 #define __pgtable_ptr_val(ptr) __pa(ptr) 1070 1071 static inline pud_t *p4d_pgtable(p4d_t p4d) 1072 { 1073 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); 1074 } 1075 1076 static inline pmd_t *pud_pgtable(pud_t pud) 1077 { 1078 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); 1079 } 1080 1081 #define pte_ERROR(e) \ 1082 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1083 #define pmd_ERROR(e) \ 1084 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1085 #define pud_ERROR(e) \ 1086 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1087 #define pgd_ERROR(e) \ 1088 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1089 1090 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1091 { 1092 if (radix_enabled()) { 1093 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1094 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1095 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1096 #endif 1097 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1098 } 1099 return hash__map_kernel_page(ea, pa, prot); 1100 } 1101 1102 void unmap_kernel_page(unsigned long va); 1103 1104 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1105 unsigned long page_size, 1106 unsigned long phys) 1107 { 1108 if (radix_enabled()) 1109 return radix__vmemmap_create_mapping(start, page_size, phys); 1110 return hash__vmemmap_create_mapping(start, page_size, phys); 1111 } 1112 1113 #ifdef CONFIG_MEMORY_HOTPLUG 1114 static inline void vmemmap_remove_mapping(unsigned long start, 1115 unsigned long page_size) 1116 { 1117 if (radix_enabled()) 1118 return radix__vmemmap_remove_mapping(start, page_size); 1119 return hash__vmemmap_remove_mapping(start, page_size); 1120 } 1121 #endif 1122 1123 #ifdef CONFIG_DEBUG_PAGEALLOC 1124 static inline void __kernel_map_pages(struct page *page, int numpages, int enable) 1125 { 1126 if (radix_enabled()) 1127 radix__kernel_map_pages(page, numpages, enable); 1128 else 1129 hash__kernel_map_pages(page, numpages, enable); 1130 } 1131 #endif 1132 1133 static inline pte_t pmd_pte(pmd_t pmd) 1134 { 1135 return __pte_raw(pmd_raw(pmd)); 1136 } 1137 1138 static inline pmd_t pte_pmd(pte_t pte) 1139 { 1140 return __pmd_raw(pte_raw(pte)); 1141 } 1142 1143 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1144 { 1145 return (pte_t *)pmd; 1146 } 1147 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1148 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1149 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1150 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1151 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1152 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1153 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1154 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1155 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1156 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1157 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1158 1159 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1160 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1161 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1162 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1163 1164 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1165 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1166 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1167 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1168 #endif 1169 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1170 1171 #ifdef CONFIG_NUMA_BALANCING 1172 static inline int pmd_protnone(pmd_t pmd) 1173 { 1174 return pte_protnone(pmd_pte(pmd)); 1175 } 1176 #endif /* CONFIG_NUMA_BALANCING */ 1177 1178 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1179 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1180 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1181 1182 #define pmd_access_permitted pmd_access_permitted 1183 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1184 { 1185 /* 1186 * pmdp_invalidate sets this combination (which is not caught by 1187 * !pte_present() check in pte_access_permitted), to prevent 1188 * lock-free lookups, as part of the serialize_against_pte_lookup() 1189 * synchronisation. 1190 * 1191 * This also catches the case where the PTE's hardware PRESENT bit is 1192 * cleared while TLB is flushed, which is suboptimal but should not 1193 * be frequent. 1194 */ 1195 if (pmd_is_serializing(pmd)) 1196 return false; 1197 1198 return pte_access_permitted(pmd_pte(pmd), write); 1199 } 1200 1201 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1202 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1203 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1204 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1205 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1206 pmd_t *pmdp, pmd_t pmd); 1207 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1208 unsigned long addr, pmd_t *pmd) 1209 { 1210 } 1211 1212 extern int hash__has_transparent_hugepage(void); 1213 static inline int has_transparent_hugepage(void) 1214 { 1215 if (radix_enabled()) 1216 return radix__has_transparent_hugepage(); 1217 return hash__has_transparent_hugepage(); 1218 } 1219 #define has_transparent_hugepage has_transparent_hugepage 1220 1221 static inline unsigned long 1222 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1223 unsigned long clr, unsigned long set) 1224 { 1225 if (radix_enabled()) 1226 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1227 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1228 } 1229 1230 /* 1231 * returns true for pmd migration entries, THP, devmap, hugetlb 1232 * But compile time dependent on THP config 1233 */ 1234 static inline int pmd_large(pmd_t pmd) 1235 { 1236 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1237 } 1238 1239 /* 1240 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1241 * the below will work for radix too 1242 */ 1243 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1244 unsigned long addr, pmd_t *pmdp) 1245 { 1246 unsigned long old; 1247 1248 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1249 return 0; 1250 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1251 return ((old & _PAGE_ACCESSED) != 0); 1252 } 1253 1254 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1255 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1256 pmd_t *pmdp) 1257 { 1258 if (__pmd_write((*pmdp))) 1259 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1260 else if (unlikely(pmd_savedwrite(*pmdp))) 1261 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1262 } 1263 1264 /* 1265 * Only returns true for a THP. False for pmd migration entry. 1266 * We also need to return true when we come across a pte that 1267 * in between a thp split. While splitting THP, we mark the pmd 1268 * invalid (pmdp_invalidate()) before we set it with pte page 1269 * address. A pmd_trans_huge() check against a pmd entry during that time 1270 * should return true. 1271 * We should not call this on a hugetlb entry. We should check for HugeTLB 1272 * entry using vma->vm_flags 1273 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1274 */ 1275 static inline int pmd_trans_huge(pmd_t pmd) 1276 { 1277 if (!pmd_present(pmd)) 1278 return false; 1279 1280 if (radix_enabled()) 1281 return radix__pmd_trans_huge(pmd); 1282 return hash__pmd_trans_huge(pmd); 1283 } 1284 1285 #define __HAVE_ARCH_PMD_SAME 1286 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1287 { 1288 if (radix_enabled()) 1289 return radix__pmd_same(pmd_a, pmd_b); 1290 return hash__pmd_same(pmd_a, pmd_b); 1291 } 1292 1293 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1294 { 1295 if (radix_enabled()) 1296 return radix__pmd_mkhuge(pmd); 1297 return hash__pmd_mkhuge(pmd); 1298 } 1299 1300 /* 1301 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1302 */ 1303 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1304 { 1305 #ifdef CONFIG_DEBUG_VM 1306 if (radix_enabled()) 1307 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1308 else 1309 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1310 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1311 #endif 1312 return pmd; 1313 } 1314 1315 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1316 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1317 unsigned long address, pmd_t *pmdp, 1318 pmd_t entry, int dirty); 1319 1320 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1321 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1322 unsigned long address, pmd_t *pmdp); 1323 1324 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1325 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1326 unsigned long addr, pmd_t *pmdp) 1327 { 1328 if (radix_enabled()) 1329 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1330 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1331 } 1332 1333 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1334 unsigned long address, pmd_t *pmdp) 1335 { 1336 if (radix_enabled()) 1337 return radix__pmdp_collapse_flush(vma, address, pmdp); 1338 return hash__pmdp_collapse_flush(vma, address, pmdp); 1339 } 1340 #define pmdp_collapse_flush pmdp_collapse_flush 1341 1342 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1343 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1344 unsigned long addr, 1345 pmd_t *pmdp, int full); 1346 1347 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1348 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1349 pmd_t *pmdp, pgtable_t pgtable) 1350 { 1351 if (radix_enabled()) 1352 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1353 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1354 } 1355 1356 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1357 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1358 pmd_t *pmdp) 1359 { 1360 if (radix_enabled()) 1361 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1362 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1363 } 1364 1365 #define __HAVE_ARCH_PMDP_INVALIDATE 1366 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1367 pmd_t *pmdp); 1368 1369 #define pmd_move_must_withdraw pmd_move_must_withdraw 1370 struct spinlock; 1371 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1372 struct spinlock *old_pmd_ptl, 1373 struct vm_area_struct *vma); 1374 /* 1375 * Hash translation mode use the deposited table to store hash pte 1376 * slot information. 1377 */ 1378 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1379 static inline bool arch_needs_pgtable_deposit(void) 1380 { 1381 if (radix_enabled()) 1382 return false; 1383 return true; 1384 } 1385 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1386 1387 1388 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1389 { 1390 if (radix_enabled()) 1391 return radix__pmd_mkdevmap(pmd); 1392 return hash__pmd_mkdevmap(pmd); 1393 } 1394 1395 static inline int pmd_devmap(pmd_t pmd) 1396 { 1397 return pte_devmap(pmd_pte(pmd)); 1398 } 1399 1400 static inline int pud_devmap(pud_t pud) 1401 { 1402 return 0; 1403 } 1404 1405 static inline int pgd_devmap(pgd_t pgd) 1406 { 1407 return 0; 1408 } 1409 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1410 1411 static inline int pud_pfn(pud_t pud) 1412 { 1413 /* 1414 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1415 * check so this should never be used. If it grows another user we 1416 * want to know about it. 1417 */ 1418 BUILD_BUG(); 1419 return 0; 1420 } 1421 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1422 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1423 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1424 pte_t *, pte_t, pte_t); 1425 1426 /* 1427 * Returns true for a R -> RW upgrade of pte 1428 */ 1429 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1430 { 1431 if (!(old_val & _PAGE_READ)) 1432 return false; 1433 1434 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1435 return true; 1436 1437 return false; 1438 } 1439 1440 /* 1441 * Like pmd_huge() and pmd_large(), but works regardless of config options 1442 */ 1443 #define pmd_is_leaf pmd_is_leaf 1444 #define pmd_leaf pmd_is_leaf 1445 static inline bool pmd_is_leaf(pmd_t pmd) 1446 { 1447 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1448 } 1449 1450 #define pud_is_leaf pud_is_leaf 1451 #define pud_leaf pud_is_leaf 1452 static inline bool pud_is_leaf(pud_t pud) 1453 { 1454 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1455 } 1456 1457 #define p4d_is_leaf p4d_is_leaf 1458 #define p4d_leaf p4d_is_leaf 1459 static inline bool p4d_is_leaf(p4d_t p4d) 1460 { 1461 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PTE)); 1462 } 1463 1464 #endif /* __ASSEMBLY__ */ 1465 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1466