1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #include <linux/sizes.h> 11 #endif 12 13 /* 14 * Common bits between hash and Radix page table 15 */ 16 #define _PAGE_BIT_SWAP_TYPE 0 17 18 #define _PAGE_EXEC 0x00001 /* execute permission */ 19 #define _PAGE_WRITE 0x00002 /* write access allowed */ 20 #define _PAGE_READ 0x00004 /* read access allowed */ 21 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 22 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 23 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 24 #define _PAGE_SAO 0x00010 /* Strong access order */ 25 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 26 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 27 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 28 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 29 /* 30 * Software bits 31 */ 32 #define _RPAGE_SW0 0x2000000000000000UL 33 #define _RPAGE_SW1 0x00800 34 #define _RPAGE_SW2 0x00400 35 #define _RPAGE_SW3 0x00200 36 #define _RPAGE_RSV1 0x00040UL 37 38 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 39 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 40 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 41 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 42 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 43 44 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 45 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 46 /* 47 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 48 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 49 * differentiate between two use a SW field when invalidating. 50 * 51 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 52 * 53 * This is used only when _PAGE_PRESENT is cleared. 54 */ 55 #define _PAGE_INVALID _RPAGE_SW0 56 57 /* 58 * Top and bottom bits of RPN which can be used by hash 59 * translation mode, because we expect them to be zero 60 * otherwise. 61 */ 62 #define _RPAGE_RPN0 0x01000 63 #define _RPAGE_RPN1 0x02000 64 #define _RPAGE_RPN43 0x0080000000000000UL 65 #define _RPAGE_RPN42 0x0040000000000000UL 66 #define _RPAGE_RPN41 0x0020000000000000UL 67 68 /* Max physical address bit as per radix table */ 69 #define _RPAGE_PA_MAX 56 70 71 /* 72 * Max physical address bit we will use for now. 73 * 74 * This is mostly a hardware limitation and for now Power9 has 75 * a 51 bit limit. 76 * 77 * This is different from the number of physical bit required to address 78 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 79 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 80 * number of sections we can support (SECTIONS_SHIFT). 81 * 82 * This is different from Radix page table limitation above and 83 * should always be less than that. The limit is done such that 84 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 85 * for hash linux page table specific bits. 86 * 87 * In order to be compatible with future hardware generations we keep 88 * some offsets and limit this for now to 53 89 */ 90 #define _PAGE_PA_MAX 53 91 92 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 93 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 94 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 95 96 /* 97 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 98 * Instead of fixing all of them, add an alternate define which 99 * maps CI pte mapping. 100 */ 101 #define _PAGE_NO_CACHE _PAGE_TOLERANT 102 /* 103 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 104 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 105 * and every thing below PAGE_SHIFT; 106 */ 107 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 108 /* 109 * set of bits not changed in pmd_modify. Even though we have hash specific bits 110 * in here, on radix we expect them to be zero. 111 */ 112 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 113 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 114 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 115 /* 116 * user access blocked by key 117 */ 118 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 119 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 120 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) 121 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 122 _PAGE_RW | _PAGE_EXEC) 123 /* 124 * _PAGE_CHG_MASK masks of bits that are to be preserved across 125 * pgprot changes 126 */ 127 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 128 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 129 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 130 131 /* 132 * We define 2 sets of base prot bits, one for basic pages (ie, 133 * cacheable kernel and user pages) and one for non cacheable 134 * pages. We always set _PAGE_COHERENT when SMP is enabled or 135 * the processor might need it for DMA coherency. 136 */ 137 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 138 #define _PAGE_BASE (_PAGE_BASE_NC) 139 140 /* Permission masks used to generate the __P and __S table, 141 * 142 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 143 * 144 * Write permissions imply read permissions for now (we could make write-only 145 * pages on BookE but we don't bother for now). Execute permission control is 146 * possible on platforms that define _PAGE_EXEC 147 */ 148 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 149 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 150 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 151 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 152 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 153 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 154 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 155 156 /* Permission masks used for kernel mappings */ 157 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 158 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 159 _PAGE_TOLERANT) 160 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 161 _PAGE_NON_IDEMPOTENT) 162 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 163 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 164 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 165 166 /* 167 * Protection used for kernel text. We want the debuggers to be able to 168 * set breakpoints anywhere, so don't write protect the kernel text 169 * on platforms where such control is possible. 170 */ 171 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 172 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 173 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 174 #else 175 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 176 #endif 177 178 /* Make modules code happy. We don't set RO yet */ 179 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 180 #define PAGE_AGP (PAGE_KERNEL_NC) 181 182 #ifndef __ASSEMBLY__ 183 /* 184 * page table defines 185 */ 186 extern unsigned long __pte_index_size; 187 extern unsigned long __pmd_index_size; 188 extern unsigned long __pud_index_size; 189 extern unsigned long __pgd_index_size; 190 extern unsigned long __pud_cache_index; 191 #define PTE_INDEX_SIZE __pte_index_size 192 #define PMD_INDEX_SIZE __pmd_index_size 193 #define PUD_INDEX_SIZE __pud_index_size 194 #define PGD_INDEX_SIZE __pgd_index_size 195 /* pmd table use page table fragments */ 196 #define PMD_CACHE_INDEX 0 197 #define PUD_CACHE_INDEX __pud_cache_index 198 /* 199 * Because of use of pte fragments and THP, size of page table 200 * are not always derived out of index size above. 201 */ 202 extern unsigned long __pte_table_size; 203 extern unsigned long __pmd_table_size; 204 extern unsigned long __pud_table_size; 205 extern unsigned long __pgd_table_size; 206 #define PTE_TABLE_SIZE __pte_table_size 207 #define PMD_TABLE_SIZE __pmd_table_size 208 #define PUD_TABLE_SIZE __pud_table_size 209 #define PGD_TABLE_SIZE __pgd_table_size 210 211 extern unsigned long __pmd_val_bits; 212 extern unsigned long __pud_val_bits; 213 extern unsigned long __pgd_val_bits; 214 #define PMD_VAL_BITS __pmd_val_bits 215 #define PUD_VAL_BITS __pud_val_bits 216 #define PGD_VAL_BITS __pgd_val_bits 217 218 extern unsigned long __pte_frag_nr; 219 #define PTE_FRAG_NR __pte_frag_nr 220 extern unsigned long __pte_frag_size_shift; 221 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 222 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 223 224 extern unsigned long __pmd_frag_nr; 225 #define PMD_FRAG_NR __pmd_frag_nr 226 extern unsigned long __pmd_frag_size_shift; 227 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 228 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 229 230 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 231 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 232 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 233 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 234 235 /* PMD_SHIFT determines what a second-level page table entry can map */ 236 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 237 #define PMD_SIZE (1UL << PMD_SHIFT) 238 #define PMD_MASK (~(PMD_SIZE-1)) 239 240 /* PUD_SHIFT determines what a third-level page table entry can map */ 241 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 242 #define PUD_SIZE (1UL << PUD_SHIFT) 243 #define PUD_MASK (~(PUD_SIZE-1)) 244 245 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 246 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 247 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 248 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 249 250 /* Bits to mask out from a PMD to get to the PTE page */ 251 #define PMD_MASKED_BITS 0xc0000000000000ffUL 252 /* Bits to mask out from a PUD to get to the PMD page */ 253 #define PUD_MASKED_BITS 0xc0000000000000ffUL 254 /* Bits to mask out from a PGD to get to the PUD page */ 255 #define P4D_MASKED_BITS 0xc0000000000000ffUL 256 257 /* 258 * Used as an indicator for rcu callback functions 259 */ 260 enum pgtable_index { 261 PTE_INDEX = 0, 262 PMD_INDEX, 263 PUD_INDEX, 264 PGD_INDEX, 265 /* 266 * Below are used with 4k page size and hugetlb 267 */ 268 HTLB_16M_INDEX, 269 HTLB_16G_INDEX, 270 }; 271 272 extern unsigned long __vmalloc_start; 273 extern unsigned long __vmalloc_end; 274 #define VMALLOC_START __vmalloc_start 275 #define VMALLOC_END __vmalloc_end 276 277 static inline unsigned int ioremap_max_order(void) 278 { 279 if (radix_enabled()) 280 return PUD_SHIFT; 281 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 282 } 283 #define IOREMAP_MAX_ORDER ioremap_max_order() 284 285 extern unsigned long __kernel_virt_start; 286 extern unsigned long __kernel_io_start; 287 extern unsigned long __kernel_io_end; 288 #define KERN_VIRT_START __kernel_virt_start 289 #define KERN_IO_START __kernel_io_start 290 #define KERN_IO_END __kernel_io_end 291 292 extern struct page *vmemmap; 293 extern unsigned long pci_io_base; 294 #endif /* __ASSEMBLY__ */ 295 296 #include <asm/book3s/64/hash.h> 297 #include <asm/book3s/64/radix.h> 298 299 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 300 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 301 #else 302 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 303 #endif 304 305 306 #ifdef CONFIG_PPC_64K_PAGES 307 #include <asm/book3s/64/pgtable-64k.h> 308 #else 309 #include <asm/book3s/64/pgtable-4k.h> 310 #endif 311 312 #include <asm/barrier.h> 313 /* 314 * IO space itself carved into the PIO region (ISA and PHB IO space) and 315 * the ioremap space 316 * 317 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 318 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 319 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 320 */ 321 #define FULL_IO_SIZE 0x80000000ul 322 #define ISA_IO_BASE (KERN_IO_START) 323 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 324 #define PHB_IO_BASE (ISA_IO_END) 325 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 326 #define IOREMAP_BASE (PHB_IO_END) 327 #define IOREMAP_START (ioremap_bot) 328 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) 329 #define FIXADDR_SIZE SZ_32M 330 331 /* Advertise special mapping type for AGP */ 332 #define HAVE_PAGE_AGP 333 334 #ifndef __ASSEMBLY__ 335 336 /* 337 * This is the default implementation of various PTE accessors, it's 338 * used in all cases except Book3S with 64K pages where we have a 339 * concept of sub-pages 340 */ 341 #ifndef __real_pte 342 343 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 344 #define __rpte_to_pte(r) ((r).pte) 345 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 346 347 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 348 do { \ 349 index = 0; \ 350 shift = mmu_psize_defs[psize].shift; \ 351 352 #define pte_iterate_hashed_end() } while(0) 353 354 /* 355 * We expect this to be called only for user addresses or kernel virtual 356 * addresses other than the linear mapping. 357 */ 358 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 359 360 #endif /* __real_pte */ 361 362 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 363 pte_t *ptep, unsigned long clr, 364 unsigned long set, int huge) 365 { 366 if (radix_enabled()) 367 return radix__pte_update(mm, addr, ptep, clr, set, huge); 368 return hash__pte_update(mm, addr, ptep, clr, set, huge); 369 } 370 /* 371 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 372 * We currently remove entries from the hashtable regardless of whether 373 * the entry was young or dirty. 374 * 375 * We should be more intelligent about this but for the moment we override 376 * these functions and force a tlb flush unconditionally 377 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 378 * function for both hash and radix. 379 */ 380 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 381 unsigned long addr, pte_t *ptep) 382 { 383 unsigned long old; 384 385 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 386 return 0; 387 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 388 return (old & _PAGE_ACCESSED) != 0; 389 } 390 391 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 392 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 393 ({ \ 394 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 395 }) 396 397 /* 398 * On Book3S CPUs, clearing the accessed bit without a TLB flush 399 * doesn't cause data corruption. [ It could cause incorrect 400 * page aging and the (mistaken) reclaim of hot pages, but the 401 * chance of that should be relatively low. ] 402 * 403 * So as a performance optimization don't flush the TLB when 404 * clearing the accessed bit, it will eventually be flushed by 405 * a context switch or a VM operation anyway. [ In the rare 406 * event of it not getting flushed for a long time the delay 407 * shouldn't really matter because there's no real memory 408 * pressure for swapout to react to. ] 409 */ 410 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 411 #define ptep_clear_flush_young ptep_test_and_clear_young 412 413 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 414 #define pmdp_clear_flush_young pmdp_test_and_clear_young 415 416 static inline int __pte_write(pte_t pte) 417 { 418 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 419 } 420 421 #ifdef CONFIG_NUMA_BALANCING 422 #define pte_savedwrite pte_savedwrite 423 static inline bool pte_savedwrite(pte_t pte) 424 { 425 /* 426 * Saved write ptes are prot none ptes that doesn't have 427 * privileged bit sit. We mark prot none as one which has 428 * present and pviliged bit set and RWX cleared. To mark 429 * protnone which used to have _PAGE_WRITE set we clear 430 * the privileged bit. 431 */ 432 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 433 } 434 #else 435 #define pte_savedwrite pte_savedwrite 436 static inline bool pte_savedwrite(pte_t pte) 437 { 438 return false; 439 } 440 #endif 441 442 static inline int pte_write(pte_t pte) 443 { 444 return __pte_write(pte) || pte_savedwrite(pte); 445 } 446 447 static inline int pte_read(pte_t pte) 448 { 449 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 450 } 451 452 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 453 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 454 pte_t *ptep) 455 { 456 if (__pte_write(*ptep)) 457 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 458 else if (unlikely(pte_savedwrite(*ptep))) 459 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 460 } 461 462 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 463 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 464 unsigned long addr, pte_t *ptep) 465 { 466 /* 467 * We should not find protnone for hugetlb, but this complete the 468 * interface. 469 */ 470 if (__pte_write(*ptep)) 471 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 472 else if (unlikely(pte_savedwrite(*ptep))) 473 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 474 } 475 476 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 477 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 478 unsigned long addr, pte_t *ptep) 479 { 480 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 481 return __pte(old); 482 } 483 484 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 485 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 486 unsigned long addr, 487 pte_t *ptep, int full) 488 { 489 if (full && radix_enabled()) { 490 /* 491 * We know that this is a full mm pte clear and 492 * hence can be sure there is no parallel set_pte. 493 */ 494 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 495 } 496 return ptep_get_and_clear(mm, addr, ptep); 497 } 498 499 500 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 501 pte_t * ptep) 502 { 503 pte_update(mm, addr, ptep, ~0UL, 0, 0); 504 } 505 506 static inline int pte_dirty(pte_t pte) 507 { 508 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 509 } 510 511 static inline int pte_young(pte_t pte) 512 { 513 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 514 } 515 516 static inline int pte_special(pte_t pte) 517 { 518 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 519 } 520 521 static inline bool pte_exec(pte_t pte) 522 { 523 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 524 } 525 526 527 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 528 static inline bool pte_soft_dirty(pte_t pte) 529 { 530 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 531 } 532 533 static inline pte_t pte_mksoft_dirty(pte_t pte) 534 { 535 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 536 } 537 538 static inline pte_t pte_clear_soft_dirty(pte_t pte) 539 { 540 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 541 } 542 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 543 544 #ifdef CONFIG_NUMA_BALANCING 545 static inline int pte_protnone(pte_t pte) 546 { 547 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 548 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 549 } 550 551 #define pte_mk_savedwrite pte_mk_savedwrite 552 static inline pte_t pte_mk_savedwrite(pte_t pte) 553 { 554 /* 555 * Used by Autonuma subsystem to preserve the write bit 556 * while marking the pte PROT_NONE. Only allow this 557 * on PROT_NONE pte 558 */ 559 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 560 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 561 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 562 } 563 564 #define pte_clear_savedwrite pte_clear_savedwrite 565 static inline pte_t pte_clear_savedwrite(pte_t pte) 566 { 567 /* 568 * Used by KSM subsystem to make a protnone pte readonly. 569 */ 570 VM_BUG_ON(!pte_protnone(pte)); 571 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 572 } 573 #else 574 #define pte_clear_savedwrite pte_clear_savedwrite 575 static inline pte_t pte_clear_savedwrite(pte_t pte) 576 { 577 VM_WARN_ON(1); 578 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 579 } 580 #endif /* CONFIG_NUMA_BALANCING */ 581 582 static inline bool pte_hw_valid(pte_t pte) 583 { 584 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 585 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 586 } 587 588 static inline int pte_present(pte_t pte) 589 { 590 /* 591 * A pte is considerent present if _PAGE_PRESENT is set. 592 * We also need to consider the pte present which is marked 593 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 594 * if we find _PAGE_PRESENT cleared. 595 */ 596 597 if (pte_hw_valid(pte)) 598 return true; 599 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 600 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 601 } 602 603 #ifdef CONFIG_PPC_MEM_KEYS 604 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 605 #else 606 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 607 { 608 return true; 609 } 610 #endif /* CONFIG_PPC_MEM_KEYS */ 611 612 static inline bool pte_user(pte_t pte) 613 { 614 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 615 } 616 617 #define pte_access_permitted pte_access_permitted 618 static inline bool pte_access_permitted(pte_t pte, bool write) 619 { 620 /* 621 * _PAGE_READ is needed for any access and will be 622 * cleared for PROT_NONE 623 */ 624 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 625 return false; 626 627 if (write && !pte_write(pte)) 628 return false; 629 630 return arch_pte_access_permitted(pte_val(pte), write, 0); 631 } 632 633 /* 634 * Conversion functions: convert a page and protection to a page entry, 635 * and a page entry and page directory to the page they refer to. 636 * 637 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 638 * long for now. 639 */ 640 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 641 { 642 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 643 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 644 645 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 646 } 647 648 static inline unsigned long pte_pfn(pte_t pte) 649 { 650 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 651 } 652 653 /* Generic modifiers for PTE bits */ 654 static inline pte_t pte_wrprotect(pte_t pte) 655 { 656 if (unlikely(pte_savedwrite(pte))) 657 return pte_clear_savedwrite(pte); 658 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 659 } 660 661 static inline pte_t pte_exprotect(pte_t pte) 662 { 663 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 664 } 665 666 static inline pte_t pte_mkclean(pte_t pte) 667 { 668 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 669 } 670 671 static inline pte_t pte_mkold(pte_t pte) 672 { 673 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 674 } 675 676 static inline pte_t pte_mkexec(pte_t pte) 677 { 678 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 679 } 680 681 static inline pte_t pte_mkwrite(pte_t pte) 682 { 683 /* 684 * write implies read, hence set both 685 */ 686 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 687 } 688 689 static inline pte_t pte_mkdirty(pte_t pte) 690 { 691 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 692 } 693 694 static inline pte_t pte_mkyoung(pte_t pte) 695 { 696 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 697 } 698 699 static inline pte_t pte_mkspecial(pte_t pte) 700 { 701 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 702 } 703 704 static inline pte_t pte_mkhuge(pte_t pte) 705 { 706 return pte; 707 } 708 709 static inline pte_t pte_mkdevmap(pte_t pte) 710 { 711 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 712 } 713 714 static inline pte_t pte_mkprivileged(pte_t pte) 715 { 716 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 717 } 718 719 static inline pte_t pte_mkuser(pte_t pte) 720 { 721 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 722 } 723 724 /* 725 * This is potentially called with a pmd as the argument, in which case it's not 726 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 727 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 728 * use in page directory entries (ie. non-ptes). 729 */ 730 static inline int pte_devmap(pte_t pte) 731 { 732 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 733 734 return (pte_raw(pte) & mask) == mask; 735 } 736 737 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 738 { 739 /* FIXME!! check whether this need to be a conditional */ 740 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 741 cpu_to_be64(pgprot_val(newprot))); 742 } 743 744 /* Encode and de-code a swap entry */ 745 #define MAX_SWAPFILES_CHECK() do { \ 746 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 747 /* \ 748 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 749 * We filter HPTEFLAGS on set_pte. \ 750 */ \ 751 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 752 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 753 } while (0) 754 755 #define SWP_TYPE_BITS 5 756 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 757 & ((1UL << SWP_TYPE_BITS) - 1)) 758 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 759 #define __swp_entry(type, offset) ((swp_entry_t) { \ 760 ((type) << _PAGE_BIT_SWAP_TYPE) \ 761 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 762 /* 763 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 764 * swap type and offset we get from swap and convert that to pte to find a 765 * matching pte in linux page table. 766 * Clear bits not found in swap entries here. 767 */ 768 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 769 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 770 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 771 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 772 773 #ifdef CONFIG_MEM_SOFT_DIRTY 774 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 775 #else 776 #define _PAGE_SWP_SOFT_DIRTY 0UL 777 #endif /* CONFIG_MEM_SOFT_DIRTY */ 778 779 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 780 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 781 { 782 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 783 } 784 785 static inline bool pte_swp_soft_dirty(pte_t pte) 786 { 787 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 788 } 789 790 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 791 { 792 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 793 } 794 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 795 796 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 797 { 798 /* 799 * This check for _PAGE_RWX and _PAGE_PRESENT bits 800 */ 801 if (access & ~ptev) 802 return false; 803 /* 804 * This check for access to privilege space 805 */ 806 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 807 return false; 808 809 return true; 810 } 811 /* 812 * Generic functions with hash/radix callbacks 813 */ 814 815 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 816 pte_t *ptep, pte_t entry, 817 unsigned long address, 818 int psize) 819 { 820 if (radix_enabled()) 821 return radix__ptep_set_access_flags(vma, ptep, entry, 822 address, psize); 823 return hash__ptep_set_access_flags(ptep, entry); 824 } 825 826 #define __HAVE_ARCH_PTE_SAME 827 static inline int pte_same(pte_t pte_a, pte_t pte_b) 828 { 829 if (radix_enabled()) 830 return radix__pte_same(pte_a, pte_b); 831 return hash__pte_same(pte_a, pte_b); 832 } 833 834 static inline int pte_none(pte_t pte) 835 { 836 if (radix_enabled()) 837 return radix__pte_none(pte); 838 return hash__pte_none(pte); 839 } 840 841 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 842 pte_t *ptep, pte_t pte, int percpu) 843 { 844 845 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 846 /* 847 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 848 * in all the callers. 849 */ 850 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 851 852 if (radix_enabled()) 853 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 854 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 855 } 856 857 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 858 859 #define pgprot_noncached pgprot_noncached 860 static inline pgprot_t pgprot_noncached(pgprot_t prot) 861 { 862 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 863 _PAGE_NON_IDEMPOTENT); 864 } 865 866 #define pgprot_noncached_wc pgprot_noncached_wc 867 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 868 { 869 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 870 _PAGE_TOLERANT); 871 } 872 873 #define pgprot_cached pgprot_cached 874 static inline pgprot_t pgprot_cached(pgprot_t prot) 875 { 876 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 877 } 878 879 #define pgprot_writecombine pgprot_writecombine 880 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 881 { 882 return pgprot_noncached_wc(prot); 883 } 884 /* 885 * check a pte mapping have cache inhibited property 886 */ 887 static inline bool pte_ci(pte_t pte) 888 { 889 __be64 pte_v = pte_raw(pte); 890 891 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 892 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 893 return true; 894 return false; 895 } 896 897 static inline void pmd_clear(pmd_t *pmdp) 898 { 899 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 900 /* 901 * Don't use this if we can possibly have a hash page table 902 * entry mapping this. 903 */ 904 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 905 } 906 *pmdp = __pmd(0); 907 } 908 909 static inline int pmd_none(pmd_t pmd) 910 { 911 return !pmd_raw(pmd); 912 } 913 914 static inline int pmd_present(pmd_t pmd) 915 { 916 /* 917 * A pmd is considerent present if _PAGE_PRESENT is set. 918 * We also need to consider the pmd present which is marked 919 * invalid during a split. Hence we look for _PAGE_INVALID 920 * if we find _PAGE_PRESENT cleared. 921 */ 922 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 923 return true; 924 925 return false; 926 } 927 928 static inline int pmd_is_serializing(pmd_t pmd) 929 { 930 /* 931 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 932 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 933 * 934 * This condition may also occur when flushing a pmd while flushing 935 * it (see ptep_modify_prot_start), so callers must ensure this 936 * case is fine as well. 937 */ 938 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 939 cpu_to_be64(_PAGE_INVALID)) 940 return true; 941 942 return false; 943 } 944 945 static inline int pmd_bad(pmd_t pmd) 946 { 947 if (radix_enabled()) 948 return radix__pmd_bad(pmd); 949 return hash__pmd_bad(pmd); 950 } 951 952 static inline void pud_clear(pud_t *pudp) 953 { 954 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 955 /* 956 * Don't use this if we can possibly have a hash page table 957 * entry mapping this. 958 */ 959 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 960 } 961 *pudp = __pud(0); 962 } 963 964 static inline int pud_none(pud_t pud) 965 { 966 return !pud_raw(pud); 967 } 968 969 static inline int pud_present(pud_t pud) 970 { 971 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 972 } 973 974 extern struct page *pud_page(pud_t pud); 975 extern struct page *pmd_page(pmd_t pmd); 976 static inline pte_t pud_pte(pud_t pud) 977 { 978 return __pte_raw(pud_raw(pud)); 979 } 980 981 static inline pud_t pte_pud(pte_t pte) 982 { 983 return __pud_raw(pte_raw(pte)); 984 } 985 #define pud_write(pud) pte_write(pud_pte(pud)) 986 987 static inline int pud_bad(pud_t pud) 988 { 989 if (radix_enabled()) 990 return radix__pud_bad(pud); 991 return hash__pud_bad(pud); 992 } 993 994 #define pud_access_permitted pud_access_permitted 995 static inline bool pud_access_permitted(pud_t pud, bool write) 996 { 997 return pte_access_permitted(pud_pte(pud), write); 998 } 999 1000 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 1001 static inline __be64 p4d_raw(p4d_t x) 1002 { 1003 return pgd_raw(x.pgd); 1004 } 1005 1006 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 1007 1008 static inline void p4d_clear(p4d_t *p4dp) 1009 { 1010 *p4dp = __p4d(0); 1011 } 1012 1013 static inline int p4d_none(p4d_t p4d) 1014 { 1015 return !p4d_raw(p4d); 1016 } 1017 1018 static inline int p4d_present(p4d_t p4d) 1019 { 1020 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 1021 } 1022 1023 static inline pte_t p4d_pte(p4d_t p4d) 1024 { 1025 return __pte_raw(p4d_raw(p4d)); 1026 } 1027 1028 static inline p4d_t pte_p4d(pte_t pte) 1029 { 1030 return __p4d_raw(pte_raw(pte)); 1031 } 1032 1033 static inline int p4d_bad(p4d_t p4d) 1034 { 1035 if (radix_enabled()) 1036 return radix__p4d_bad(p4d); 1037 return hash__p4d_bad(p4d); 1038 } 1039 1040 #define p4d_access_permitted p4d_access_permitted 1041 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 1042 { 1043 return pte_access_permitted(p4d_pte(p4d), write); 1044 } 1045 1046 extern struct page *p4d_page(p4d_t p4d); 1047 1048 /* Pointers in the page table tree are physical addresses */ 1049 #define __pgtable_ptr_val(ptr) __pa(ptr) 1050 1051 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 1052 #define p4d_page_vaddr(p4d) __va(p4d_val(p4d) & ~P4D_MASKED_BITS) 1053 1054 #define pte_ERROR(e) \ 1055 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1056 #define pmd_ERROR(e) \ 1057 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1058 #define pud_ERROR(e) \ 1059 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1060 #define pgd_ERROR(e) \ 1061 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1062 1063 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1064 { 1065 if (radix_enabled()) { 1066 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1067 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1068 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1069 #endif 1070 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1071 } 1072 return hash__map_kernel_page(ea, pa, prot); 1073 } 1074 1075 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1076 unsigned long page_size, 1077 unsigned long phys) 1078 { 1079 if (radix_enabled()) 1080 return radix__vmemmap_create_mapping(start, page_size, phys); 1081 return hash__vmemmap_create_mapping(start, page_size, phys); 1082 } 1083 1084 #ifdef CONFIG_MEMORY_HOTPLUG 1085 static inline void vmemmap_remove_mapping(unsigned long start, 1086 unsigned long page_size) 1087 { 1088 if (radix_enabled()) 1089 return radix__vmemmap_remove_mapping(start, page_size); 1090 return hash__vmemmap_remove_mapping(start, page_size); 1091 } 1092 #endif 1093 1094 static inline pte_t pmd_pte(pmd_t pmd) 1095 { 1096 return __pte_raw(pmd_raw(pmd)); 1097 } 1098 1099 static inline pmd_t pte_pmd(pte_t pte) 1100 { 1101 return __pmd_raw(pte_raw(pte)); 1102 } 1103 1104 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1105 { 1106 return (pte_t *)pmd; 1107 } 1108 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1109 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1110 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1111 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1112 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1113 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1114 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1115 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1116 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1117 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1118 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1119 1120 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1121 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1122 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1123 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1124 1125 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1126 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1127 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1128 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1129 #endif 1130 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1131 1132 #ifdef CONFIG_NUMA_BALANCING 1133 static inline int pmd_protnone(pmd_t pmd) 1134 { 1135 return pte_protnone(pmd_pte(pmd)); 1136 } 1137 #endif /* CONFIG_NUMA_BALANCING */ 1138 1139 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1140 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1141 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1142 1143 #define pmd_access_permitted pmd_access_permitted 1144 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1145 { 1146 /* 1147 * pmdp_invalidate sets this combination (which is not caught by 1148 * !pte_present() check in pte_access_permitted), to prevent 1149 * lock-free lookups, as part of the serialize_against_pte_lookup() 1150 * synchronisation. 1151 * 1152 * This also catches the case where the PTE's hardware PRESENT bit is 1153 * cleared while TLB is flushed, which is suboptimal but should not 1154 * be frequent. 1155 */ 1156 if (pmd_is_serializing(pmd)) 1157 return false; 1158 1159 return pte_access_permitted(pmd_pte(pmd), write); 1160 } 1161 1162 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1163 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1164 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1165 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1166 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1167 pmd_t *pmdp, pmd_t pmd); 1168 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1169 unsigned long addr, pmd_t *pmd) 1170 { 1171 } 1172 1173 extern int hash__has_transparent_hugepage(void); 1174 static inline int has_transparent_hugepage(void) 1175 { 1176 if (radix_enabled()) 1177 return radix__has_transparent_hugepage(); 1178 return hash__has_transparent_hugepage(); 1179 } 1180 #define has_transparent_hugepage has_transparent_hugepage 1181 1182 static inline unsigned long 1183 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1184 unsigned long clr, unsigned long set) 1185 { 1186 if (radix_enabled()) 1187 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1188 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1189 } 1190 1191 /* 1192 * returns true for pmd migration entries, THP, devmap, hugetlb 1193 * But compile time dependent on THP config 1194 */ 1195 static inline int pmd_large(pmd_t pmd) 1196 { 1197 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1198 } 1199 1200 /* 1201 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1202 * the below will work for radix too 1203 */ 1204 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1205 unsigned long addr, pmd_t *pmdp) 1206 { 1207 unsigned long old; 1208 1209 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1210 return 0; 1211 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1212 return ((old & _PAGE_ACCESSED) != 0); 1213 } 1214 1215 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1216 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1217 pmd_t *pmdp) 1218 { 1219 if (__pmd_write((*pmdp))) 1220 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1221 else if (unlikely(pmd_savedwrite(*pmdp))) 1222 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1223 } 1224 1225 /* 1226 * Only returns true for a THP. False for pmd migration entry. 1227 * We also need to return true when we come across a pte that 1228 * in between a thp split. While splitting THP, we mark the pmd 1229 * invalid (pmdp_invalidate()) before we set it with pte page 1230 * address. A pmd_trans_huge() check against a pmd entry during that time 1231 * should return true. 1232 * We should not call this on a hugetlb entry. We should check for HugeTLB 1233 * entry using vma->vm_flags 1234 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1235 */ 1236 static inline int pmd_trans_huge(pmd_t pmd) 1237 { 1238 if (!pmd_present(pmd)) 1239 return false; 1240 1241 if (radix_enabled()) 1242 return radix__pmd_trans_huge(pmd); 1243 return hash__pmd_trans_huge(pmd); 1244 } 1245 1246 #define __HAVE_ARCH_PMD_SAME 1247 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1248 { 1249 if (radix_enabled()) 1250 return radix__pmd_same(pmd_a, pmd_b); 1251 return hash__pmd_same(pmd_a, pmd_b); 1252 } 1253 1254 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1255 { 1256 if (radix_enabled()) 1257 return radix__pmd_mkhuge(pmd); 1258 return hash__pmd_mkhuge(pmd); 1259 } 1260 1261 /* 1262 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1263 */ 1264 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1265 { 1266 #ifdef CONFIG_DEBUG_VM 1267 if (radix_enabled()) 1268 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1269 else 1270 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1271 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1272 #endif 1273 return pmd; 1274 } 1275 1276 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1277 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1278 unsigned long address, pmd_t *pmdp, 1279 pmd_t entry, int dirty); 1280 1281 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1282 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1283 unsigned long address, pmd_t *pmdp); 1284 1285 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1286 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1287 unsigned long addr, pmd_t *pmdp) 1288 { 1289 if (radix_enabled()) 1290 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1291 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1292 } 1293 1294 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1295 unsigned long address, pmd_t *pmdp) 1296 { 1297 if (radix_enabled()) 1298 return radix__pmdp_collapse_flush(vma, address, pmdp); 1299 return hash__pmdp_collapse_flush(vma, address, pmdp); 1300 } 1301 #define pmdp_collapse_flush pmdp_collapse_flush 1302 1303 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1304 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1305 unsigned long addr, 1306 pmd_t *pmdp, int full); 1307 1308 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1309 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1310 pmd_t *pmdp, pgtable_t pgtable) 1311 { 1312 if (radix_enabled()) 1313 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1314 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1315 } 1316 1317 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1318 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1319 pmd_t *pmdp) 1320 { 1321 if (radix_enabled()) 1322 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1323 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1324 } 1325 1326 #define __HAVE_ARCH_PMDP_INVALIDATE 1327 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1328 pmd_t *pmdp); 1329 1330 #define pmd_move_must_withdraw pmd_move_must_withdraw 1331 struct spinlock; 1332 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1333 struct spinlock *old_pmd_ptl, 1334 struct vm_area_struct *vma); 1335 /* 1336 * Hash translation mode use the deposited table to store hash pte 1337 * slot information. 1338 */ 1339 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1340 static inline bool arch_needs_pgtable_deposit(void) 1341 { 1342 if (radix_enabled()) 1343 return false; 1344 return true; 1345 } 1346 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1347 1348 1349 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1350 { 1351 if (radix_enabled()) 1352 return radix__pmd_mkdevmap(pmd); 1353 return hash__pmd_mkdevmap(pmd); 1354 } 1355 1356 static inline int pmd_devmap(pmd_t pmd) 1357 { 1358 return pte_devmap(pmd_pte(pmd)); 1359 } 1360 1361 static inline int pud_devmap(pud_t pud) 1362 { 1363 return 0; 1364 } 1365 1366 static inline int pgd_devmap(pgd_t pgd) 1367 { 1368 return 0; 1369 } 1370 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1371 1372 static inline int pud_pfn(pud_t pud) 1373 { 1374 /* 1375 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1376 * check so this should never be used. If it grows another user we 1377 * want to know about it. 1378 */ 1379 BUILD_BUG(); 1380 return 0; 1381 } 1382 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1383 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1384 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1385 pte_t *, pte_t, pte_t); 1386 1387 /* 1388 * Returns true for a R -> RW upgrade of pte 1389 */ 1390 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1391 { 1392 if (!(old_val & _PAGE_READ)) 1393 return false; 1394 1395 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1396 return true; 1397 1398 return false; 1399 } 1400 1401 /* 1402 * Like pmd_huge() and pmd_large(), but works regardless of config options 1403 */ 1404 #define pmd_is_leaf pmd_is_leaf 1405 #define pmd_leaf pmd_is_leaf 1406 static inline bool pmd_is_leaf(pmd_t pmd) 1407 { 1408 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1409 } 1410 1411 #define pud_is_leaf pud_is_leaf 1412 #define pud_leaf pud_is_leaf 1413 static inline bool pud_is_leaf(pud_t pud) 1414 { 1415 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1416 } 1417 1418 #define p4d_is_leaf p4d_is_leaf 1419 #define p4d_leaf p4d_is_leaf 1420 static inline bool p4d_is_leaf(p4d_t p4d) 1421 { 1422 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PTE)); 1423 } 1424 1425 #endif /* __ASSEMBLY__ */ 1426 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1427