1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #include <linux/sizes.h> 11 #endif 12 13 /* 14 * Common bits between hash and Radix page table 15 */ 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x00040UL 36 37 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 38 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 39 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 40 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 41 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 42 43 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 44 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 45 /* 46 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 47 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 48 * differentiate between two use a SW field when invalidating. 49 * 50 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 51 * 52 * This is used only when _PAGE_PRESENT is cleared. 53 */ 54 #define _PAGE_INVALID _RPAGE_SW0 55 56 /* 57 * Top and bottom bits of RPN which can be used by hash 58 * translation mode, because we expect them to be zero 59 * otherwise. 60 */ 61 #define _RPAGE_RPN0 0x01000 62 #define _RPAGE_RPN1 0x02000 63 #define _RPAGE_RPN43 0x0080000000000000UL 64 #define _RPAGE_RPN42 0x0040000000000000UL 65 #define _RPAGE_RPN41 0x0020000000000000UL 66 67 /* Max physical address bit as per radix table */ 68 #define _RPAGE_PA_MAX 56 69 70 /* 71 * Max physical address bit we will use for now. 72 * 73 * This is mostly a hardware limitation and for now Power9 has 74 * a 51 bit limit. 75 * 76 * This is different from the number of physical bit required to address 77 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 78 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 79 * number of sections we can support (SECTIONS_SHIFT). 80 * 81 * This is different from Radix page table limitation above and 82 * should always be less than that. The limit is done such that 83 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 84 * for hash linux page table specific bits. 85 * 86 * In order to be compatible with future hardware generations we keep 87 * some offsets and limit this for now to 53 88 */ 89 #define _PAGE_PA_MAX 53 90 91 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 92 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 93 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) 120 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 121 /* 122 * _PAGE_CHG_MASK masks of bits that are to be preserved across 123 * pgprot changes 124 */ 125 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 126 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 127 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 128 129 /* 130 * We define 2 sets of base prot bits, one for basic pages (ie, 131 * cacheable kernel and user pages) and one for non cacheable 132 * pages. We always set _PAGE_COHERENT when SMP is enabled or 133 * the processor might need it for DMA coherency. 134 */ 135 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 136 #define _PAGE_BASE (_PAGE_BASE_NC) 137 138 /* Permission masks used to generate the __P and __S table, 139 * 140 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 141 * 142 * Write permissions imply read permissions for now (we could make write-only 143 * pages on BookE but we don't bother for now). Execute permission control is 144 * possible on platforms that define _PAGE_EXEC 145 */ 146 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 147 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 148 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 149 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 150 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 151 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 152 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 153 /* Radix only, Hash uses PAGE_READONLY_X + execute-only pkey instead */ 154 #define PAGE_EXECONLY __pgprot(_PAGE_BASE | _PAGE_EXEC) 155 156 /* Permission masks used for kernel mappings */ 157 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 158 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT) 159 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT) 160 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 161 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 162 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 163 164 #ifndef __ASSEMBLY__ 165 /* 166 * page table defines 167 */ 168 extern unsigned long __pte_index_size; 169 extern unsigned long __pmd_index_size; 170 extern unsigned long __pud_index_size; 171 extern unsigned long __pgd_index_size; 172 extern unsigned long __pud_cache_index; 173 #define PTE_INDEX_SIZE __pte_index_size 174 #define PMD_INDEX_SIZE __pmd_index_size 175 #define PUD_INDEX_SIZE __pud_index_size 176 #define PGD_INDEX_SIZE __pgd_index_size 177 /* pmd table use page table fragments */ 178 #define PMD_CACHE_INDEX 0 179 #define PUD_CACHE_INDEX __pud_cache_index 180 /* 181 * Because of use of pte fragments and THP, size of page table 182 * are not always derived out of index size above. 183 */ 184 extern unsigned long __pte_table_size; 185 extern unsigned long __pmd_table_size; 186 extern unsigned long __pud_table_size; 187 extern unsigned long __pgd_table_size; 188 #define PTE_TABLE_SIZE __pte_table_size 189 #define PMD_TABLE_SIZE __pmd_table_size 190 #define PUD_TABLE_SIZE __pud_table_size 191 #define PGD_TABLE_SIZE __pgd_table_size 192 193 extern unsigned long __pmd_val_bits; 194 extern unsigned long __pud_val_bits; 195 extern unsigned long __pgd_val_bits; 196 #define PMD_VAL_BITS __pmd_val_bits 197 #define PUD_VAL_BITS __pud_val_bits 198 #define PGD_VAL_BITS __pgd_val_bits 199 200 extern unsigned long __pte_frag_nr; 201 #define PTE_FRAG_NR __pte_frag_nr 202 extern unsigned long __pte_frag_size_shift; 203 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 204 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 205 206 extern unsigned long __pmd_frag_nr; 207 #define PMD_FRAG_NR __pmd_frag_nr 208 extern unsigned long __pmd_frag_size_shift; 209 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 210 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 211 212 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 213 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 214 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 215 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 216 217 #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE) 218 #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD) 219 #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD) 220 #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ 221 H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) 222 223 /* PMD_SHIFT determines what a second-level page table entry can map */ 224 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 225 #define PMD_SIZE (1UL << PMD_SHIFT) 226 #define PMD_MASK (~(PMD_SIZE-1)) 227 228 /* PUD_SHIFT determines what a third-level page table entry can map */ 229 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 230 #define PUD_SIZE (1UL << PUD_SHIFT) 231 #define PUD_MASK (~(PUD_SIZE-1)) 232 233 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 234 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 235 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 236 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 237 238 /* Bits to mask out from a PMD to get to the PTE page */ 239 #define PMD_MASKED_BITS 0xc0000000000000ffUL 240 /* Bits to mask out from a PUD to get to the PMD page */ 241 #define PUD_MASKED_BITS 0xc0000000000000ffUL 242 /* Bits to mask out from a PGD to get to the PUD page */ 243 #define P4D_MASKED_BITS 0xc0000000000000ffUL 244 245 /* 246 * Used as an indicator for rcu callback functions 247 */ 248 enum pgtable_index { 249 PTE_INDEX = 0, 250 PMD_INDEX, 251 PUD_INDEX, 252 PGD_INDEX, 253 /* 254 * Below are used with 4k page size and hugetlb 255 */ 256 HTLB_16M_INDEX, 257 HTLB_16G_INDEX, 258 }; 259 260 extern unsigned long __vmalloc_start; 261 extern unsigned long __vmalloc_end; 262 #define VMALLOC_START __vmalloc_start 263 #define VMALLOC_END __vmalloc_end 264 265 static inline unsigned int ioremap_max_order(void) 266 { 267 if (radix_enabled()) 268 return PUD_SHIFT; 269 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 270 } 271 #define IOREMAP_MAX_ORDER ioremap_max_order() 272 273 extern unsigned long __kernel_virt_start; 274 extern unsigned long __kernel_io_start; 275 extern unsigned long __kernel_io_end; 276 #define KERN_VIRT_START __kernel_virt_start 277 #define KERN_IO_START __kernel_io_start 278 #define KERN_IO_END __kernel_io_end 279 280 extern struct page *vmemmap; 281 extern unsigned long pci_io_base; 282 #endif /* __ASSEMBLY__ */ 283 284 #include <asm/book3s/64/hash.h> 285 #include <asm/book3s/64/radix.h> 286 287 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 288 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 289 #else 290 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 291 #endif 292 293 294 #ifdef CONFIG_PPC_64K_PAGES 295 #include <asm/book3s/64/pgtable-64k.h> 296 #else 297 #include <asm/book3s/64/pgtable-4k.h> 298 #endif 299 300 #include <asm/barrier.h> 301 /* 302 * IO space itself carved into the PIO region (ISA and PHB IO space) and 303 * the ioremap space 304 * 305 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 306 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 307 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 308 */ 309 #define FULL_IO_SIZE 0x80000000ul 310 #define ISA_IO_BASE (KERN_IO_START) 311 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 312 #define PHB_IO_BASE (ISA_IO_END) 313 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 314 #define IOREMAP_BASE (PHB_IO_END) 315 #define IOREMAP_START (ioremap_bot) 316 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) 317 #define FIXADDR_SIZE SZ_32M 318 319 #ifndef __ASSEMBLY__ 320 321 /* 322 * This is the default implementation of various PTE accessors, it's 323 * used in all cases except Book3S with 64K pages where we have a 324 * concept of sub-pages 325 */ 326 #ifndef __real_pte 327 328 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 329 #define __rpte_to_pte(r) ((r).pte) 330 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 331 332 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 333 do { \ 334 index = 0; \ 335 shift = mmu_psize_defs[psize].shift; \ 336 337 #define pte_iterate_hashed_end() } while(0) 338 339 /* 340 * We expect this to be called only for user addresses or kernel virtual 341 * addresses other than the linear mapping. 342 */ 343 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 344 345 #endif /* __real_pte */ 346 347 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 348 pte_t *ptep, unsigned long clr, 349 unsigned long set, int huge) 350 { 351 if (radix_enabled()) 352 return radix__pte_update(mm, addr, ptep, clr, set, huge); 353 return hash__pte_update(mm, addr, ptep, clr, set, huge); 354 } 355 /* 356 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 357 * We currently remove entries from the hashtable regardless of whether 358 * the entry was young or dirty. 359 * 360 * We should be more intelligent about this but for the moment we override 361 * these functions and force a tlb flush unconditionally 362 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 363 * function for both hash and radix. 364 */ 365 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 366 unsigned long addr, pte_t *ptep) 367 { 368 unsigned long old; 369 370 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 371 return 0; 372 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 373 return (old & _PAGE_ACCESSED) != 0; 374 } 375 376 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 377 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 378 ({ \ 379 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 380 }) 381 382 /* 383 * On Book3S CPUs, clearing the accessed bit without a TLB flush 384 * doesn't cause data corruption. [ It could cause incorrect 385 * page aging and the (mistaken) reclaim of hot pages, but the 386 * chance of that should be relatively low. ] 387 * 388 * So as a performance optimization don't flush the TLB when 389 * clearing the accessed bit, it will eventually be flushed by 390 * a context switch or a VM operation anyway. [ In the rare 391 * event of it not getting flushed for a long time the delay 392 * shouldn't really matter because there's no real memory 393 * pressure for swapout to react to. ] 394 * 395 * Note: this optimisation also exists in pte_needs_flush() and 396 * huge_pmd_needs_flush(). 397 */ 398 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 399 #define ptep_clear_flush_young ptep_test_and_clear_young 400 401 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 402 #define pmdp_clear_flush_young pmdp_test_and_clear_young 403 404 static inline int pte_write(pte_t pte) 405 { 406 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 407 } 408 409 static inline int pte_read(pte_t pte) 410 { 411 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 412 } 413 414 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 415 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 416 pte_t *ptep) 417 { 418 if (pte_write(*ptep)) 419 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 420 } 421 422 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 423 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 424 unsigned long addr, pte_t *ptep) 425 { 426 if (pte_write(*ptep)) 427 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 428 } 429 430 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 431 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 432 unsigned long addr, pte_t *ptep) 433 { 434 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 435 return __pte(old); 436 } 437 438 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 439 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 440 unsigned long addr, 441 pte_t *ptep, int full) 442 { 443 if (full && radix_enabled()) { 444 /* 445 * We know that this is a full mm pte clear and 446 * hence can be sure there is no parallel set_pte. 447 */ 448 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 449 } 450 return ptep_get_and_clear(mm, addr, ptep); 451 } 452 453 454 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 455 pte_t * ptep) 456 { 457 pte_update(mm, addr, ptep, ~0UL, 0, 0); 458 } 459 460 static inline int pte_dirty(pte_t pte) 461 { 462 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 463 } 464 465 static inline int pte_young(pte_t pte) 466 { 467 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 468 } 469 470 static inline int pte_special(pte_t pte) 471 { 472 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 473 } 474 475 static inline bool pte_exec(pte_t pte) 476 { 477 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 478 } 479 480 481 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 482 static inline bool pte_soft_dirty(pte_t pte) 483 { 484 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 485 } 486 487 static inline pte_t pte_mksoft_dirty(pte_t pte) 488 { 489 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 490 } 491 492 static inline pte_t pte_clear_soft_dirty(pte_t pte) 493 { 494 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 495 } 496 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 497 498 #ifdef CONFIG_NUMA_BALANCING 499 static inline int pte_protnone(pte_t pte) 500 { 501 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 502 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 503 } 504 #endif /* CONFIG_NUMA_BALANCING */ 505 506 static inline bool pte_hw_valid(pte_t pte) 507 { 508 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 509 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 510 } 511 512 static inline int pte_present(pte_t pte) 513 { 514 /* 515 * A pte is considerent present if _PAGE_PRESENT is set. 516 * We also need to consider the pte present which is marked 517 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 518 * if we find _PAGE_PRESENT cleared. 519 */ 520 521 if (pte_hw_valid(pte)) 522 return true; 523 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 524 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 525 } 526 527 #ifdef CONFIG_PPC_MEM_KEYS 528 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 529 #else 530 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 531 { 532 return true; 533 } 534 #endif /* CONFIG_PPC_MEM_KEYS */ 535 536 static inline bool pte_user(pte_t pte) 537 { 538 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 539 } 540 541 #define pte_access_permitted pte_access_permitted 542 static inline bool pte_access_permitted(pte_t pte, bool write) 543 { 544 /* 545 * _PAGE_READ is needed for any access and will be 546 * cleared for PROT_NONE 547 */ 548 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 549 return false; 550 551 if (write && !pte_write(pte)) 552 return false; 553 554 return arch_pte_access_permitted(pte_val(pte), write, 0); 555 } 556 557 /* 558 * Conversion functions: convert a page and protection to a page entry, 559 * and a page entry and page directory to the page they refer to. 560 * 561 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 562 * long for now. 563 */ 564 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 565 { 566 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 567 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 568 569 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 570 } 571 572 static inline unsigned long pte_pfn(pte_t pte) 573 { 574 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 575 } 576 577 /* Generic modifiers for PTE bits */ 578 static inline pte_t pte_wrprotect(pte_t pte) 579 { 580 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 581 } 582 583 static inline pte_t pte_exprotect(pte_t pte) 584 { 585 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 586 } 587 588 static inline pte_t pte_mkclean(pte_t pte) 589 { 590 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 591 } 592 593 static inline pte_t pte_mkold(pte_t pte) 594 { 595 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 596 } 597 598 static inline pte_t pte_mkexec(pte_t pte) 599 { 600 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 601 } 602 603 static inline pte_t pte_mkwrite(pte_t pte) 604 { 605 /* 606 * write implies read, hence set both 607 */ 608 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 609 } 610 611 static inline pte_t pte_mkdirty(pte_t pte) 612 { 613 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 614 } 615 616 static inline pte_t pte_mkyoung(pte_t pte) 617 { 618 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 619 } 620 621 static inline pte_t pte_mkspecial(pte_t pte) 622 { 623 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 624 } 625 626 static inline pte_t pte_mkhuge(pte_t pte) 627 { 628 return pte; 629 } 630 631 static inline pte_t pte_mkdevmap(pte_t pte) 632 { 633 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 634 } 635 636 static inline pte_t pte_mkprivileged(pte_t pte) 637 { 638 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 639 } 640 641 static inline pte_t pte_mkuser(pte_t pte) 642 { 643 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 644 } 645 646 /* 647 * This is potentially called with a pmd as the argument, in which case it's not 648 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 649 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 650 * use in page directory entries (ie. non-ptes). 651 */ 652 static inline int pte_devmap(pte_t pte) 653 { 654 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 655 656 return (pte_raw(pte) & mask) == mask; 657 } 658 659 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 660 { 661 /* FIXME!! check whether this need to be a conditional */ 662 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 663 cpu_to_be64(pgprot_val(newprot))); 664 } 665 666 /* Encode and de-code a swap entry */ 667 #define MAX_SWAPFILES_CHECK() do { \ 668 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 669 /* \ 670 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 671 * We filter HPTEFLAGS on set_pte. \ 672 */ \ 673 BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ 674 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 675 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ 676 } while (0) 677 678 #define SWP_TYPE_BITS 5 679 #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) 680 #define __swp_type(x) ((x).val & SWP_TYPE_MASK) 681 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 682 #define __swp_entry(type, offset) ((swp_entry_t) { \ 683 (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 684 /* 685 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 686 * swap type and offset we get from swap and convert that to pte to find a 687 * matching pte in linux page table. 688 * Clear bits not found in swap entries here. 689 */ 690 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 691 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 692 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 693 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 694 695 #ifdef CONFIG_MEM_SOFT_DIRTY 696 #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY 697 #else 698 #define _PAGE_SWP_SOFT_DIRTY 0UL 699 #endif /* CONFIG_MEM_SOFT_DIRTY */ 700 701 #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT 702 703 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 704 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 705 { 706 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 707 } 708 709 static inline bool pte_swp_soft_dirty(pte_t pte) 710 { 711 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 712 } 713 714 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 715 { 716 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 717 } 718 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 719 720 #define __HAVE_ARCH_PTE_SWP_EXCLUSIVE 721 static inline pte_t pte_swp_mkexclusive(pte_t pte) 722 { 723 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 724 } 725 726 static inline int pte_swp_exclusive(pte_t pte) 727 { 728 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 729 } 730 731 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 732 { 733 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); 734 } 735 736 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 737 { 738 /* 739 * This check for _PAGE_RWX and _PAGE_PRESENT bits 740 */ 741 if (access & ~ptev) 742 return false; 743 /* 744 * This check for access to privilege space 745 */ 746 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 747 return false; 748 749 return true; 750 } 751 /* 752 * Generic functions with hash/radix callbacks 753 */ 754 755 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 756 pte_t *ptep, pte_t entry, 757 unsigned long address, 758 int psize) 759 { 760 if (radix_enabled()) 761 return radix__ptep_set_access_flags(vma, ptep, entry, 762 address, psize); 763 return hash__ptep_set_access_flags(ptep, entry); 764 } 765 766 #define __HAVE_ARCH_PTE_SAME 767 static inline int pte_same(pte_t pte_a, pte_t pte_b) 768 { 769 if (radix_enabled()) 770 return radix__pte_same(pte_a, pte_b); 771 return hash__pte_same(pte_a, pte_b); 772 } 773 774 static inline int pte_none(pte_t pte) 775 { 776 if (radix_enabled()) 777 return radix__pte_none(pte); 778 return hash__pte_none(pte); 779 } 780 781 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 782 pte_t *ptep, pte_t pte, int percpu) 783 { 784 785 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 786 /* 787 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 788 * in all the callers. 789 */ 790 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 791 792 if (radix_enabled()) 793 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 794 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 795 } 796 797 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 798 799 #define pgprot_noncached pgprot_noncached 800 static inline pgprot_t pgprot_noncached(pgprot_t prot) 801 { 802 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 803 _PAGE_NON_IDEMPOTENT); 804 } 805 806 #define pgprot_noncached_wc pgprot_noncached_wc 807 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 808 { 809 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 810 _PAGE_TOLERANT); 811 } 812 813 #define pgprot_cached pgprot_cached 814 static inline pgprot_t pgprot_cached(pgprot_t prot) 815 { 816 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 817 } 818 819 #define pgprot_writecombine pgprot_writecombine 820 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 821 { 822 return pgprot_noncached_wc(prot); 823 } 824 /* 825 * check a pte mapping have cache inhibited property 826 */ 827 static inline bool pte_ci(pte_t pte) 828 { 829 __be64 pte_v = pte_raw(pte); 830 831 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 832 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 833 return true; 834 return false; 835 } 836 837 static inline void pmd_clear(pmd_t *pmdp) 838 { 839 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 840 /* 841 * Don't use this if we can possibly have a hash page table 842 * entry mapping this. 843 */ 844 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 845 } 846 *pmdp = __pmd(0); 847 } 848 849 static inline int pmd_none(pmd_t pmd) 850 { 851 return !pmd_raw(pmd); 852 } 853 854 static inline int pmd_present(pmd_t pmd) 855 { 856 /* 857 * A pmd is considerent present if _PAGE_PRESENT is set. 858 * We also need to consider the pmd present which is marked 859 * invalid during a split. Hence we look for _PAGE_INVALID 860 * if we find _PAGE_PRESENT cleared. 861 */ 862 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 863 return true; 864 865 return false; 866 } 867 868 static inline int pmd_is_serializing(pmd_t pmd) 869 { 870 /* 871 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 872 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 873 * 874 * This condition may also occur when flushing a pmd while flushing 875 * it (see ptep_modify_prot_start), so callers must ensure this 876 * case is fine as well. 877 */ 878 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 879 cpu_to_be64(_PAGE_INVALID)) 880 return true; 881 882 return false; 883 } 884 885 static inline int pmd_bad(pmd_t pmd) 886 { 887 if (radix_enabled()) 888 return radix__pmd_bad(pmd); 889 return hash__pmd_bad(pmd); 890 } 891 892 static inline void pud_clear(pud_t *pudp) 893 { 894 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 895 /* 896 * Don't use this if we can possibly have a hash page table 897 * entry mapping this. 898 */ 899 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 900 } 901 *pudp = __pud(0); 902 } 903 904 static inline int pud_none(pud_t pud) 905 { 906 return !pud_raw(pud); 907 } 908 909 static inline int pud_present(pud_t pud) 910 { 911 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 912 } 913 914 extern struct page *pud_page(pud_t pud); 915 extern struct page *pmd_page(pmd_t pmd); 916 static inline pte_t pud_pte(pud_t pud) 917 { 918 return __pte_raw(pud_raw(pud)); 919 } 920 921 static inline pud_t pte_pud(pte_t pte) 922 { 923 return __pud_raw(pte_raw(pte)); 924 } 925 #define pud_write(pud) pte_write(pud_pte(pud)) 926 927 static inline int pud_bad(pud_t pud) 928 { 929 if (radix_enabled()) 930 return radix__pud_bad(pud); 931 return hash__pud_bad(pud); 932 } 933 934 #define pud_access_permitted pud_access_permitted 935 static inline bool pud_access_permitted(pud_t pud, bool write) 936 { 937 return pte_access_permitted(pud_pte(pud), write); 938 } 939 940 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 941 static inline __be64 p4d_raw(p4d_t x) 942 { 943 return pgd_raw(x.pgd); 944 } 945 946 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 947 948 static inline void p4d_clear(p4d_t *p4dp) 949 { 950 *p4dp = __p4d(0); 951 } 952 953 static inline int p4d_none(p4d_t p4d) 954 { 955 return !p4d_raw(p4d); 956 } 957 958 static inline int p4d_present(p4d_t p4d) 959 { 960 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 961 } 962 963 static inline pte_t p4d_pte(p4d_t p4d) 964 { 965 return __pte_raw(p4d_raw(p4d)); 966 } 967 968 static inline p4d_t pte_p4d(pte_t pte) 969 { 970 return __p4d_raw(pte_raw(pte)); 971 } 972 973 static inline int p4d_bad(p4d_t p4d) 974 { 975 if (radix_enabled()) 976 return radix__p4d_bad(p4d); 977 return hash__p4d_bad(p4d); 978 } 979 980 #define p4d_access_permitted p4d_access_permitted 981 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 982 { 983 return pte_access_permitted(p4d_pte(p4d), write); 984 } 985 986 extern struct page *p4d_page(p4d_t p4d); 987 988 /* Pointers in the page table tree are physical addresses */ 989 #define __pgtable_ptr_val(ptr) __pa(ptr) 990 991 static inline pud_t *p4d_pgtable(p4d_t p4d) 992 { 993 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); 994 } 995 996 static inline pmd_t *pud_pgtable(pud_t pud) 997 { 998 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); 999 } 1000 1001 #define pte_ERROR(e) \ 1002 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1003 #define pmd_ERROR(e) \ 1004 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1005 #define pud_ERROR(e) \ 1006 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1007 #define pgd_ERROR(e) \ 1008 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1009 1010 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1011 { 1012 if (radix_enabled()) { 1013 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1014 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1015 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1016 #endif 1017 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1018 } 1019 return hash__map_kernel_page(ea, pa, prot); 1020 } 1021 1022 void unmap_kernel_page(unsigned long va); 1023 1024 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1025 unsigned long page_size, 1026 unsigned long phys) 1027 { 1028 if (radix_enabled()) 1029 return radix__vmemmap_create_mapping(start, page_size, phys); 1030 return hash__vmemmap_create_mapping(start, page_size, phys); 1031 } 1032 1033 #ifdef CONFIG_MEMORY_HOTPLUG 1034 static inline void vmemmap_remove_mapping(unsigned long start, 1035 unsigned long page_size) 1036 { 1037 if (radix_enabled()) 1038 return radix__vmemmap_remove_mapping(start, page_size); 1039 return hash__vmemmap_remove_mapping(start, page_size); 1040 } 1041 #endif 1042 1043 #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE) 1044 static inline void __kernel_map_pages(struct page *page, int numpages, int enable) 1045 { 1046 if (radix_enabled()) 1047 radix__kernel_map_pages(page, numpages, enable); 1048 else 1049 hash__kernel_map_pages(page, numpages, enable); 1050 } 1051 #endif 1052 1053 static inline pte_t pmd_pte(pmd_t pmd) 1054 { 1055 return __pte_raw(pmd_raw(pmd)); 1056 } 1057 1058 static inline pmd_t pte_pmd(pte_t pte) 1059 { 1060 return __pmd_raw(pte_raw(pte)); 1061 } 1062 1063 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1064 { 1065 return (pte_t *)pmd; 1066 } 1067 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1068 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1069 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1070 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1071 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1072 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1073 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1074 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1075 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1076 1077 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1078 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1079 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1080 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1081 1082 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1083 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1084 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1085 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1086 #endif 1087 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1088 1089 #ifdef CONFIG_NUMA_BALANCING 1090 static inline int pmd_protnone(pmd_t pmd) 1091 { 1092 return pte_protnone(pmd_pte(pmd)); 1093 } 1094 #endif /* CONFIG_NUMA_BALANCING */ 1095 1096 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1097 1098 #define pmd_access_permitted pmd_access_permitted 1099 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1100 { 1101 /* 1102 * pmdp_invalidate sets this combination (which is not caught by 1103 * !pte_present() check in pte_access_permitted), to prevent 1104 * lock-free lookups, as part of the serialize_against_pte_lookup() 1105 * synchronisation. 1106 * 1107 * This also catches the case where the PTE's hardware PRESENT bit is 1108 * cleared while TLB is flushed, which is suboptimal but should not 1109 * be frequent. 1110 */ 1111 if (pmd_is_serializing(pmd)) 1112 return false; 1113 1114 return pte_access_permitted(pmd_pte(pmd), write); 1115 } 1116 1117 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1118 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1119 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1120 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1121 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1122 pmd_t *pmdp, pmd_t pmd); 1123 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1124 unsigned long addr, pmd_t *pmd) 1125 { 1126 } 1127 1128 extern int hash__has_transparent_hugepage(void); 1129 static inline int has_transparent_hugepage(void) 1130 { 1131 if (radix_enabled()) 1132 return radix__has_transparent_hugepage(); 1133 return hash__has_transparent_hugepage(); 1134 } 1135 #define has_transparent_hugepage has_transparent_hugepage 1136 1137 static inline unsigned long 1138 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1139 unsigned long clr, unsigned long set) 1140 { 1141 if (radix_enabled()) 1142 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1143 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1144 } 1145 1146 /* 1147 * returns true for pmd migration entries, THP, devmap, hugetlb 1148 * But compile time dependent on THP config 1149 */ 1150 static inline int pmd_large(pmd_t pmd) 1151 { 1152 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1153 } 1154 1155 /* 1156 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1157 * the below will work for radix too 1158 */ 1159 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1160 unsigned long addr, pmd_t *pmdp) 1161 { 1162 unsigned long old; 1163 1164 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1165 return 0; 1166 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1167 return ((old & _PAGE_ACCESSED) != 0); 1168 } 1169 1170 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1171 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1172 pmd_t *pmdp) 1173 { 1174 if (pmd_write(*pmdp)) 1175 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1176 } 1177 1178 /* 1179 * Only returns true for a THP. False for pmd migration entry. 1180 * We also need to return true when we come across a pte that 1181 * in between a thp split. While splitting THP, we mark the pmd 1182 * invalid (pmdp_invalidate()) before we set it with pte page 1183 * address. A pmd_trans_huge() check against a pmd entry during that time 1184 * should return true. 1185 * We should not call this on a hugetlb entry. We should check for HugeTLB 1186 * entry using vma->vm_flags 1187 * The page table walk rule is explained in Documentation/mm/transhuge.rst 1188 */ 1189 static inline int pmd_trans_huge(pmd_t pmd) 1190 { 1191 if (!pmd_present(pmd)) 1192 return false; 1193 1194 if (radix_enabled()) 1195 return radix__pmd_trans_huge(pmd); 1196 return hash__pmd_trans_huge(pmd); 1197 } 1198 1199 #define __HAVE_ARCH_PMD_SAME 1200 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1201 { 1202 if (radix_enabled()) 1203 return radix__pmd_same(pmd_a, pmd_b); 1204 return hash__pmd_same(pmd_a, pmd_b); 1205 } 1206 1207 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1208 { 1209 if (radix_enabled()) 1210 return radix__pmd_mkhuge(pmd); 1211 return hash__pmd_mkhuge(pmd); 1212 } 1213 1214 /* 1215 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1216 */ 1217 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1218 { 1219 #ifdef CONFIG_DEBUG_VM 1220 if (radix_enabled()) 1221 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1222 else 1223 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1224 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1225 #endif 1226 return pmd; 1227 } 1228 1229 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1230 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1231 unsigned long address, pmd_t *pmdp, 1232 pmd_t entry, int dirty); 1233 1234 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1235 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1236 unsigned long address, pmd_t *pmdp); 1237 1238 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1239 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1240 unsigned long addr, pmd_t *pmdp) 1241 { 1242 if (radix_enabled()) 1243 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1244 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1245 } 1246 1247 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1248 unsigned long address, pmd_t *pmdp) 1249 { 1250 if (radix_enabled()) 1251 return radix__pmdp_collapse_flush(vma, address, pmdp); 1252 return hash__pmdp_collapse_flush(vma, address, pmdp); 1253 } 1254 #define pmdp_collapse_flush pmdp_collapse_flush 1255 1256 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1257 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1258 unsigned long addr, 1259 pmd_t *pmdp, int full); 1260 1261 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1262 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1263 pmd_t *pmdp, pgtable_t pgtable) 1264 { 1265 if (radix_enabled()) 1266 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1267 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1268 } 1269 1270 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1271 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1272 pmd_t *pmdp) 1273 { 1274 if (radix_enabled()) 1275 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1276 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1277 } 1278 1279 #define __HAVE_ARCH_PMDP_INVALIDATE 1280 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1281 pmd_t *pmdp); 1282 1283 #define pmd_move_must_withdraw pmd_move_must_withdraw 1284 struct spinlock; 1285 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1286 struct spinlock *old_pmd_ptl, 1287 struct vm_area_struct *vma); 1288 /* 1289 * Hash translation mode use the deposited table to store hash pte 1290 * slot information. 1291 */ 1292 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1293 static inline bool arch_needs_pgtable_deposit(void) 1294 { 1295 if (radix_enabled()) 1296 return false; 1297 return true; 1298 } 1299 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1300 1301 1302 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1303 { 1304 if (radix_enabled()) 1305 return radix__pmd_mkdevmap(pmd); 1306 return hash__pmd_mkdevmap(pmd); 1307 } 1308 1309 static inline int pmd_devmap(pmd_t pmd) 1310 { 1311 return pte_devmap(pmd_pte(pmd)); 1312 } 1313 1314 static inline int pud_devmap(pud_t pud) 1315 { 1316 return 0; 1317 } 1318 1319 static inline int pgd_devmap(pgd_t pgd) 1320 { 1321 return 0; 1322 } 1323 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1324 1325 static inline int pud_pfn(pud_t pud) 1326 { 1327 /* 1328 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1329 * check so this should never be used. If it grows another user we 1330 * want to know about it. 1331 */ 1332 BUILD_BUG(); 1333 return 0; 1334 } 1335 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1336 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1337 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1338 pte_t *, pte_t, pte_t); 1339 1340 /* 1341 * Returns true for a R -> RW upgrade of pte 1342 */ 1343 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1344 { 1345 if (!(old_val & _PAGE_READ)) 1346 return false; 1347 1348 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1349 return true; 1350 1351 return false; 1352 } 1353 1354 /* 1355 * Like pmd_huge() and pmd_large(), but works regardless of config options 1356 */ 1357 #define pmd_is_leaf pmd_is_leaf 1358 #define pmd_leaf pmd_is_leaf 1359 static inline bool pmd_is_leaf(pmd_t pmd) 1360 { 1361 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1362 } 1363 1364 #define pud_is_leaf pud_is_leaf 1365 #define pud_leaf pud_is_leaf 1366 static inline bool pud_is_leaf(pud_t pud) 1367 { 1368 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1369 } 1370 1371 #endif /* __ASSEMBLY__ */ 1372 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1373