1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #include <linux/sizes.h> 11 #endif 12 13 /* 14 * Common bits between hash and Radix page table 15 */ 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x00040UL 36 37 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 38 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 39 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 40 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 41 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 42 43 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 44 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 45 /* 46 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 47 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 48 * differentiate between two use a SW field when invalidating. 49 * 50 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 51 * 52 * This is used only when _PAGE_PRESENT is cleared. 53 */ 54 #define _PAGE_INVALID _RPAGE_SW0 55 56 /* 57 * Top and bottom bits of RPN which can be used by hash 58 * translation mode, because we expect them to be zero 59 * otherwise. 60 */ 61 #define _RPAGE_RPN0 0x01000 62 #define _RPAGE_RPN1 0x02000 63 #define _RPAGE_RPN43 0x0080000000000000UL 64 #define _RPAGE_RPN42 0x0040000000000000UL 65 #define _RPAGE_RPN41 0x0020000000000000UL 66 67 /* Max physical address bit as per radix table */ 68 #define _RPAGE_PA_MAX 56 69 70 /* 71 * Max physical address bit we will use for now. 72 * 73 * This is mostly a hardware limitation and for now Power9 has 74 * a 51 bit limit. 75 * 76 * This is different from the number of physical bit required to address 77 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 78 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 79 * number of sections we can support (SECTIONS_SHIFT). 80 * 81 * This is different from Radix page table limitation above and 82 * should always be less than that. The limit is done such that 83 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 84 * for hash linux page table specific bits. 85 * 86 * In order to be compatible with future hardware generations we keep 87 * some offsets and limit this for now to 53 88 */ 89 #define _PAGE_PA_MAX 53 90 91 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 92 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 93 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) 120 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 121 _PAGE_RW | _PAGE_EXEC) 122 /* 123 * _PAGE_CHG_MASK masks of bits that are to be preserved across 124 * pgprot changes 125 */ 126 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 127 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 128 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 129 130 /* 131 * We define 2 sets of base prot bits, one for basic pages (ie, 132 * cacheable kernel and user pages) and one for non cacheable 133 * pages. We always set _PAGE_COHERENT when SMP is enabled or 134 * the processor might need it for DMA coherency. 135 */ 136 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 137 #define _PAGE_BASE (_PAGE_BASE_NC) 138 139 /* Permission masks used to generate the __P and __S table, 140 * 141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 142 * 143 * Write permissions imply read permissions for now (we could make write-only 144 * pages on BookE but we don't bother for now). Execute permission control is 145 * possible on platforms that define _PAGE_EXEC 146 */ 147 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 148 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 149 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 150 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 151 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 152 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 153 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 154 /* Radix only, Hash uses PAGE_READONLY_X + execute-only pkey instead */ 155 #define PAGE_EXECONLY __pgprot(_PAGE_BASE | _PAGE_EXEC) 156 157 /* Permission masks used for kernel mappings */ 158 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 159 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 160 _PAGE_TOLERANT) 161 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 162 _PAGE_NON_IDEMPOTENT) 163 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 164 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 165 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 166 167 /* 168 * Protection used for kernel text. We want the debuggers to be able to 169 * set breakpoints anywhere, so don't write protect the kernel text 170 * on platforms where such control is possible. 171 */ 172 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 173 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 174 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 175 #else 176 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 177 #endif 178 179 /* Make modules code happy. We don't set RO yet */ 180 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 181 #define PAGE_AGP (PAGE_KERNEL_NC) 182 183 #ifndef __ASSEMBLY__ 184 /* 185 * page table defines 186 */ 187 extern unsigned long __pte_index_size; 188 extern unsigned long __pmd_index_size; 189 extern unsigned long __pud_index_size; 190 extern unsigned long __pgd_index_size; 191 extern unsigned long __pud_cache_index; 192 #define PTE_INDEX_SIZE __pte_index_size 193 #define PMD_INDEX_SIZE __pmd_index_size 194 #define PUD_INDEX_SIZE __pud_index_size 195 #define PGD_INDEX_SIZE __pgd_index_size 196 /* pmd table use page table fragments */ 197 #define PMD_CACHE_INDEX 0 198 #define PUD_CACHE_INDEX __pud_cache_index 199 /* 200 * Because of use of pte fragments and THP, size of page table 201 * are not always derived out of index size above. 202 */ 203 extern unsigned long __pte_table_size; 204 extern unsigned long __pmd_table_size; 205 extern unsigned long __pud_table_size; 206 extern unsigned long __pgd_table_size; 207 #define PTE_TABLE_SIZE __pte_table_size 208 #define PMD_TABLE_SIZE __pmd_table_size 209 #define PUD_TABLE_SIZE __pud_table_size 210 #define PGD_TABLE_SIZE __pgd_table_size 211 212 extern unsigned long __pmd_val_bits; 213 extern unsigned long __pud_val_bits; 214 extern unsigned long __pgd_val_bits; 215 #define PMD_VAL_BITS __pmd_val_bits 216 #define PUD_VAL_BITS __pud_val_bits 217 #define PGD_VAL_BITS __pgd_val_bits 218 219 extern unsigned long __pte_frag_nr; 220 #define PTE_FRAG_NR __pte_frag_nr 221 extern unsigned long __pte_frag_size_shift; 222 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 223 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 224 225 extern unsigned long __pmd_frag_nr; 226 #define PMD_FRAG_NR __pmd_frag_nr 227 extern unsigned long __pmd_frag_size_shift; 228 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 229 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 230 231 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 232 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 233 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 234 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 235 236 #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE) 237 #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD) 238 #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD) 239 #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ 240 H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) 241 242 /* PMD_SHIFT determines what a second-level page table entry can map */ 243 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 244 #define PMD_SIZE (1UL << PMD_SHIFT) 245 #define PMD_MASK (~(PMD_SIZE-1)) 246 247 /* PUD_SHIFT determines what a third-level page table entry can map */ 248 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 249 #define PUD_SIZE (1UL << PUD_SHIFT) 250 #define PUD_MASK (~(PUD_SIZE-1)) 251 252 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 253 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 254 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 255 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 256 257 /* Bits to mask out from a PMD to get to the PTE page */ 258 #define PMD_MASKED_BITS 0xc0000000000000ffUL 259 /* Bits to mask out from a PUD to get to the PMD page */ 260 #define PUD_MASKED_BITS 0xc0000000000000ffUL 261 /* Bits to mask out from a PGD to get to the PUD page */ 262 #define P4D_MASKED_BITS 0xc0000000000000ffUL 263 264 /* 265 * Used as an indicator for rcu callback functions 266 */ 267 enum pgtable_index { 268 PTE_INDEX = 0, 269 PMD_INDEX, 270 PUD_INDEX, 271 PGD_INDEX, 272 /* 273 * Below are used with 4k page size and hugetlb 274 */ 275 HTLB_16M_INDEX, 276 HTLB_16G_INDEX, 277 }; 278 279 extern unsigned long __vmalloc_start; 280 extern unsigned long __vmalloc_end; 281 #define VMALLOC_START __vmalloc_start 282 #define VMALLOC_END __vmalloc_end 283 284 static inline unsigned int ioremap_max_order(void) 285 { 286 if (radix_enabled()) 287 return PUD_SHIFT; 288 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 289 } 290 #define IOREMAP_MAX_ORDER ioremap_max_order() 291 292 extern unsigned long __kernel_virt_start; 293 extern unsigned long __kernel_io_start; 294 extern unsigned long __kernel_io_end; 295 #define KERN_VIRT_START __kernel_virt_start 296 #define KERN_IO_START __kernel_io_start 297 #define KERN_IO_END __kernel_io_end 298 299 extern struct page *vmemmap; 300 extern unsigned long pci_io_base; 301 #endif /* __ASSEMBLY__ */ 302 303 #include <asm/book3s/64/hash.h> 304 #include <asm/book3s/64/radix.h> 305 306 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 307 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 308 #else 309 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 310 #endif 311 312 313 #ifdef CONFIG_PPC_64K_PAGES 314 #include <asm/book3s/64/pgtable-64k.h> 315 #else 316 #include <asm/book3s/64/pgtable-4k.h> 317 #endif 318 319 #include <asm/barrier.h> 320 /* 321 * IO space itself carved into the PIO region (ISA and PHB IO space) and 322 * the ioremap space 323 * 324 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 325 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 326 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 327 */ 328 #define FULL_IO_SIZE 0x80000000ul 329 #define ISA_IO_BASE (KERN_IO_START) 330 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 331 #define PHB_IO_BASE (ISA_IO_END) 332 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 333 #define IOREMAP_BASE (PHB_IO_END) 334 #define IOREMAP_START (ioremap_bot) 335 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) 336 #define FIXADDR_SIZE SZ_32M 337 338 /* Advertise special mapping type for AGP */ 339 #define HAVE_PAGE_AGP 340 341 #ifndef __ASSEMBLY__ 342 343 /* 344 * This is the default implementation of various PTE accessors, it's 345 * used in all cases except Book3S with 64K pages where we have a 346 * concept of sub-pages 347 */ 348 #ifndef __real_pte 349 350 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 351 #define __rpte_to_pte(r) ((r).pte) 352 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 353 354 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 355 do { \ 356 index = 0; \ 357 shift = mmu_psize_defs[psize].shift; \ 358 359 #define pte_iterate_hashed_end() } while(0) 360 361 /* 362 * We expect this to be called only for user addresses or kernel virtual 363 * addresses other than the linear mapping. 364 */ 365 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 366 367 #endif /* __real_pte */ 368 369 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 370 pte_t *ptep, unsigned long clr, 371 unsigned long set, int huge) 372 { 373 if (radix_enabled()) 374 return radix__pte_update(mm, addr, ptep, clr, set, huge); 375 return hash__pte_update(mm, addr, ptep, clr, set, huge); 376 } 377 /* 378 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 379 * We currently remove entries from the hashtable regardless of whether 380 * the entry was young or dirty. 381 * 382 * We should be more intelligent about this but for the moment we override 383 * these functions and force a tlb flush unconditionally 384 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 385 * function for both hash and radix. 386 */ 387 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 388 unsigned long addr, pte_t *ptep) 389 { 390 unsigned long old; 391 392 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 393 return 0; 394 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 395 return (old & _PAGE_ACCESSED) != 0; 396 } 397 398 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 399 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 400 ({ \ 401 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 402 }) 403 404 /* 405 * On Book3S CPUs, clearing the accessed bit without a TLB flush 406 * doesn't cause data corruption. [ It could cause incorrect 407 * page aging and the (mistaken) reclaim of hot pages, but the 408 * chance of that should be relatively low. ] 409 * 410 * So as a performance optimization don't flush the TLB when 411 * clearing the accessed bit, it will eventually be flushed by 412 * a context switch or a VM operation anyway. [ In the rare 413 * event of it not getting flushed for a long time the delay 414 * shouldn't really matter because there's no real memory 415 * pressure for swapout to react to. ] 416 */ 417 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 418 #define ptep_clear_flush_young ptep_test_and_clear_young 419 420 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 421 #define pmdp_clear_flush_young pmdp_test_and_clear_young 422 423 static inline int __pte_write(pte_t pte) 424 { 425 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 426 } 427 428 #ifdef CONFIG_NUMA_BALANCING 429 #define pte_savedwrite pte_savedwrite 430 static inline bool pte_savedwrite(pte_t pte) 431 { 432 /* 433 * Saved write ptes are prot none ptes that doesn't have 434 * privileged bit sit. We mark prot none as one which has 435 * present and pviliged bit set and RWX cleared. To mark 436 * protnone which used to have _PAGE_WRITE set we clear 437 * the privileged bit. 438 */ 439 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 440 } 441 #else 442 #define pte_savedwrite pte_savedwrite 443 static inline bool pte_savedwrite(pte_t pte) 444 { 445 return false; 446 } 447 #endif 448 449 static inline int pte_write(pte_t pte) 450 { 451 return __pte_write(pte) || pte_savedwrite(pte); 452 } 453 454 static inline int pte_read(pte_t pte) 455 { 456 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 457 } 458 459 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 460 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 461 pte_t *ptep) 462 { 463 if (__pte_write(*ptep)) 464 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 465 else if (unlikely(pte_savedwrite(*ptep))) 466 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 467 } 468 469 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 470 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 471 unsigned long addr, pte_t *ptep) 472 { 473 /* 474 * We should not find protnone for hugetlb, but this complete the 475 * interface. 476 */ 477 if (__pte_write(*ptep)) 478 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 479 else if (unlikely(pte_savedwrite(*ptep))) 480 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 481 } 482 483 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 484 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 485 unsigned long addr, pte_t *ptep) 486 { 487 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 488 return __pte(old); 489 } 490 491 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 492 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 493 unsigned long addr, 494 pte_t *ptep, int full) 495 { 496 if (full && radix_enabled()) { 497 /* 498 * We know that this is a full mm pte clear and 499 * hence can be sure there is no parallel set_pte. 500 */ 501 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 502 } 503 return ptep_get_and_clear(mm, addr, ptep); 504 } 505 506 507 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 508 pte_t * ptep) 509 { 510 pte_update(mm, addr, ptep, ~0UL, 0, 0); 511 } 512 513 static inline int pte_dirty(pte_t pte) 514 { 515 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 516 } 517 518 static inline int pte_young(pte_t pte) 519 { 520 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 521 } 522 523 static inline int pte_special(pte_t pte) 524 { 525 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 526 } 527 528 static inline bool pte_exec(pte_t pte) 529 { 530 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 531 } 532 533 534 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 535 static inline bool pte_soft_dirty(pte_t pte) 536 { 537 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 538 } 539 540 static inline pte_t pte_mksoft_dirty(pte_t pte) 541 { 542 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 543 } 544 545 static inline pte_t pte_clear_soft_dirty(pte_t pte) 546 { 547 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 548 } 549 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 550 551 #ifdef CONFIG_NUMA_BALANCING 552 static inline int pte_protnone(pte_t pte) 553 { 554 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 555 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 556 } 557 558 #define pte_mk_savedwrite pte_mk_savedwrite 559 static inline pte_t pte_mk_savedwrite(pte_t pte) 560 { 561 /* 562 * Used by Autonuma subsystem to preserve the write bit 563 * while marking the pte PROT_NONE. Only allow this 564 * on PROT_NONE pte 565 */ 566 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 567 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 568 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 569 } 570 571 #define pte_clear_savedwrite pte_clear_savedwrite 572 static inline pte_t pte_clear_savedwrite(pte_t pte) 573 { 574 /* 575 * Used by KSM subsystem to make a protnone pte readonly. 576 */ 577 VM_BUG_ON(!pte_protnone(pte)); 578 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 579 } 580 #else 581 #define pte_clear_savedwrite pte_clear_savedwrite 582 static inline pte_t pte_clear_savedwrite(pte_t pte) 583 { 584 VM_WARN_ON(1); 585 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 586 } 587 #endif /* CONFIG_NUMA_BALANCING */ 588 589 static inline bool pte_hw_valid(pte_t pte) 590 { 591 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 592 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 593 } 594 595 static inline int pte_present(pte_t pte) 596 { 597 /* 598 * A pte is considerent present if _PAGE_PRESENT is set. 599 * We also need to consider the pte present which is marked 600 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 601 * if we find _PAGE_PRESENT cleared. 602 */ 603 604 if (pte_hw_valid(pte)) 605 return true; 606 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 607 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 608 } 609 610 #ifdef CONFIG_PPC_MEM_KEYS 611 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 612 #else 613 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 614 { 615 return true; 616 } 617 #endif /* CONFIG_PPC_MEM_KEYS */ 618 619 static inline bool pte_user(pte_t pte) 620 { 621 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 622 } 623 624 #define pte_access_permitted pte_access_permitted 625 static inline bool pte_access_permitted(pte_t pte, bool write) 626 { 627 /* 628 * _PAGE_READ is needed for any access and will be 629 * cleared for PROT_NONE 630 */ 631 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 632 return false; 633 634 if (write && !pte_write(pte)) 635 return false; 636 637 return arch_pte_access_permitted(pte_val(pte), write, 0); 638 } 639 640 /* 641 * Conversion functions: convert a page and protection to a page entry, 642 * and a page entry and page directory to the page they refer to. 643 * 644 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 645 * long for now. 646 */ 647 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 648 { 649 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 650 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 651 652 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 653 } 654 655 static inline unsigned long pte_pfn(pte_t pte) 656 { 657 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 658 } 659 660 /* Generic modifiers for PTE bits */ 661 static inline pte_t pte_wrprotect(pte_t pte) 662 { 663 if (unlikely(pte_savedwrite(pte))) 664 return pte_clear_savedwrite(pte); 665 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 666 } 667 668 static inline pte_t pte_exprotect(pte_t pte) 669 { 670 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 671 } 672 673 static inline pte_t pte_mkclean(pte_t pte) 674 { 675 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 676 } 677 678 static inline pte_t pte_mkold(pte_t pte) 679 { 680 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 681 } 682 683 static inline pte_t pte_mkexec(pte_t pte) 684 { 685 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 686 } 687 688 static inline pte_t pte_mkwrite(pte_t pte) 689 { 690 /* 691 * write implies read, hence set both 692 */ 693 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 694 } 695 696 static inline pte_t pte_mkdirty(pte_t pte) 697 { 698 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 699 } 700 701 static inline pte_t pte_mkyoung(pte_t pte) 702 { 703 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 704 } 705 706 static inline pte_t pte_mkspecial(pte_t pte) 707 { 708 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 709 } 710 711 static inline pte_t pte_mkhuge(pte_t pte) 712 { 713 return pte; 714 } 715 716 static inline pte_t pte_mkdevmap(pte_t pte) 717 { 718 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 719 } 720 721 static inline pte_t pte_mkprivileged(pte_t pte) 722 { 723 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 724 } 725 726 static inline pte_t pte_mkuser(pte_t pte) 727 { 728 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 729 } 730 731 /* 732 * This is potentially called with a pmd as the argument, in which case it's not 733 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 734 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 735 * use in page directory entries (ie. non-ptes). 736 */ 737 static inline int pte_devmap(pte_t pte) 738 { 739 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 740 741 return (pte_raw(pte) & mask) == mask; 742 } 743 744 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 745 { 746 /* FIXME!! check whether this need to be a conditional */ 747 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 748 cpu_to_be64(pgprot_val(newprot))); 749 } 750 751 /* Encode and de-code a swap entry */ 752 #define MAX_SWAPFILES_CHECK() do { \ 753 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 754 /* \ 755 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 756 * We filter HPTEFLAGS on set_pte. \ 757 */ \ 758 BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ 759 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 760 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ 761 } while (0) 762 763 #define SWP_TYPE_BITS 5 764 #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) 765 #define __swp_type(x) ((x).val & SWP_TYPE_MASK) 766 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 767 #define __swp_entry(type, offset) ((swp_entry_t) { \ 768 (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 769 /* 770 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 771 * swap type and offset we get from swap and convert that to pte to find a 772 * matching pte in linux page table. 773 * Clear bits not found in swap entries here. 774 */ 775 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 776 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 777 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 778 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 779 780 #ifdef CONFIG_MEM_SOFT_DIRTY 781 #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY 782 #else 783 #define _PAGE_SWP_SOFT_DIRTY 0UL 784 #endif /* CONFIG_MEM_SOFT_DIRTY */ 785 786 #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT 787 788 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 789 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 790 { 791 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 792 } 793 794 static inline bool pte_swp_soft_dirty(pte_t pte) 795 { 796 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 797 } 798 799 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 800 { 801 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 802 } 803 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 804 805 #define __HAVE_ARCH_PTE_SWP_EXCLUSIVE 806 static inline pte_t pte_swp_mkexclusive(pte_t pte) 807 { 808 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 809 } 810 811 static inline int pte_swp_exclusive(pte_t pte) 812 { 813 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 814 } 815 816 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 817 { 818 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); 819 } 820 821 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 822 { 823 /* 824 * This check for _PAGE_RWX and _PAGE_PRESENT bits 825 */ 826 if (access & ~ptev) 827 return false; 828 /* 829 * This check for access to privilege space 830 */ 831 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 832 return false; 833 834 return true; 835 } 836 /* 837 * Generic functions with hash/radix callbacks 838 */ 839 840 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 841 pte_t *ptep, pte_t entry, 842 unsigned long address, 843 int psize) 844 { 845 if (radix_enabled()) 846 return radix__ptep_set_access_flags(vma, ptep, entry, 847 address, psize); 848 return hash__ptep_set_access_flags(ptep, entry); 849 } 850 851 #define __HAVE_ARCH_PTE_SAME 852 static inline int pte_same(pte_t pte_a, pte_t pte_b) 853 { 854 if (radix_enabled()) 855 return radix__pte_same(pte_a, pte_b); 856 return hash__pte_same(pte_a, pte_b); 857 } 858 859 static inline int pte_none(pte_t pte) 860 { 861 if (radix_enabled()) 862 return radix__pte_none(pte); 863 return hash__pte_none(pte); 864 } 865 866 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 867 pte_t *ptep, pte_t pte, int percpu) 868 { 869 870 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 871 /* 872 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 873 * in all the callers. 874 */ 875 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 876 877 if (radix_enabled()) 878 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 879 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 880 } 881 882 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 883 884 #define pgprot_noncached pgprot_noncached 885 static inline pgprot_t pgprot_noncached(pgprot_t prot) 886 { 887 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 888 _PAGE_NON_IDEMPOTENT); 889 } 890 891 #define pgprot_noncached_wc pgprot_noncached_wc 892 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 893 { 894 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 895 _PAGE_TOLERANT); 896 } 897 898 #define pgprot_cached pgprot_cached 899 static inline pgprot_t pgprot_cached(pgprot_t prot) 900 { 901 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 902 } 903 904 #define pgprot_writecombine pgprot_writecombine 905 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 906 { 907 return pgprot_noncached_wc(prot); 908 } 909 /* 910 * check a pte mapping have cache inhibited property 911 */ 912 static inline bool pte_ci(pte_t pte) 913 { 914 __be64 pte_v = pte_raw(pte); 915 916 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 917 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 918 return true; 919 return false; 920 } 921 922 static inline void pmd_clear(pmd_t *pmdp) 923 { 924 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 925 /* 926 * Don't use this if we can possibly have a hash page table 927 * entry mapping this. 928 */ 929 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 930 } 931 *pmdp = __pmd(0); 932 } 933 934 static inline int pmd_none(pmd_t pmd) 935 { 936 return !pmd_raw(pmd); 937 } 938 939 static inline int pmd_present(pmd_t pmd) 940 { 941 /* 942 * A pmd is considerent present if _PAGE_PRESENT is set. 943 * We also need to consider the pmd present which is marked 944 * invalid during a split. Hence we look for _PAGE_INVALID 945 * if we find _PAGE_PRESENT cleared. 946 */ 947 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 948 return true; 949 950 return false; 951 } 952 953 static inline int pmd_is_serializing(pmd_t pmd) 954 { 955 /* 956 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 957 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 958 * 959 * This condition may also occur when flushing a pmd while flushing 960 * it (see ptep_modify_prot_start), so callers must ensure this 961 * case is fine as well. 962 */ 963 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 964 cpu_to_be64(_PAGE_INVALID)) 965 return true; 966 967 return false; 968 } 969 970 static inline int pmd_bad(pmd_t pmd) 971 { 972 if (radix_enabled()) 973 return radix__pmd_bad(pmd); 974 return hash__pmd_bad(pmd); 975 } 976 977 static inline void pud_clear(pud_t *pudp) 978 { 979 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 980 /* 981 * Don't use this if we can possibly have a hash page table 982 * entry mapping this. 983 */ 984 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 985 } 986 *pudp = __pud(0); 987 } 988 989 static inline int pud_none(pud_t pud) 990 { 991 return !pud_raw(pud); 992 } 993 994 static inline int pud_present(pud_t pud) 995 { 996 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 997 } 998 999 extern struct page *pud_page(pud_t pud); 1000 extern struct page *pmd_page(pmd_t pmd); 1001 static inline pte_t pud_pte(pud_t pud) 1002 { 1003 return __pte_raw(pud_raw(pud)); 1004 } 1005 1006 static inline pud_t pte_pud(pte_t pte) 1007 { 1008 return __pud_raw(pte_raw(pte)); 1009 } 1010 #define pud_write(pud) pte_write(pud_pte(pud)) 1011 1012 static inline int pud_bad(pud_t pud) 1013 { 1014 if (radix_enabled()) 1015 return radix__pud_bad(pud); 1016 return hash__pud_bad(pud); 1017 } 1018 1019 #define pud_access_permitted pud_access_permitted 1020 static inline bool pud_access_permitted(pud_t pud, bool write) 1021 { 1022 return pte_access_permitted(pud_pte(pud), write); 1023 } 1024 1025 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 1026 static inline __be64 p4d_raw(p4d_t x) 1027 { 1028 return pgd_raw(x.pgd); 1029 } 1030 1031 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 1032 1033 static inline void p4d_clear(p4d_t *p4dp) 1034 { 1035 *p4dp = __p4d(0); 1036 } 1037 1038 static inline int p4d_none(p4d_t p4d) 1039 { 1040 return !p4d_raw(p4d); 1041 } 1042 1043 static inline int p4d_present(p4d_t p4d) 1044 { 1045 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 1046 } 1047 1048 static inline pte_t p4d_pte(p4d_t p4d) 1049 { 1050 return __pte_raw(p4d_raw(p4d)); 1051 } 1052 1053 static inline p4d_t pte_p4d(pte_t pte) 1054 { 1055 return __p4d_raw(pte_raw(pte)); 1056 } 1057 1058 static inline int p4d_bad(p4d_t p4d) 1059 { 1060 if (radix_enabled()) 1061 return radix__p4d_bad(p4d); 1062 return hash__p4d_bad(p4d); 1063 } 1064 1065 #define p4d_access_permitted p4d_access_permitted 1066 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 1067 { 1068 return pte_access_permitted(p4d_pte(p4d), write); 1069 } 1070 1071 extern struct page *p4d_page(p4d_t p4d); 1072 1073 /* Pointers in the page table tree are physical addresses */ 1074 #define __pgtable_ptr_val(ptr) __pa(ptr) 1075 1076 static inline pud_t *p4d_pgtable(p4d_t p4d) 1077 { 1078 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); 1079 } 1080 1081 static inline pmd_t *pud_pgtable(pud_t pud) 1082 { 1083 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); 1084 } 1085 1086 #define pte_ERROR(e) \ 1087 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1088 #define pmd_ERROR(e) \ 1089 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1090 #define pud_ERROR(e) \ 1091 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1092 #define pgd_ERROR(e) \ 1093 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1094 1095 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1096 { 1097 if (radix_enabled()) { 1098 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1099 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1100 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1101 #endif 1102 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1103 } 1104 return hash__map_kernel_page(ea, pa, prot); 1105 } 1106 1107 void unmap_kernel_page(unsigned long va); 1108 1109 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1110 unsigned long page_size, 1111 unsigned long phys) 1112 { 1113 if (radix_enabled()) 1114 return radix__vmemmap_create_mapping(start, page_size, phys); 1115 return hash__vmemmap_create_mapping(start, page_size, phys); 1116 } 1117 1118 #ifdef CONFIG_MEMORY_HOTPLUG 1119 static inline void vmemmap_remove_mapping(unsigned long start, 1120 unsigned long page_size) 1121 { 1122 if (radix_enabled()) 1123 return radix__vmemmap_remove_mapping(start, page_size); 1124 return hash__vmemmap_remove_mapping(start, page_size); 1125 } 1126 #endif 1127 1128 #ifdef CONFIG_DEBUG_PAGEALLOC 1129 static inline void __kernel_map_pages(struct page *page, int numpages, int enable) 1130 { 1131 if (radix_enabled()) 1132 radix__kernel_map_pages(page, numpages, enable); 1133 else 1134 hash__kernel_map_pages(page, numpages, enable); 1135 } 1136 #endif 1137 1138 static inline pte_t pmd_pte(pmd_t pmd) 1139 { 1140 return __pte_raw(pmd_raw(pmd)); 1141 } 1142 1143 static inline pmd_t pte_pmd(pte_t pte) 1144 { 1145 return __pmd_raw(pte_raw(pte)); 1146 } 1147 1148 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1149 { 1150 return (pte_t *)pmd; 1151 } 1152 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1153 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1154 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1155 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1156 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1157 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1158 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1159 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1160 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1161 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1162 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1163 1164 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1165 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1166 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1167 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1168 1169 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1170 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1171 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1172 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1173 #endif 1174 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1175 1176 #ifdef CONFIG_NUMA_BALANCING 1177 static inline int pmd_protnone(pmd_t pmd) 1178 { 1179 return pte_protnone(pmd_pte(pmd)); 1180 } 1181 #endif /* CONFIG_NUMA_BALANCING */ 1182 1183 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1184 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1185 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1186 1187 #define pmd_access_permitted pmd_access_permitted 1188 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1189 { 1190 /* 1191 * pmdp_invalidate sets this combination (which is not caught by 1192 * !pte_present() check in pte_access_permitted), to prevent 1193 * lock-free lookups, as part of the serialize_against_pte_lookup() 1194 * synchronisation. 1195 * 1196 * This also catches the case where the PTE's hardware PRESENT bit is 1197 * cleared while TLB is flushed, which is suboptimal but should not 1198 * be frequent. 1199 */ 1200 if (pmd_is_serializing(pmd)) 1201 return false; 1202 1203 return pte_access_permitted(pmd_pte(pmd), write); 1204 } 1205 1206 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1207 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1208 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1209 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1210 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1211 pmd_t *pmdp, pmd_t pmd); 1212 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1213 unsigned long addr, pmd_t *pmd) 1214 { 1215 } 1216 1217 extern int hash__has_transparent_hugepage(void); 1218 static inline int has_transparent_hugepage(void) 1219 { 1220 if (radix_enabled()) 1221 return radix__has_transparent_hugepage(); 1222 return hash__has_transparent_hugepage(); 1223 } 1224 #define has_transparent_hugepage has_transparent_hugepage 1225 1226 static inline unsigned long 1227 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1228 unsigned long clr, unsigned long set) 1229 { 1230 if (radix_enabled()) 1231 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1232 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1233 } 1234 1235 /* 1236 * returns true for pmd migration entries, THP, devmap, hugetlb 1237 * But compile time dependent on THP config 1238 */ 1239 static inline int pmd_large(pmd_t pmd) 1240 { 1241 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1242 } 1243 1244 /* 1245 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1246 * the below will work for radix too 1247 */ 1248 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1249 unsigned long addr, pmd_t *pmdp) 1250 { 1251 unsigned long old; 1252 1253 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1254 return 0; 1255 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1256 return ((old & _PAGE_ACCESSED) != 0); 1257 } 1258 1259 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1260 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1261 pmd_t *pmdp) 1262 { 1263 if (__pmd_write((*pmdp))) 1264 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1265 else if (unlikely(pmd_savedwrite(*pmdp))) 1266 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1267 } 1268 1269 /* 1270 * Only returns true for a THP. False for pmd migration entry. 1271 * We also need to return true when we come across a pte that 1272 * in between a thp split. While splitting THP, we mark the pmd 1273 * invalid (pmdp_invalidate()) before we set it with pte page 1274 * address. A pmd_trans_huge() check against a pmd entry during that time 1275 * should return true. 1276 * We should not call this on a hugetlb entry. We should check for HugeTLB 1277 * entry using vma->vm_flags 1278 * The page table walk rule is explained in Documentation/mm/transhuge.rst 1279 */ 1280 static inline int pmd_trans_huge(pmd_t pmd) 1281 { 1282 if (!pmd_present(pmd)) 1283 return false; 1284 1285 if (radix_enabled()) 1286 return radix__pmd_trans_huge(pmd); 1287 return hash__pmd_trans_huge(pmd); 1288 } 1289 1290 #define __HAVE_ARCH_PMD_SAME 1291 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1292 { 1293 if (radix_enabled()) 1294 return radix__pmd_same(pmd_a, pmd_b); 1295 return hash__pmd_same(pmd_a, pmd_b); 1296 } 1297 1298 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1299 { 1300 if (radix_enabled()) 1301 return radix__pmd_mkhuge(pmd); 1302 return hash__pmd_mkhuge(pmd); 1303 } 1304 1305 /* 1306 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1307 */ 1308 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1309 { 1310 #ifdef CONFIG_DEBUG_VM 1311 if (radix_enabled()) 1312 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1313 else 1314 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1315 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1316 #endif 1317 return pmd; 1318 } 1319 1320 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1321 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1322 unsigned long address, pmd_t *pmdp, 1323 pmd_t entry, int dirty); 1324 1325 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1326 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1327 unsigned long address, pmd_t *pmdp); 1328 1329 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1330 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1331 unsigned long addr, pmd_t *pmdp) 1332 { 1333 if (radix_enabled()) 1334 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1335 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1336 } 1337 1338 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1339 unsigned long address, pmd_t *pmdp) 1340 { 1341 if (radix_enabled()) 1342 return radix__pmdp_collapse_flush(vma, address, pmdp); 1343 return hash__pmdp_collapse_flush(vma, address, pmdp); 1344 } 1345 #define pmdp_collapse_flush pmdp_collapse_flush 1346 1347 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1348 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1349 unsigned long addr, 1350 pmd_t *pmdp, int full); 1351 1352 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1353 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1354 pmd_t *pmdp, pgtable_t pgtable) 1355 { 1356 if (radix_enabled()) 1357 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1358 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1359 } 1360 1361 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1362 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1363 pmd_t *pmdp) 1364 { 1365 if (radix_enabled()) 1366 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1367 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1368 } 1369 1370 #define __HAVE_ARCH_PMDP_INVALIDATE 1371 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1372 pmd_t *pmdp); 1373 1374 #define pmd_move_must_withdraw pmd_move_must_withdraw 1375 struct spinlock; 1376 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1377 struct spinlock *old_pmd_ptl, 1378 struct vm_area_struct *vma); 1379 /* 1380 * Hash translation mode use the deposited table to store hash pte 1381 * slot information. 1382 */ 1383 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1384 static inline bool arch_needs_pgtable_deposit(void) 1385 { 1386 if (radix_enabled()) 1387 return false; 1388 return true; 1389 } 1390 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1391 1392 1393 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1394 { 1395 if (radix_enabled()) 1396 return radix__pmd_mkdevmap(pmd); 1397 return hash__pmd_mkdevmap(pmd); 1398 } 1399 1400 static inline int pmd_devmap(pmd_t pmd) 1401 { 1402 return pte_devmap(pmd_pte(pmd)); 1403 } 1404 1405 static inline int pud_devmap(pud_t pud) 1406 { 1407 return 0; 1408 } 1409 1410 static inline int pgd_devmap(pgd_t pgd) 1411 { 1412 return 0; 1413 } 1414 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1415 1416 static inline int pud_pfn(pud_t pud) 1417 { 1418 /* 1419 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1420 * check so this should never be used. If it grows another user we 1421 * want to know about it. 1422 */ 1423 BUILD_BUG(); 1424 return 0; 1425 } 1426 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1427 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1428 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1429 pte_t *, pte_t, pte_t); 1430 1431 /* 1432 * Returns true for a R -> RW upgrade of pte 1433 */ 1434 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1435 { 1436 if (!(old_val & _PAGE_READ)) 1437 return false; 1438 1439 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1440 return true; 1441 1442 return false; 1443 } 1444 1445 /* 1446 * Like pmd_huge() and pmd_large(), but works regardless of config options 1447 */ 1448 #define pmd_is_leaf pmd_is_leaf 1449 #define pmd_leaf pmd_is_leaf 1450 static inline bool pmd_is_leaf(pmd_t pmd) 1451 { 1452 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1453 } 1454 1455 #define pud_is_leaf pud_is_leaf 1456 #define pud_leaf pud_is_leaf 1457 static inline bool pud_is_leaf(pud_t pud) 1458 { 1459 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1460 } 1461 1462 #define p4d_is_leaf p4d_is_leaf 1463 #define p4d_leaf p4d_is_leaf 1464 static inline bool p4d_is_leaf(p4d_t p4d) 1465 { 1466 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PTE)); 1467 } 1468 1469 #endif /* __ASSEMBLY__ */ 1470 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1471