1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/5level-fixup.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x1000000000000000UL 36 #define _RPAGE_RSV2 0x0800000000000000UL 37 #define _RPAGE_RSV3 0x0400000000000000UL 38 #define _RPAGE_RSV4 0x0200000000000000UL 39 #define _RPAGE_RSV5 0x00040UL 40 41 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 43 /* 44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 46 * differentiate between two use a SW field when invalidating. 47 * 48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 49 * 50 * This is used only when _PAGE_PRESENT is cleared. 51 */ 52 #define _PAGE_INVALID _RPAGE_SW0 53 54 /* 55 * Top and bottom bits of RPN which can be used by hash 56 * translation mode, because we expect them to be zero 57 * otherwise. 58 */ 59 #define _RPAGE_RPN0 0x01000 60 #define _RPAGE_RPN1 0x02000 61 #define _RPAGE_RPN44 0x0100000000000000UL 62 #define _RPAGE_RPN43 0x0080000000000000UL 63 #define _RPAGE_RPN42 0x0040000000000000UL 64 #define _RPAGE_RPN41 0x0020000000000000UL 65 66 /* Max physical address bit as per radix table */ 67 #define _RPAGE_PA_MAX 57 68 69 /* 70 * Max physical address bit we will use for now. 71 * 72 * This is mostly a hardware limitation and for now Power9 has 73 * a 51 bit limit. 74 * 75 * This is different from the number of physical bit required to address 76 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 77 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 78 * number of sections we can support (SECTIONS_SHIFT). 79 * 80 * This is different from Radix page table limitation above and 81 * should always be less than that. The limit is done such that 82 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 83 * for hash linux page table specific bits. 84 * 85 * In order to be compatible with future hardware generations we keep 86 * some offsets and limit this for now to 53 87 */ 88 #define _PAGE_PA_MAX 53 89 90 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 91 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 92 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 93 #define __HAVE_ARCH_PTE_DEVMAP 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 120 _PAGE_RW | _PAGE_EXEC) 121 /* 122 * _PAGE_CHG_MASK masks of bits that are to be preserved across 123 * pgprot changes 124 */ 125 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 126 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 127 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 128 129 #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \ 130 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4) 131 /* 132 * We define 2 sets of base prot bits, one for basic pages (ie, 133 * cacheable kernel and user pages) and one for non cacheable 134 * pages. We always set _PAGE_COHERENT when SMP is enabled or 135 * the processor might need it for DMA coherency. 136 */ 137 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 138 #define _PAGE_BASE (_PAGE_BASE_NC) 139 140 /* Permission masks used to generate the __P and __S table, 141 * 142 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 143 * 144 * Write permissions imply read permissions for now (we could make write-only 145 * pages on BookE but we don't bother for now). Execute permission control is 146 * possible on platforms that define _PAGE_EXEC 147 */ 148 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 149 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 150 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 151 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 152 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 153 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 154 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 155 156 /* Permission masks used for kernel mappings */ 157 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 158 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 159 _PAGE_TOLERANT) 160 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 161 _PAGE_NON_IDEMPOTENT) 162 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 163 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 164 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 165 166 /* 167 * Protection used for kernel text. We want the debuggers to be able to 168 * set breakpoints anywhere, so don't write protect the kernel text 169 * on platforms where such control is possible. 170 */ 171 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 172 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 173 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 174 #else 175 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 176 #endif 177 178 /* Make modules code happy. We don't set RO yet */ 179 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 180 #define PAGE_AGP (PAGE_KERNEL_NC) 181 182 #ifndef __ASSEMBLY__ 183 /* 184 * page table defines 185 */ 186 extern unsigned long __pte_index_size; 187 extern unsigned long __pmd_index_size; 188 extern unsigned long __pud_index_size; 189 extern unsigned long __pgd_index_size; 190 extern unsigned long __pud_cache_index; 191 #define PTE_INDEX_SIZE __pte_index_size 192 #define PMD_INDEX_SIZE __pmd_index_size 193 #define PUD_INDEX_SIZE __pud_index_size 194 #define PGD_INDEX_SIZE __pgd_index_size 195 /* pmd table use page table fragments */ 196 #define PMD_CACHE_INDEX 0 197 #define PUD_CACHE_INDEX __pud_cache_index 198 /* 199 * Because of use of pte fragments and THP, size of page table 200 * are not always derived out of index size above. 201 */ 202 extern unsigned long __pte_table_size; 203 extern unsigned long __pmd_table_size; 204 extern unsigned long __pud_table_size; 205 extern unsigned long __pgd_table_size; 206 #define PTE_TABLE_SIZE __pte_table_size 207 #define PMD_TABLE_SIZE __pmd_table_size 208 #define PUD_TABLE_SIZE __pud_table_size 209 #define PGD_TABLE_SIZE __pgd_table_size 210 211 extern unsigned long __pmd_val_bits; 212 extern unsigned long __pud_val_bits; 213 extern unsigned long __pgd_val_bits; 214 #define PMD_VAL_BITS __pmd_val_bits 215 #define PUD_VAL_BITS __pud_val_bits 216 #define PGD_VAL_BITS __pgd_val_bits 217 218 extern unsigned long __pte_frag_nr; 219 #define PTE_FRAG_NR __pte_frag_nr 220 extern unsigned long __pte_frag_size_shift; 221 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 222 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 223 224 extern unsigned long __pmd_frag_nr; 225 #define PMD_FRAG_NR __pmd_frag_nr 226 extern unsigned long __pmd_frag_size_shift; 227 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 228 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 229 230 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 231 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 232 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 233 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 234 235 /* PMD_SHIFT determines what a second-level page table entry can map */ 236 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 237 #define PMD_SIZE (1UL << PMD_SHIFT) 238 #define PMD_MASK (~(PMD_SIZE-1)) 239 240 /* PUD_SHIFT determines what a third-level page table entry can map */ 241 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 242 #define PUD_SIZE (1UL << PUD_SHIFT) 243 #define PUD_MASK (~(PUD_SIZE-1)) 244 245 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 246 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 247 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 248 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 249 250 /* Bits to mask out from a PMD to get to the PTE page */ 251 #define PMD_MASKED_BITS 0xc0000000000000ffUL 252 /* Bits to mask out from a PUD to get to the PMD page */ 253 #define PUD_MASKED_BITS 0xc0000000000000ffUL 254 /* Bits to mask out from a PGD to get to the PUD page */ 255 #define PGD_MASKED_BITS 0xc0000000000000ffUL 256 257 /* 258 * Used as an indicator for rcu callback functions 259 */ 260 enum pgtable_index { 261 PTE_INDEX = 0, 262 PMD_INDEX, 263 PUD_INDEX, 264 PGD_INDEX, 265 /* 266 * Below are used with 4k page size and hugetlb 267 */ 268 HTLB_16M_INDEX, 269 HTLB_16G_INDEX, 270 }; 271 272 extern unsigned long __vmalloc_start; 273 extern unsigned long __vmalloc_end; 274 #define VMALLOC_START __vmalloc_start 275 #define VMALLOC_END __vmalloc_end 276 277 extern unsigned long __kernel_virt_start; 278 extern unsigned long __kernel_virt_size; 279 extern unsigned long __kernel_io_start; 280 #define KERN_VIRT_START __kernel_virt_start 281 #define KERN_VIRT_SIZE __kernel_virt_size 282 #define KERN_IO_START __kernel_io_start 283 extern struct page *vmemmap; 284 extern unsigned long ioremap_bot; 285 extern unsigned long pci_io_base; 286 #endif /* __ASSEMBLY__ */ 287 288 #include <asm/book3s/64/hash.h> 289 #include <asm/book3s/64/radix.h> 290 291 #ifdef CONFIG_PPC_64K_PAGES 292 #include <asm/book3s/64/pgtable-64k.h> 293 #else 294 #include <asm/book3s/64/pgtable-4k.h> 295 #endif 296 297 #include <asm/barrier.h> 298 /* 299 * The second half of the kernel virtual space is used for IO mappings, 300 * it's itself carved into the PIO region (ISA and PHB IO space) and 301 * the ioremap space 302 * 303 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 304 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 305 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 306 */ 307 #define FULL_IO_SIZE 0x80000000ul 308 #define ISA_IO_BASE (KERN_IO_START) 309 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 310 #define PHB_IO_BASE (ISA_IO_END) 311 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 312 #define IOREMAP_BASE (PHB_IO_END) 313 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 314 315 /* Advertise special mapping type for AGP */ 316 #define HAVE_PAGE_AGP 317 318 #ifndef __ASSEMBLY__ 319 320 /* 321 * This is the default implementation of various PTE accessors, it's 322 * used in all cases except Book3S with 64K pages where we have a 323 * concept of sub-pages 324 */ 325 #ifndef __real_pte 326 327 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 328 #define __rpte_to_pte(r) ((r).pte) 329 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 330 331 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 332 do { \ 333 index = 0; \ 334 shift = mmu_psize_defs[psize].shift; \ 335 336 #define pte_iterate_hashed_end() } while(0) 337 338 /* 339 * We expect this to be called only for user addresses or kernel virtual 340 * addresses other than the linear mapping. 341 */ 342 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 343 344 #endif /* __real_pte */ 345 346 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 347 pte_t *ptep, unsigned long clr, 348 unsigned long set, int huge) 349 { 350 if (radix_enabled()) 351 return radix__pte_update(mm, addr, ptep, clr, set, huge); 352 return hash__pte_update(mm, addr, ptep, clr, set, huge); 353 } 354 /* 355 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 356 * We currently remove entries from the hashtable regardless of whether 357 * the entry was young or dirty. 358 * 359 * We should be more intelligent about this but for the moment we override 360 * these functions and force a tlb flush unconditionally 361 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 362 * function for both hash and radix. 363 */ 364 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 365 unsigned long addr, pte_t *ptep) 366 { 367 unsigned long old; 368 369 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 370 return 0; 371 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 372 return (old & _PAGE_ACCESSED) != 0; 373 } 374 375 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 376 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 377 ({ \ 378 int __r; \ 379 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 380 __r; \ 381 }) 382 383 static inline int __pte_write(pte_t pte) 384 { 385 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 386 } 387 388 #ifdef CONFIG_NUMA_BALANCING 389 #define pte_savedwrite pte_savedwrite 390 static inline bool pte_savedwrite(pte_t pte) 391 { 392 /* 393 * Saved write ptes are prot none ptes that doesn't have 394 * privileged bit sit. We mark prot none as one which has 395 * present and pviliged bit set and RWX cleared. To mark 396 * protnone which used to have _PAGE_WRITE set we clear 397 * the privileged bit. 398 */ 399 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 400 } 401 #else 402 #define pte_savedwrite pte_savedwrite 403 static inline bool pte_savedwrite(pte_t pte) 404 { 405 return false; 406 } 407 #endif 408 409 static inline int pte_write(pte_t pte) 410 { 411 return __pte_write(pte) || pte_savedwrite(pte); 412 } 413 414 static inline int pte_read(pte_t pte) 415 { 416 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 417 } 418 419 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 420 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 421 pte_t *ptep) 422 { 423 if (__pte_write(*ptep)) 424 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 425 else if (unlikely(pte_savedwrite(*ptep))) 426 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 427 } 428 429 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 430 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 431 unsigned long addr, pte_t *ptep) 432 { 433 /* 434 * We should not find protnone for hugetlb, but this complete the 435 * interface. 436 */ 437 if (__pte_write(*ptep)) 438 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 439 else if (unlikely(pte_savedwrite(*ptep))) 440 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 441 } 442 443 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 444 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 445 unsigned long addr, pte_t *ptep) 446 { 447 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 448 return __pte(old); 449 } 450 451 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 452 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 453 unsigned long addr, 454 pte_t *ptep, int full) 455 { 456 if (full && radix_enabled()) { 457 /* 458 * We know that this is a full mm pte clear and 459 * hence can be sure there is no parallel set_pte. 460 */ 461 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 462 } 463 return ptep_get_and_clear(mm, addr, ptep); 464 } 465 466 467 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 468 pte_t * ptep) 469 { 470 pte_update(mm, addr, ptep, ~0UL, 0, 0); 471 } 472 473 static inline int pte_dirty(pte_t pte) 474 { 475 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 476 } 477 478 static inline int pte_young(pte_t pte) 479 { 480 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 481 } 482 483 static inline int pte_special(pte_t pte) 484 { 485 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 486 } 487 488 static inline bool pte_exec(pte_t pte) 489 { 490 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 491 } 492 493 494 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 495 static inline bool pte_soft_dirty(pte_t pte) 496 { 497 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 498 } 499 500 static inline pte_t pte_mksoft_dirty(pte_t pte) 501 { 502 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 503 } 504 505 static inline pte_t pte_clear_soft_dirty(pte_t pte) 506 { 507 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 508 } 509 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 510 511 #ifdef CONFIG_NUMA_BALANCING 512 static inline int pte_protnone(pte_t pte) 513 { 514 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 515 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 516 } 517 518 #define pte_mk_savedwrite pte_mk_savedwrite 519 static inline pte_t pte_mk_savedwrite(pte_t pte) 520 { 521 /* 522 * Used by Autonuma subsystem to preserve the write bit 523 * while marking the pte PROT_NONE. Only allow this 524 * on PROT_NONE pte 525 */ 526 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 527 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 528 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 529 } 530 531 #define pte_clear_savedwrite pte_clear_savedwrite 532 static inline pte_t pte_clear_savedwrite(pte_t pte) 533 { 534 /* 535 * Used by KSM subsystem to make a protnone pte readonly. 536 */ 537 VM_BUG_ON(!pte_protnone(pte)); 538 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 539 } 540 #else 541 #define pte_clear_savedwrite pte_clear_savedwrite 542 static inline pte_t pte_clear_savedwrite(pte_t pte) 543 { 544 VM_WARN_ON(1); 545 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 546 } 547 #endif /* CONFIG_NUMA_BALANCING */ 548 549 static inline int pte_present(pte_t pte) 550 { 551 /* 552 * A pte is considerent present if _PAGE_PRESENT is set. 553 * We also need to consider the pte present which is marked 554 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 555 * if we find _PAGE_PRESENT cleared. 556 */ 557 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)); 558 } 559 560 static inline bool pte_hw_valid(pte_t pte) 561 { 562 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 563 } 564 565 #ifdef CONFIG_PPC_MEM_KEYS 566 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 567 #else 568 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 569 { 570 return true; 571 } 572 #endif /* CONFIG_PPC_MEM_KEYS */ 573 574 static inline bool pte_user(pte_t pte) 575 { 576 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 577 } 578 579 #define pte_access_permitted pte_access_permitted 580 static inline bool pte_access_permitted(pte_t pte, bool write) 581 { 582 /* 583 * _PAGE_READ is needed for any access and will be 584 * cleared for PROT_NONE 585 */ 586 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 587 return false; 588 589 if (write && !pte_write(pte)) 590 return false; 591 592 return arch_pte_access_permitted(pte_val(pte), write, 0); 593 } 594 595 /* 596 * Conversion functions: convert a page and protection to a page entry, 597 * and a page entry and page directory to the page they refer to. 598 * 599 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 600 * long for now. 601 */ 602 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 603 { 604 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 605 pgprot_val(pgprot)); 606 } 607 608 static inline unsigned long pte_pfn(pte_t pte) 609 { 610 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 611 } 612 613 /* Generic modifiers for PTE bits */ 614 static inline pte_t pte_wrprotect(pte_t pte) 615 { 616 if (unlikely(pte_savedwrite(pte))) 617 return pte_clear_savedwrite(pte); 618 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 619 } 620 621 static inline pte_t pte_exprotect(pte_t pte) 622 { 623 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 624 } 625 626 static inline pte_t pte_mkclean(pte_t pte) 627 { 628 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 629 } 630 631 static inline pte_t pte_mkold(pte_t pte) 632 { 633 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 634 } 635 636 static inline pte_t pte_mkexec(pte_t pte) 637 { 638 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 639 } 640 641 static inline pte_t pte_mkpte(pte_t pte) 642 { 643 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 644 } 645 646 static inline pte_t pte_mkwrite(pte_t pte) 647 { 648 /* 649 * write implies read, hence set both 650 */ 651 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 652 } 653 654 static inline pte_t pte_mkdirty(pte_t pte) 655 { 656 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 657 } 658 659 static inline pte_t pte_mkyoung(pte_t pte) 660 { 661 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 662 } 663 664 static inline pte_t pte_mkspecial(pte_t pte) 665 { 666 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 667 } 668 669 static inline pte_t pte_mkhuge(pte_t pte) 670 { 671 return pte; 672 } 673 674 static inline pte_t pte_mkdevmap(pte_t pte) 675 { 676 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 677 } 678 679 static inline pte_t pte_mkprivileged(pte_t pte) 680 { 681 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 682 } 683 684 static inline pte_t pte_mkuser(pte_t pte) 685 { 686 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 687 } 688 689 /* 690 * This is potentially called with a pmd as the argument, in which case it's not 691 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 692 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 693 * use in page directory entries (ie. non-ptes). 694 */ 695 static inline int pte_devmap(pte_t pte) 696 { 697 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 698 699 return (pte_raw(pte) & mask) == mask; 700 } 701 702 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 703 { 704 /* FIXME!! check whether this need to be a conditional */ 705 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 706 cpu_to_be64(pgprot_val(newprot))); 707 } 708 709 /* Encode and de-code a swap entry */ 710 #define MAX_SWAPFILES_CHECK() do { \ 711 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 712 /* \ 713 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 714 * We filter HPTEFLAGS on set_pte. \ 715 */ \ 716 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 717 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 718 } while (0) 719 720 #define SWP_TYPE_BITS 5 721 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 722 & ((1UL << SWP_TYPE_BITS) - 1)) 723 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 724 #define __swp_entry(type, offset) ((swp_entry_t) { \ 725 ((type) << _PAGE_BIT_SWAP_TYPE) \ 726 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 727 /* 728 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 729 * swap type and offset we get from swap and convert that to pte to find a 730 * matching pte in linux page table. 731 * Clear bits not found in swap entries here. 732 */ 733 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 734 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 735 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 736 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 737 738 #ifdef CONFIG_MEM_SOFT_DIRTY 739 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 740 #else 741 #define _PAGE_SWP_SOFT_DIRTY 0UL 742 #endif /* CONFIG_MEM_SOFT_DIRTY */ 743 744 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 745 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 746 { 747 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 748 } 749 750 static inline bool pte_swp_soft_dirty(pte_t pte) 751 { 752 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 753 } 754 755 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 756 { 757 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 758 } 759 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 760 761 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 762 { 763 /* 764 * This check for _PAGE_RWX and _PAGE_PRESENT bits 765 */ 766 if (access & ~ptev) 767 return false; 768 /* 769 * This check for access to privilege space 770 */ 771 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 772 return false; 773 774 return true; 775 } 776 /* 777 * Generic functions with hash/radix callbacks 778 */ 779 780 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 781 pte_t *ptep, pte_t entry, 782 unsigned long address, 783 int psize) 784 { 785 if (radix_enabled()) 786 return radix__ptep_set_access_flags(vma, ptep, entry, 787 address, psize); 788 return hash__ptep_set_access_flags(ptep, entry); 789 } 790 791 #define __HAVE_ARCH_PTE_SAME 792 static inline int pte_same(pte_t pte_a, pte_t pte_b) 793 { 794 if (radix_enabled()) 795 return radix__pte_same(pte_a, pte_b); 796 return hash__pte_same(pte_a, pte_b); 797 } 798 799 static inline int pte_none(pte_t pte) 800 { 801 if (radix_enabled()) 802 return radix__pte_none(pte); 803 return hash__pte_none(pte); 804 } 805 806 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 807 pte_t *ptep, pte_t pte, int percpu) 808 { 809 if (radix_enabled()) 810 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 811 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 812 } 813 814 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 815 816 #define pgprot_noncached pgprot_noncached 817 static inline pgprot_t pgprot_noncached(pgprot_t prot) 818 { 819 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 820 _PAGE_NON_IDEMPOTENT); 821 } 822 823 #define pgprot_noncached_wc pgprot_noncached_wc 824 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 825 { 826 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 827 _PAGE_TOLERANT); 828 } 829 830 #define pgprot_cached pgprot_cached 831 static inline pgprot_t pgprot_cached(pgprot_t prot) 832 { 833 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 834 } 835 836 #define pgprot_writecombine pgprot_writecombine 837 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 838 { 839 return pgprot_noncached_wc(prot); 840 } 841 /* 842 * check a pte mapping have cache inhibited property 843 */ 844 static inline bool pte_ci(pte_t pte) 845 { 846 __be64 pte_v = pte_raw(pte); 847 848 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 849 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 850 return true; 851 return false; 852 } 853 854 static inline void pmd_clear(pmd_t *pmdp) 855 { 856 *pmdp = __pmd(0); 857 } 858 859 static inline int pmd_none(pmd_t pmd) 860 { 861 return !pmd_raw(pmd); 862 } 863 864 static inline int pmd_present(pmd_t pmd) 865 { 866 /* 867 * A pmd is considerent present if _PAGE_PRESENT is set. 868 * We also need to consider the pmd present which is marked 869 * invalid during a split. Hence we look for _PAGE_INVALID 870 * if we find _PAGE_PRESENT cleared. 871 */ 872 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 873 return true; 874 875 return false; 876 } 877 878 static inline int pmd_bad(pmd_t pmd) 879 { 880 if (radix_enabled()) 881 return radix__pmd_bad(pmd); 882 return hash__pmd_bad(pmd); 883 } 884 885 static inline void pud_clear(pud_t *pudp) 886 { 887 *pudp = __pud(0); 888 } 889 890 static inline int pud_none(pud_t pud) 891 { 892 return !pud_raw(pud); 893 } 894 895 static inline int pud_present(pud_t pud) 896 { 897 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 898 } 899 900 extern struct page *pud_page(pud_t pud); 901 extern struct page *pmd_page(pmd_t pmd); 902 static inline pte_t pud_pte(pud_t pud) 903 { 904 return __pte_raw(pud_raw(pud)); 905 } 906 907 static inline pud_t pte_pud(pte_t pte) 908 { 909 return __pud_raw(pte_raw(pte)); 910 } 911 #define pud_write(pud) pte_write(pud_pte(pud)) 912 913 static inline int pud_bad(pud_t pud) 914 { 915 if (radix_enabled()) 916 return radix__pud_bad(pud); 917 return hash__pud_bad(pud); 918 } 919 920 #define pud_access_permitted pud_access_permitted 921 static inline bool pud_access_permitted(pud_t pud, bool write) 922 { 923 return pte_access_permitted(pud_pte(pud), write); 924 } 925 926 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 927 928 static inline void pgd_clear(pgd_t *pgdp) 929 { 930 *pgdp = __pgd(0); 931 } 932 933 static inline int pgd_none(pgd_t pgd) 934 { 935 return !pgd_raw(pgd); 936 } 937 938 static inline int pgd_present(pgd_t pgd) 939 { 940 return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT)); 941 } 942 943 static inline pte_t pgd_pte(pgd_t pgd) 944 { 945 return __pte_raw(pgd_raw(pgd)); 946 } 947 948 static inline pgd_t pte_pgd(pte_t pte) 949 { 950 return __pgd_raw(pte_raw(pte)); 951 } 952 953 static inline int pgd_bad(pgd_t pgd) 954 { 955 if (radix_enabled()) 956 return radix__pgd_bad(pgd); 957 return hash__pgd_bad(pgd); 958 } 959 960 #define pgd_access_permitted pgd_access_permitted 961 static inline bool pgd_access_permitted(pgd_t pgd, bool write) 962 { 963 return pte_access_permitted(pgd_pte(pgd), write); 964 } 965 966 extern struct page *pgd_page(pgd_t pgd); 967 968 /* Pointers in the page table tree are physical addresses */ 969 #define __pgtable_ptr_val(ptr) __pa(ptr) 970 971 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 972 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 973 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 974 975 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 976 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 977 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 978 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 979 980 /* 981 * Find an entry in a page-table-directory. We combine the address region 982 * (the high order N bits) and the pgd portion of the address. 983 */ 984 985 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 986 987 #define pud_offset(pgdp, addr) \ 988 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 989 #define pmd_offset(pudp,addr) \ 990 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 991 #define pte_offset_kernel(dir,addr) \ 992 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 993 994 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 995 #define pte_unmap(pte) do { } while(0) 996 997 /* to find an entry in a kernel page-table-directory */ 998 /* This now only contains the vmalloc pages */ 999 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1000 1001 #define pte_ERROR(e) \ 1002 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1003 #define pmd_ERROR(e) \ 1004 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1005 #define pud_ERROR(e) \ 1006 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1007 #define pgd_ERROR(e) \ 1008 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1009 1010 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1011 { 1012 if (radix_enabled()) { 1013 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1014 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1015 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1016 #endif 1017 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1018 } 1019 return hash__map_kernel_page(ea, pa, prot); 1020 } 1021 1022 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1023 unsigned long page_size, 1024 unsigned long phys) 1025 { 1026 if (radix_enabled()) 1027 return radix__vmemmap_create_mapping(start, page_size, phys); 1028 return hash__vmemmap_create_mapping(start, page_size, phys); 1029 } 1030 1031 #ifdef CONFIG_MEMORY_HOTPLUG 1032 static inline void vmemmap_remove_mapping(unsigned long start, 1033 unsigned long page_size) 1034 { 1035 if (radix_enabled()) 1036 return radix__vmemmap_remove_mapping(start, page_size); 1037 return hash__vmemmap_remove_mapping(start, page_size); 1038 } 1039 #endif 1040 1041 static inline pte_t pmd_pte(pmd_t pmd) 1042 { 1043 return __pte_raw(pmd_raw(pmd)); 1044 } 1045 1046 static inline pmd_t pte_pmd(pte_t pte) 1047 { 1048 return __pmd_raw(pte_raw(pte)); 1049 } 1050 1051 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1052 { 1053 return (pte_t *)pmd; 1054 } 1055 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1056 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1057 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1058 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1059 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1060 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1061 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1062 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1063 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1064 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1065 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1066 1067 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1068 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1069 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1070 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1071 1072 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1073 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1074 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1075 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1076 #endif 1077 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1078 1079 #ifdef CONFIG_NUMA_BALANCING 1080 static inline int pmd_protnone(pmd_t pmd) 1081 { 1082 return pte_protnone(pmd_pte(pmd)); 1083 } 1084 #endif /* CONFIG_NUMA_BALANCING */ 1085 1086 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1087 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1088 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1089 1090 #define pmd_access_permitted pmd_access_permitted 1091 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1092 { 1093 return pte_access_permitted(pmd_pte(pmd), write); 1094 } 1095 1096 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1097 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1098 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1099 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1100 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1101 pmd_t *pmdp, pmd_t pmd); 1102 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1103 pmd_t *pmd); 1104 extern int hash__has_transparent_hugepage(void); 1105 static inline int has_transparent_hugepage(void) 1106 { 1107 if (radix_enabled()) 1108 return radix__has_transparent_hugepage(); 1109 return hash__has_transparent_hugepage(); 1110 } 1111 #define has_transparent_hugepage has_transparent_hugepage 1112 1113 static inline unsigned long 1114 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1115 unsigned long clr, unsigned long set) 1116 { 1117 if (radix_enabled()) 1118 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1119 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1120 } 1121 1122 /* 1123 * returns true for pmd migration entries, THP, devmap, hugetlb 1124 * But compile time dependent on THP config 1125 */ 1126 static inline int pmd_large(pmd_t pmd) 1127 { 1128 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1129 } 1130 1131 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1132 { 1133 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1134 } 1135 /* 1136 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1137 * the below will work for radix too 1138 */ 1139 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1140 unsigned long addr, pmd_t *pmdp) 1141 { 1142 unsigned long old; 1143 1144 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1145 return 0; 1146 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1147 return ((old & _PAGE_ACCESSED) != 0); 1148 } 1149 1150 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1151 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1152 pmd_t *pmdp) 1153 { 1154 if (__pmd_write((*pmdp))) 1155 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1156 else if (unlikely(pmd_savedwrite(*pmdp))) 1157 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1158 } 1159 1160 /* 1161 * Only returns true for a THP. False for pmd migration entry. 1162 * We also need to return true when we come across a pte that 1163 * in between a thp split. While splitting THP, we mark the pmd 1164 * invalid (pmdp_invalidate()) before we set it with pte page 1165 * address. A pmd_trans_huge() check against a pmd entry during that time 1166 * should return true. 1167 * We should not call this on a hugetlb entry. We should check for HugeTLB 1168 * entry using vma->vm_flags 1169 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1170 */ 1171 static inline int pmd_trans_huge(pmd_t pmd) 1172 { 1173 if (!pmd_present(pmd)) 1174 return false; 1175 1176 if (radix_enabled()) 1177 return radix__pmd_trans_huge(pmd); 1178 return hash__pmd_trans_huge(pmd); 1179 } 1180 1181 #define __HAVE_ARCH_PMD_SAME 1182 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1183 { 1184 if (radix_enabled()) 1185 return radix__pmd_same(pmd_a, pmd_b); 1186 return hash__pmd_same(pmd_a, pmd_b); 1187 } 1188 1189 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1190 { 1191 if (radix_enabled()) 1192 return radix__pmd_mkhuge(pmd); 1193 return hash__pmd_mkhuge(pmd); 1194 } 1195 1196 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1197 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1198 unsigned long address, pmd_t *pmdp, 1199 pmd_t entry, int dirty); 1200 1201 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1202 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1203 unsigned long address, pmd_t *pmdp); 1204 1205 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1206 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1207 unsigned long addr, pmd_t *pmdp) 1208 { 1209 if (radix_enabled()) 1210 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1211 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1212 } 1213 1214 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1215 unsigned long address, pmd_t *pmdp) 1216 { 1217 if (radix_enabled()) 1218 return radix__pmdp_collapse_flush(vma, address, pmdp); 1219 return hash__pmdp_collapse_flush(vma, address, pmdp); 1220 } 1221 #define pmdp_collapse_flush pmdp_collapse_flush 1222 1223 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1224 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1225 pmd_t *pmdp, pgtable_t pgtable) 1226 { 1227 if (radix_enabled()) 1228 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1229 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1230 } 1231 1232 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1233 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1234 pmd_t *pmdp) 1235 { 1236 if (radix_enabled()) 1237 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1238 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1239 } 1240 1241 #define __HAVE_ARCH_PMDP_INVALIDATE 1242 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1243 pmd_t *pmdp); 1244 1245 #define pmd_move_must_withdraw pmd_move_must_withdraw 1246 struct spinlock; 1247 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1248 struct spinlock *old_pmd_ptl, 1249 struct vm_area_struct *vma); 1250 /* 1251 * Hash translation mode use the deposited table to store hash pte 1252 * slot information. 1253 */ 1254 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1255 static inline bool arch_needs_pgtable_deposit(void) 1256 { 1257 if (radix_enabled()) 1258 return false; 1259 return true; 1260 } 1261 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1262 1263 1264 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1265 { 1266 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1267 } 1268 1269 static inline int pmd_devmap(pmd_t pmd) 1270 { 1271 return pte_devmap(pmd_pte(pmd)); 1272 } 1273 1274 static inline int pud_devmap(pud_t pud) 1275 { 1276 return 0; 1277 } 1278 1279 static inline int pgd_devmap(pgd_t pgd) 1280 { 1281 return 0; 1282 } 1283 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1284 1285 static inline int pud_pfn(pud_t pud) 1286 { 1287 /* 1288 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1289 * check so this should never be used. If it grows another user we 1290 * want to know about it. 1291 */ 1292 BUILD_BUG(); 1293 return 0; 1294 } 1295 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1296 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1297 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1298 pte_t *, pte_t, pte_t); 1299 1300 /* 1301 * Returns true for a R -> RW upgrade of pte 1302 */ 1303 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1304 { 1305 if (!(old_val & _PAGE_READ)) 1306 return false; 1307 1308 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1309 return true; 1310 1311 return false; 1312 } 1313 1314 #endif /* __ASSEMBLY__ */ 1315 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1316