1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_ 3 #define _ASM_POWERPC_BOOK3S_64_MMU_H_ 4 5 #include <asm/page.h> 6 7 #ifndef __ASSEMBLY__ 8 /* 9 * Page size definition 10 * 11 * shift : is the "PAGE_SHIFT" value for that page size 12 * sllp : is a bit mask with the value of SLB L || LP to be or'ed 13 * directly to a slbmte "vsid" value 14 * penc : is the HPTE encoding mask for the "LP" field: 15 * 16 */ 17 struct mmu_psize_def { 18 unsigned int shift; /* number of bits */ 19 int penc[MMU_PAGE_COUNT]; /* HPTE encoding */ 20 unsigned int tlbiel; /* tlbiel supported for that page size */ 21 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ 22 union { 23 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ 24 unsigned long ap; /* Ap encoding used by PowerISA 3.0 */ 25 }; 26 }; 27 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 28 29 /* 30 * For BOOK3s 64 with 4k and 64K linux page size 31 * we want to use pointers, because the page table 32 * actually store pfn 33 */ 34 typedef pte_t *pgtable_t; 35 36 #endif /* __ASSEMBLY__ */ 37 38 /* 64-bit classic hash table MMU */ 39 #include <asm/book3s/64/mmu-hash.h> 40 41 #ifndef __ASSEMBLY__ 42 /* 43 * ISA 3.0 partition and process table entry format 44 */ 45 struct prtb_entry { 46 __be64 prtb0; 47 __be64 prtb1; 48 }; 49 extern struct prtb_entry *process_tb; 50 51 struct patb_entry { 52 __be64 patb0; 53 __be64 patb1; 54 }; 55 extern struct patb_entry *partition_tb; 56 57 /* Bits in patb0 field */ 58 #define PATB_HR (1UL << 63) 59 #define RPDB_MASK 0x0fffffffffffff00UL 60 #define RPDB_SHIFT (1UL << 8) 61 #define RTS1_SHIFT 61 /* top 2 bits of radix tree size */ 62 #define RTS1_MASK (3UL << RTS1_SHIFT) 63 #define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */ 64 #define RTS2_MASK (7UL << RTS2_SHIFT) 65 #define RPDS_MASK 0x1f /* root page dir. size field */ 66 67 /* Bits in patb1 field */ 68 #define PATB_GR (1UL << 63) /* guest uses radix; must match HR */ 69 #define PRTS_MASK 0x1f /* process table size field */ 70 #define PRTB_MASK 0x0ffffffffffff000UL 71 72 /* Number of supported PID bits */ 73 extern unsigned int mmu_pid_bits; 74 75 /* Base PID to allocate from */ 76 extern unsigned int mmu_base_pid; 77 78 #define PRTB_SIZE_SHIFT (mmu_pid_bits + 4) 79 #define PRTB_ENTRIES (1ul << mmu_pid_bits) 80 81 /* 82 * Power9 currently only support 64K partition table size. 83 */ 84 #define PATB_SIZE_SHIFT 16 85 86 typedef unsigned long mm_context_id_t; 87 struct spinlock; 88 89 /* Maximum possible number of NPUs in a system. */ 90 #define NV_MAX_NPUS 8 91 92 /* 93 * One bit per slice. We have lower slices which cover 256MB segments 94 * upto 4G range. That gets us 16 low slices. For the rest we track slices 95 * in 1TB size. 96 */ 97 struct slice_mask { 98 u64 low_slices; 99 DECLARE_BITMAP(high_slices, SLICE_NUM_HIGH); 100 }; 101 102 typedef struct { 103 union { 104 /* 105 * We use id as the PIDR content for radix. On hash we can use 106 * more than one id. The extended ids are used when we start 107 * having address above 512TB. We allocate one extended id 108 * for each 512TB. The new id is then used with the 49 bit 109 * EA to build a new VA. We always use ESID_BITS_1T_MASK bits 110 * from EA and new context ids to build the new VAs. 111 */ 112 mm_context_id_t id; 113 mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE]; 114 }; 115 u16 user_psize; /* page size index */ 116 117 /* Number of bits in the mm_cpumask */ 118 atomic_t active_cpus; 119 120 /* Number of users of the external (Nest) MMU */ 121 atomic_t copros; 122 123 /* NPU NMMU context */ 124 struct npu_context *npu_context; 125 126 #ifdef CONFIG_PPC_MM_SLICES 127 /* SLB page size encodings*/ 128 unsigned char low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE]; 129 unsigned char high_slices_psize[SLICE_ARRAY_SIZE]; 130 unsigned long slb_addr_limit; 131 # ifdef CONFIG_PPC_64K_PAGES 132 struct slice_mask mask_64k; 133 # endif 134 struct slice_mask mask_4k; 135 # ifdef CONFIG_HUGETLB_PAGE 136 struct slice_mask mask_16m; 137 struct slice_mask mask_16g; 138 # endif 139 #else 140 u16 sllp; /* SLB page size encoding */ 141 #endif 142 unsigned long vdso_base; 143 #ifdef CONFIG_PPC_SUBPAGE_PROT 144 struct subpage_prot_table spt; 145 #endif /* CONFIG_PPC_SUBPAGE_PROT */ 146 /* 147 * pagetable fragment support 148 */ 149 void *pte_frag; 150 void *pmd_frag; 151 #ifdef CONFIG_SPAPR_TCE_IOMMU 152 struct list_head iommu_group_mem_list; 153 #endif 154 155 #ifdef CONFIG_PPC_MEM_KEYS 156 /* 157 * Each bit represents one protection key. 158 * bit set -> key allocated 159 * bit unset -> key available for allocation 160 */ 161 u32 pkey_allocation_map; 162 s16 execute_only_pkey; /* key holding execute-only protection */ 163 #endif 164 } mm_context_t; 165 166 /* 167 * The current system page and segment sizes 168 */ 169 extern int mmu_linear_psize; 170 extern int mmu_virtual_psize; 171 extern int mmu_vmalloc_psize; 172 extern int mmu_vmemmap_psize; 173 extern int mmu_io_psize; 174 175 /* MMU initialization */ 176 void mmu_early_init_devtree(void); 177 void hash__early_init_devtree(void); 178 void radix__early_init_devtree(void); 179 extern void radix_init_native(void); 180 extern void hash__early_init_mmu(void); 181 extern void radix__early_init_mmu(void); 182 static inline void early_init_mmu(void) 183 { 184 if (radix_enabled()) 185 return radix__early_init_mmu(); 186 return hash__early_init_mmu(); 187 } 188 extern void hash__early_init_mmu_secondary(void); 189 extern void radix__early_init_mmu_secondary(void); 190 static inline void early_init_mmu_secondary(void) 191 { 192 if (radix_enabled()) 193 return radix__early_init_mmu_secondary(); 194 return hash__early_init_mmu_secondary(); 195 } 196 197 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, 198 phys_addr_t first_memblock_size); 199 extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base, 200 phys_addr_t first_memblock_size); 201 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base, 202 phys_addr_t first_memblock_size) 203 { 204 if (early_radix_enabled()) 205 return radix__setup_initial_memory_limit(first_memblock_base, 206 first_memblock_size); 207 return hash__setup_initial_memory_limit(first_memblock_base, 208 first_memblock_size); 209 } 210 211 extern int (*register_process_table)(unsigned long base, unsigned long page_size, 212 unsigned long tbl_size); 213 214 #ifdef CONFIG_PPC_PSERIES 215 extern void radix_init_pseries(void); 216 #else 217 static inline void radix_init_pseries(void) { }; 218 #endif 219 220 static inline int get_user_context(mm_context_t *ctx, unsigned long ea) 221 { 222 int index = ea >> MAX_EA_BITS_PER_CONTEXT; 223 224 if (likely(index < ARRAY_SIZE(ctx->extended_id))) 225 return ctx->extended_id[index]; 226 227 /* should never happen */ 228 WARN_ON(1); 229 return 0; 230 } 231 232 static inline unsigned long get_user_vsid(mm_context_t *ctx, 233 unsigned long ea, int ssize) 234 { 235 unsigned long context = get_user_context(ctx, ea); 236 237 return get_vsid(context, ea, ssize); 238 } 239 240 #endif /* __ASSEMBLY__ */ 241 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */ 242