1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
3 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
4 
5 #include <asm/page.h>
6 
7 #ifndef __ASSEMBLY__
8 /*
9  * Page size definition
10  *
11  *    shift : is the "PAGE_SHIFT" value for that page size
12  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
13  *            directly to a slbmte "vsid" value
14  *    penc  : is the HPTE encoding mask for the "LP" field:
15  *
16  */
17 struct mmu_psize_def {
18 	unsigned int	shift;	/* number of bits */
19 	int		penc[MMU_PAGE_COUNT];	/* HPTE encoding */
20 	unsigned int	tlbiel;	/* tlbiel supported for that page size */
21 	unsigned long	avpnm;	/* bits to mask out in AVPN in the HPTE */
22 	union {
23 		unsigned long	sllp;	/* SLB L||LP (exact mask to use in slbmte) */
24 		unsigned long ap;	/* Ap encoding used by PowerISA 3.0 */
25 	};
26 };
27 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
28 #endif /* __ASSEMBLY__ */
29 
30 /* 64-bit classic hash table MMU */
31 #include <asm/book3s/64/mmu-hash.h>
32 
33 #ifndef __ASSEMBLY__
34 /*
35  * ISA 3.0 partition and process table entry format
36  */
37 struct prtb_entry {
38 	__be64 prtb0;
39 	__be64 prtb1;
40 };
41 extern struct prtb_entry *process_tb;
42 
43 struct patb_entry {
44 	__be64 patb0;
45 	__be64 patb1;
46 };
47 extern struct patb_entry *partition_tb;
48 
49 /* Bits in patb0 field */
50 #define PATB_HR		(1UL << 63)
51 #define RPDB_MASK	0x0fffffffffffff00UL
52 #define RPDB_SHIFT	(1UL << 8)
53 #define RTS1_SHIFT	61		/* top 2 bits of radix tree size */
54 #define RTS1_MASK	(3UL << RTS1_SHIFT)
55 #define RTS2_SHIFT	5		/* bottom 3 bits of radix tree size */
56 #define RTS2_MASK	(7UL << RTS2_SHIFT)
57 #define RPDS_MASK	0x1f		/* root page dir. size field */
58 
59 /* Bits in patb1 field */
60 #define PATB_GR		(1UL << 63)	/* guest uses radix; must match HR */
61 #define PRTS_MASK	0x1f		/* process table size field */
62 #define PRTB_MASK	0x0ffffffffffff000UL
63 
64 /* Number of supported PID bits */
65 extern unsigned int mmu_pid_bits;
66 
67 /* Base PID to allocate from */
68 extern unsigned int mmu_base_pid;
69 
70 /*
71  * memory block size used with radix translation.
72  */
73 extern unsigned long __ro_after_init radix_mem_block_size;
74 
75 #define PRTB_SIZE_SHIFT	(mmu_pid_bits + 4)
76 #define PRTB_ENTRIES	(1ul << mmu_pid_bits)
77 
78 /*
79  * Power9 currently only support 64K partition table size.
80  */
81 #define PATB_SIZE_SHIFT	16
82 
83 typedef unsigned long mm_context_id_t;
84 struct spinlock;
85 
86 /* Maximum possible number of NPUs in a system. */
87 #define NV_MAX_NPUS 8
88 
89 typedef struct {
90 	union {
91 		/*
92 		 * We use id as the PIDR content for radix. On hash we can use
93 		 * more than one id. The extended ids are used when we start
94 		 * having address above 512TB. We allocate one extended id
95 		 * for each 512TB. The new id is then used with the 49 bit
96 		 * EA to build a new VA. We always use ESID_BITS_1T_MASK bits
97 		 * from EA and new context ids to build the new VAs.
98 		 */
99 		mm_context_id_t id;
100 		mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE];
101 	};
102 
103 	/* Number of bits in the mm_cpumask */
104 	atomic_t active_cpus;
105 
106 	/* Number of users of the external (Nest) MMU */
107 	atomic_t copros;
108 
109 	/* Number of user space windows opened in process mm_context */
110 	atomic_t vas_windows;
111 
112 	struct hash_mm_context *hash_context;
113 
114 	unsigned long vdso_base;
115 	/*
116 	 * pagetable fragment support
117 	 */
118 	void *pte_frag;
119 	void *pmd_frag;
120 #ifdef CONFIG_SPAPR_TCE_IOMMU
121 	struct list_head iommu_group_mem_list;
122 #endif
123 
124 #ifdef CONFIG_PPC_MEM_KEYS
125 	/*
126 	 * Each bit represents one protection key.
127 	 * bit set   -> key allocated
128 	 * bit unset -> key available for allocation
129 	 */
130 	u32 pkey_allocation_map;
131 	s16 execute_only_pkey; /* key holding execute-only protection */
132 #endif
133 } mm_context_t;
134 
135 static inline u16 mm_ctx_user_psize(mm_context_t *ctx)
136 {
137 	return ctx->hash_context->user_psize;
138 }
139 
140 static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize)
141 {
142 	ctx->hash_context->user_psize = user_psize;
143 }
144 
145 static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx)
146 {
147 	return ctx->hash_context->low_slices_psize;
148 }
149 
150 static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx)
151 {
152 	return ctx->hash_context->high_slices_psize;
153 }
154 
155 static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx)
156 {
157 	return ctx->hash_context->slb_addr_limit;
158 }
159 
160 static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit)
161 {
162 	ctx->hash_context->slb_addr_limit = limit;
163 }
164 
165 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)
166 {
167 #ifdef CONFIG_PPC_64K_PAGES
168 	if (psize == MMU_PAGE_64K)
169 		return &ctx->hash_context->mask_64k;
170 #endif
171 #ifdef CONFIG_HUGETLB_PAGE
172 	if (psize == MMU_PAGE_16M)
173 		return &ctx->hash_context->mask_16m;
174 	if (psize == MMU_PAGE_16G)
175 		return &ctx->hash_context->mask_16g;
176 #endif
177 	BUG_ON(psize != MMU_PAGE_4K);
178 
179 	return &ctx->hash_context->mask_4k;
180 }
181 
182 #ifdef CONFIG_PPC_SUBPAGE_PROT
183 static inline struct subpage_prot_table *mm_ctx_subpage_prot(mm_context_t *ctx)
184 {
185 	return ctx->hash_context->spt;
186 }
187 #endif
188 
189 /*
190  * The current system page and segment sizes
191  */
192 extern int mmu_linear_psize;
193 extern int mmu_virtual_psize;
194 extern int mmu_vmalloc_psize;
195 extern int mmu_vmemmap_psize;
196 extern int mmu_io_psize;
197 
198 /* MMU initialization */
199 void mmu_early_init_devtree(void);
200 void hash__early_init_devtree(void);
201 void radix__early_init_devtree(void);
202 #ifdef CONFIG_PPC_MEM_KEYS
203 void pkey_early_init_devtree(void);
204 #else
205 static inline void pkey_early_init_devtree(void) {}
206 #endif
207 
208 extern void hash__early_init_mmu(void);
209 extern void radix__early_init_mmu(void);
210 static inline void __init early_init_mmu(void)
211 {
212 	if (radix_enabled())
213 		return radix__early_init_mmu();
214 	return hash__early_init_mmu();
215 }
216 extern void hash__early_init_mmu_secondary(void);
217 extern void radix__early_init_mmu_secondary(void);
218 static inline void early_init_mmu_secondary(void)
219 {
220 	if (radix_enabled())
221 		return radix__early_init_mmu_secondary();
222 	return hash__early_init_mmu_secondary();
223 }
224 
225 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
226 					 phys_addr_t first_memblock_size);
227 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
228 					      phys_addr_t first_memblock_size)
229 {
230 	/*
231 	 * Hash has more strict restrictions. At this point we don't
232 	 * know which translations we will pick. Hence go with hash
233 	 * restrictions.
234 	 */
235 	return hash__setup_initial_memory_limit(first_memblock_base,
236 					   first_memblock_size);
237 }
238 
239 #ifdef CONFIG_PPC_PSERIES
240 extern void radix_init_pseries(void);
241 #else
242 static inline void radix_init_pseries(void) { };
243 #endif
244 
245 static inline int get_user_context(mm_context_t *ctx, unsigned long ea)
246 {
247 	int index = ea >> MAX_EA_BITS_PER_CONTEXT;
248 
249 	if (likely(index < ARRAY_SIZE(ctx->extended_id)))
250 		return ctx->extended_id[index];
251 
252 	/* should never happen */
253 	WARN_ON(1);
254 	return 0;
255 }
256 
257 static inline unsigned long get_user_vsid(mm_context_t *ctx,
258 					  unsigned long ea, int ssize)
259 {
260 	unsigned long context = get_user_context(ctx, ea);
261 
262 	return get_vsid(context, ea, ssize);
263 }
264 
265 #endif /* __ASSEMBLY__ */
266 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
267