1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_ 3 #define _ASM_POWERPC_BOOK3S_64_MMU_H_ 4 5 #include <asm/page.h> 6 7 #ifndef __ASSEMBLY__ 8 /* 9 * Page size definition 10 * 11 * shift : is the "PAGE_SHIFT" value for that page size 12 * sllp : is a bit mask with the value of SLB L || LP to be or'ed 13 * directly to a slbmte "vsid" value 14 * penc : is the HPTE encoding mask for the "LP" field: 15 * 16 */ 17 struct mmu_psize_def { 18 unsigned int shift; /* number of bits */ 19 int penc[MMU_PAGE_COUNT]; /* HPTE encoding */ 20 unsigned int tlbiel; /* tlbiel supported for that page size */ 21 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ 22 unsigned long h_rpt_pgsize; /* H_RPT_INVALIDATE page size encoding */ 23 union { 24 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ 25 unsigned long ap; /* Ap encoding used by PowerISA 3.0 */ 26 }; 27 }; 28 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 29 #endif /* __ASSEMBLY__ */ 30 31 /* 64-bit classic hash table MMU */ 32 #include <asm/book3s/64/mmu-hash.h> 33 34 #ifndef __ASSEMBLY__ 35 /* 36 * ISA 3.0 partition and process table entry format 37 */ 38 struct prtb_entry { 39 __be64 prtb0; 40 __be64 prtb1; 41 }; 42 extern struct prtb_entry *process_tb; 43 44 struct patb_entry { 45 __be64 patb0; 46 __be64 patb1; 47 }; 48 extern struct patb_entry *partition_tb; 49 50 /* Bits in patb0 field */ 51 #define PATB_HR (1UL << 63) 52 #define RPDB_MASK 0x0fffffffffffff00UL 53 #define RPDB_SHIFT (1UL << 8) 54 #define RTS1_SHIFT 61 /* top 2 bits of radix tree size */ 55 #define RTS1_MASK (3UL << RTS1_SHIFT) 56 #define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */ 57 #define RTS2_MASK (7UL << RTS2_SHIFT) 58 #define RPDS_MASK 0x1f /* root page dir. size field */ 59 60 /* Bits in patb1 field */ 61 #define PATB_GR (1UL << 63) /* guest uses radix; must match HR */ 62 #define PRTS_MASK 0x1f /* process table size field */ 63 #define PRTB_MASK 0x0ffffffffffff000UL 64 65 /* Number of supported LPID bits */ 66 extern unsigned int mmu_lpid_bits; 67 68 /* Number of supported PID bits */ 69 extern unsigned int mmu_pid_bits; 70 71 /* Base PID to allocate from */ 72 extern unsigned int mmu_base_pid; 73 74 /* 75 * memory block size used with radix translation. 76 */ 77 extern unsigned long __ro_after_init radix_mem_block_size; 78 79 #define PRTB_SIZE_SHIFT (mmu_pid_bits + 4) 80 #define PRTB_ENTRIES (1ul << mmu_pid_bits) 81 82 #define PATB_SIZE_SHIFT (mmu_lpid_bits + 4) 83 #define PATB_ENTRIES (1ul << mmu_lpid_bits) 84 85 typedef unsigned long mm_context_id_t; 86 struct spinlock; 87 88 /* Maximum possible number of NPUs in a system. */ 89 #define NV_MAX_NPUS 8 90 91 typedef struct { 92 union { 93 /* 94 * We use id as the PIDR content for radix. On hash we can use 95 * more than one id. The extended ids are used when we start 96 * having address above 512TB. We allocate one extended id 97 * for each 512TB. The new id is then used with the 49 bit 98 * EA to build a new VA. We always use ESID_BITS_1T_MASK bits 99 * from EA and new context ids to build the new VAs. 100 */ 101 mm_context_id_t id; 102 mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE]; 103 }; 104 105 /* Number of bits in the mm_cpumask */ 106 atomic_t active_cpus; 107 108 /* Number of users of the external (Nest) MMU */ 109 atomic_t copros; 110 111 /* Number of user space windows opened in process mm_context */ 112 atomic_t vas_windows; 113 114 struct hash_mm_context *hash_context; 115 116 void __user *vdso; 117 /* 118 * pagetable fragment support 119 */ 120 void *pte_frag; 121 void *pmd_frag; 122 #ifdef CONFIG_SPAPR_TCE_IOMMU 123 struct list_head iommu_group_mem_list; 124 #endif 125 126 #ifdef CONFIG_PPC_MEM_KEYS 127 /* 128 * Each bit represents one protection key. 129 * bit set -> key allocated 130 * bit unset -> key available for allocation 131 */ 132 u32 pkey_allocation_map; 133 s16 execute_only_pkey; /* key holding execute-only protection */ 134 #endif 135 } mm_context_t; 136 137 static inline u16 mm_ctx_user_psize(mm_context_t *ctx) 138 { 139 return ctx->hash_context->user_psize; 140 } 141 142 static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize) 143 { 144 ctx->hash_context->user_psize = user_psize; 145 } 146 147 static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx) 148 { 149 return ctx->hash_context->low_slices_psize; 150 } 151 152 static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx) 153 { 154 return ctx->hash_context->high_slices_psize; 155 } 156 157 static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx) 158 { 159 return ctx->hash_context->slb_addr_limit; 160 } 161 162 static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit) 163 { 164 ctx->hash_context->slb_addr_limit = limit; 165 } 166 167 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize) 168 { 169 #ifdef CONFIG_PPC_64K_PAGES 170 if (psize == MMU_PAGE_64K) 171 return &ctx->hash_context->mask_64k; 172 #endif 173 #ifdef CONFIG_HUGETLB_PAGE 174 if (psize == MMU_PAGE_16M) 175 return &ctx->hash_context->mask_16m; 176 if (psize == MMU_PAGE_16G) 177 return &ctx->hash_context->mask_16g; 178 #endif 179 BUG_ON(psize != MMU_PAGE_4K); 180 181 return &ctx->hash_context->mask_4k; 182 } 183 184 #ifdef CONFIG_PPC_SUBPAGE_PROT 185 static inline struct subpage_prot_table *mm_ctx_subpage_prot(mm_context_t *ctx) 186 { 187 return ctx->hash_context->spt; 188 } 189 #endif 190 191 /* 192 * The current system page and segment sizes 193 */ 194 extern int mmu_linear_psize; 195 extern int mmu_virtual_psize; 196 extern int mmu_vmalloc_psize; 197 extern int mmu_vmemmap_psize; 198 extern int mmu_io_psize; 199 200 /* MMU initialization */ 201 void mmu_early_init_devtree(void); 202 void hash__early_init_devtree(void); 203 void radix__early_init_devtree(void); 204 #ifdef CONFIG_PPC_PKEY 205 void pkey_early_init_devtree(void); 206 #else 207 static inline void pkey_early_init_devtree(void) {} 208 #endif 209 210 extern void hash__early_init_mmu(void); 211 extern void radix__early_init_mmu(void); 212 static inline void __init early_init_mmu(void) 213 { 214 if (radix_enabled()) 215 return radix__early_init_mmu(); 216 return hash__early_init_mmu(); 217 } 218 extern void hash__early_init_mmu_secondary(void); 219 extern void radix__early_init_mmu_secondary(void); 220 static inline void early_init_mmu_secondary(void) 221 { 222 if (radix_enabled()) 223 return radix__early_init_mmu_secondary(); 224 return hash__early_init_mmu_secondary(); 225 } 226 227 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, 228 phys_addr_t first_memblock_size); 229 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base, 230 phys_addr_t first_memblock_size) 231 { 232 /* 233 * Hash has more strict restrictions. At this point we don't 234 * know which translations we will pick. Hence go with hash 235 * restrictions. 236 */ 237 return hash__setup_initial_memory_limit(first_memblock_base, 238 first_memblock_size); 239 } 240 241 #ifdef CONFIG_PPC_PSERIES 242 extern void radix_init_pseries(void); 243 #else 244 static inline void radix_init_pseries(void) { } 245 #endif 246 247 #ifdef CONFIG_HOTPLUG_CPU 248 #define arch_clear_mm_cpumask_cpu(cpu, mm) \ 249 do { \ 250 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { \ 251 atomic_dec(&(mm)->context.active_cpus); \ 252 cpumask_clear_cpu(cpu, mm_cpumask(mm)); \ 253 } \ 254 } while (0) 255 256 void cleanup_cpu_mmu_context(void); 257 #endif 258 259 static inline int get_user_context(mm_context_t *ctx, unsigned long ea) 260 { 261 int index = ea >> MAX_EA_BITS_PER_CONTEXT; 262 263 if (likely(index < ARRAY_SIZE(ctx->extended_id))) 264 return ctx->extended_id[index]; 265 266 /* should never happen */ 267 WARN_ON(1); 268 return 0; 269 } 270 271 static inline unsigned long get_user_vsid(mm_context_t *ctx, 272 unsigned long ea, int ssize) 273 { 274 unsigned long context = get_user_context(ctx, ea); 275 276 return get_vsid(context, ea, ssize); 277 } 278 279 #endif /* __ASSEMBLY__ */ 280 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */ 281