1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ 2 #define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ 3 /* 4 * PowerPC64 memory management structures 5 * 6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com> 7 * PPC64 rework. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 15 #include <asm/asm-compat.h> 16 #include <asm/page.h> 17 #include <asm/bug.h> 18 19 /* 20 * This is necessary to get the definition of PGTABLE_RANGE which we 21 * need for various slices related matters. Note that this isn't the 22 * complete pgtable.h but only a portion of it. 23 */ 24 #include <asm/book3s/64/pgtable.h> 25 #include <asm/bug.h> 26 #include <asm/processor.h> 27 #include <asm/cpu_has_feature.h> 28 29 /* 30 * SLB 31 */ 32 33 #define SLB_NUM_BOLTED 3 34 #define SLB_CACHE_ENTRIES 8 35 #define SLB_MIN_SIZE 32 36 37 /* Bits in the SLB ESID word */ 38 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */ 39 40 /* Bits in the SLB VSID word */ 41 #define SLB_VSID_SHIFT 12 42 #define SLB_VSID_SHIFT_1T 24 43 #define SLB_VSID_SSIZE_SHIFT 62 44 #define SLB_VSID_B ASM_CONST(0xc000000000000000) 45 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000) 46 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000) 47 #define SLB_VSID_KS ASM_CONST(0x0000000000000800) 48 #define SLB_VSID_KP ASM_CONST(0x0000000000000400) 49 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ 50 #define SLB_VSID_L ASM_CONST(0x0000000000000100) 51 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */ 52 #define SLB_VSID_LP ASM_CONST(0x0000000000000030) 53 #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000) 54 #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010) 55 #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020) 56 #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030) 57 #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP) 58 59 #define SLB_VSID_KERNEL (SLB_VSID_KP) 60 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C) 61 62 #define SLBIE_C (0x08000000) 63 #define SLBIE_SSIZE_SHIFT 25 64 65 /* 66 * Hash table 67 */ 68 69 #define HPTES_PER_GROUP 8 70 71 #define HPTE_V_SSIZE_SHIFT 62 72 #define HPTE_V_AVPN_SHIFT 7 73 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) 74 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) 75 #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) 76 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) 77 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008) 78 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004) 79 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002) 80 #define HPTE_V_VALID ASM_CONST(0x0000000000000001) 81 82 /* 83 * ISA 3.0 have a different HPTE format. 84 */ 85 #define HPTE_R_3_0_SSIZE_SHIFT 58 86 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000) 87 #define HPTE_R_TS ASM_CONST(0x4000000000000000) 88 #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000) 89 #define HPTE_R_RPN_SHIFT 12 90 #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000) 91 #define HPTE_R_PP ASM_CONST(0x0000000000000003) 92 #define HPTE_R_PPP ASM_CONST(0x8000000000000003) 93 #define HPTE_R_N ASM_CONST(0x0000000000000004) 94 #define HPTE_R_G ASM_CONST(0x0000000000000008) 95 #define HPTE_R_M ASM_CONST(0x0000000000000010) 96 #define HPTE_R_I ASM_CONST(0x0000000000000020) 97 #define HPTE_R_W ASM_CONST(0x0000000000000040) 98 #define HPTE_R_WIMG ASM_CONST(0x0000000000000078) 99 #define HPTE_R_C ASM_CONST(0x0000000000000080) 100 #define HPTE_R_R ASM_CONST(0x0000000000000100) 101 #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00) 102 103 #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000) 104 #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000) 105 106 /* Values for PP (assumes Ks=0, Kp=1) */ 107 #define PP_RWXX 0 /* Supervisor read/write, User none */ 108 #define PP_RWRX 1 /* Supervisor read/write, User read */ 109 #define PP_RWRW 2 /* Supervisor read/write, User read/write */ 110 #define PP_RXRX 3 /* Supervisor read, User read */ 111 #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */ 112 113 /* Fields for tlbiel instruction in architecture 2.06 */ 114 #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */ 115 #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */ 116 #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */ 117 #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */ 118 #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */ 119 #define TLBIEL_INVAL_SET_SHIFT 12 120 121 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */ 122 #define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */ 123 #define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */ 124 #define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */ 125 126 #ifndef __ASSEMBLY__ 127 128 struct mmu_hash_ops { 129 void (*hpte_invalidate)(unsigned long slot, 130 unsigned long vpn, 131 int bpsize, int apsize, 132 int ssize, int local); 133 long (*hpte_updatepp)(unsigned long slot, 134 unsigned long newpp, 135 unsigned long vpn, 136 int bpsize, int apsize, 137 int ssize, unsigned long flags); 138 void (*hpte_updateboltedpp)(unsigned long newpp, 139 unsigned long ea, 140 int psize, int ssize); 141 long (*hpte_insert)(unsigned long hpte_group, 142 unsigned long vpn, 143 unsigned long prpn, 144 unsigned long rflags, 145 unsigned long vflags, 146 int psize, int apsize, 147 int ssize); 148 long (*hpte_remove)(unsigned long hpte_group); 149 int (*hpte_removebolted)(unsigned long ea, 150 int psize, int ssize); 151 void (*flush_hash_range)(unsigned long number, int local); 152 void (*hugepage_invalidate)(unsigned long vsid, 153 unsigned long addr, 154 unsigned char *hpte_slot_array, 155 int psize, int ssize, int local); 156 /* 157 * Special for kexec. 158 * To be called in real mode with interrupts disabled. No locks are 159 * taken as such, concurrent access on pre POWER5 hardware could result 160 * in a deadlock. 161 * The linear mapping is destroyed as well. 162 */ 163 void (*hpte_clear_all)(void); 164 }; 165 extern struct mmu_hash_ops mmu_hash_ops; 166 167 struct hash_pte { 168 __be64 v; 169 __be64 r; 170 }; 171 172 extern struct hash_pte *htab_address; 173 extern unsigned long htab_size_bytes; 174 extern unsigned long htab_hash_mask; 175 176 177 static inline int shift_to_mmu_psize(unsigned int shift) 178 { 179 int psize; 180 181 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) 182 if (mmu_psize_defs[psize].shift == shift) 183 return psize; 184 return -1; 185 } 186 187 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) 188 { 189 if (mmu_psize_defs[mmu_psize].shift) 190 return mmu_psize_defs[mmu_psize].shift; 191 BUG(); 192 } 193 194 static inline unsigned long get_sllp_encoding(int psize) 195 { 196 unsigned long sllp; 197 198 sllp = ((mmu_psize_defs[psize].sllp & SLB_VSID_L) >> 6) | 199 ((mmu_psize_defs[psize].sllp & SLB_VSID_LP) >> 4); 200 return sllp; 201 } 202 203 #endif /* __ASSEMBLY__ */ 204 205 /* 206 * Segment sizes. 207 * These are the values used by hardware in the B field of 208 * SLB entries and the first dword of MMU hashtable entries. 209 * The B field is 2 bits; the values 2 and 3 are unused and reserved. 210 */ 211 #define MMU_SEGSIZE_256M 0 212 #define MMU_SEGSIZE_1T 1 213 214 /* 215 * encode page number shift. 216 * in order to fit the 78 bit va in a 64 bit variable we shift the va by 217 * 12 bits. This enable us to address upto 76 bit va. 218 * For hpt hash from a va we can ignore the page size bits of va and for 219 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure 220 * we work in all cases including 4k page size. 221 */ 222 #define VPN_SHIFT 12 223 224 /* 225 * HPTE Large Page (LP) details 226 */ 227 #define LP_SHIFT 12 228 #define LP_BITS 8 229 #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) 230 231 #ifndef __ASSEMBLY__ 232 233 static inline int slb_vsid_shift(int ssize) 234 { 235 if (ssize == MMU_SEGSIZE_256M) 236 return SLB_VSID_SHIFT; 237 return SLB_VSID_SHIFT_1T; 238 } 239 240 static inline int segment_shift(int ssize) 241 { 242 if (ssize == MMU_SEGSIZE_256M) 243 return SID_SHIFT; 244 return SID_SHIFT_1T; 245 } 246 247 /* 248 * The current system page and segment sizes 249 */ 250 extern int mmu_kernel_ssize; 251 extern int mmu_highuser_ssize; 252 extern u16 mmu_slb_size; 253 extern unsigned long tce_alloc_start, tce_alloc_end; 254 255 /* 256 * If the processor supports 64k normal pages but not 64k cache 257 * inhibited pages, we have to be prepared to switch processes 258 * to use 4k pages when they create cache-inhibited mappings. 259 * If this is the case, mmu_ci_restrictions will be set to 1. 260 */ 261 extern int mmu_ci_restrictions; 262 263 /* 264 * This computes the AVPN and B fields of the first dword of a HPTE, 265 * for use when we want to match an existing PTE. The bottom 7 bits 266 * of the returned value are zero. 267 */ 268 static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize, 269 int ssize) 270 { 271 unsigned long v; 272 /* 273 * The AVA field omits the low-order 23 bits of the 78 bits VA. 274 * These bits are not needed in the PTE, because the 275 * low-order b of these bits are part of the byte offset 276 * into the virtual page and, if b < 23, the high-order 277 * 23-b of these bits are always used in selecting the 278 * PTEGs to be searched 279 */ 280 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm); 281 v <<= HPTE_V_AVPN_SHIFT; 282 if (!cpu_has_feature(CPU_FTR_ARCH_300)) 283 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT; 284 return v; 285 } 286 287 /* 288 * This function sets the AVPN and L fields of the HPTE appropriately 289 * using the base page size and actual page size. 290 */ 291 static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize, 292 int actual_psize, int ssize) 293 { 294 unsigned long v; 295 v = hpte_encode_avpn(vpn, base_psize, ssize); 296 if (actual_psize != MMU_PAGE_4K) 297 v |= HPTE_V_LARGE; 298 return v; 299 } 300 301 /* 302 * This function sets the ARPN, and LP fields of the HPTE appropriately 303 * for the page size. We assume the pa is already "clean" that is properly 304 * aligned for the requested page size 305 */ 306 static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize, 307 int actual_psize, int ssize) 308 { 309 310 if (cpu_has_feature(CPU_FTR_ARCH_300)) 311 pa |= ((unsigned long) ssize) << HPTE_R_3_0_SSIZE_SHIFT; 312 313 /* A 4K page needs no special encoding */ 314 if (actual_psize == MMU_PAGE_4K) 315 return pa & HPTE_R_RPN; 316 else { 317 unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize]; 318 unsigned int shift = mmu_psize_defs[actual_psize].shift; 319 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT); 320 } 321 } 322 323 /* 324 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size. 325 */ 326 static inline unsigned long hpt_vpn(unsigned long ea, 327 unsigned long vsid, int ssize) 328 { 329 unsigned long mask; 330 int s_shift = segment_shift(ssize); 331 332 mask = (1ul << (s_shift - VPN_SHIFT)) - 1; 333 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask); 334 } 335 336 /* 337 * This hashes a virtual address 338 */ 339 static inline unsigned long hpt_hash(unsigned long vpn, 340 unsigned int shift, int ssize) 341 { 342 int mask; 343 unsigned long hash, vsid; 344 345 /* VPN_SHIFT can be atmost 12 */ 346 if (ssize == MMU_SEGSIZE_256M) { 347 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1; 348 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^ 349 ((vpn & mask) >> (shift - VPN_SHIFT)); 350 } else { 351 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1; 352 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT); 353 hash = vsid ^ (vsid << 25) ^ 354 ((vpn & mask) >> (shift - VPN_SHIFT)) ; 355 } 356 return hash & 0x7fffffffffUL; 357 } 358 359 #define HPTE_LOCAL_UPDATE 0x1 360 #define HPTE_NOHPTE_UPDATE 0x2 361 362 extern int __hash_page_4K(unsigned long ea, unsigned long access, 363 unsigned long vsid, pte_t *ptep, unsigned long trap, 364 unsigned long flags, int ssize, int subpage_prot); 365 extern int __hash_page_64K(unsigned long ea, unsigned long access, 366 unsigned long vsid, pte_t *ptep, unsigned long trap, 367 unsigned long flags, int ssize); 368 struct mm_struct; 369 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap); 370 extern int hash_page_mm(struct mm_struct *mm, unsigned long ea, 371 unsigned long access, unsigned long trap, 372 unsigned long flags); 373 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap, 374 unsigned long dsisr); 375 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, 376 pte_t *ptep, unsigned long trap, unsigned long flags, 377 int ssize, unsigned int shift, unsigned int mmu_psize); 378 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 379 extern int __hash_page_thp(unsigned long ea, unsigned long access, 380 unsigned long vsid, pmd_t *pmdp, unsigned long trap, 381 unsigned long flags, int ssize, unsigned int psize); 382 #else 383 static inline int __hash_page_thp(unsigned long ea, unsigned long access, 384 unsigned long vsid, pmd_t *pmdp, 385 unsigned long trap, unsigned long flags, 386 int ssize, unsigned int psize) 387 { 388 BUG(); 389 return -1; 390 } 391 #endif 392 extern void hash_failure_debug(unsigned long ea, unsigned long access, 393 unsigned long vsid, unsigned long trap, 394 int ssize, int psize, int lpsize, 395 unsigned long pte); 396 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, 397 unsigned long pstart, unsigned long prot, 398 int psize, int ssize); 399 int htab_remove_mapping(unsigned long vstart, unsigned long vend, 400 int psize, int ssize); 401 extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages); 402 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr); 403 404 #ifdef CONFIG_PPC_PSERIES 405 void hpte_init_pseries(void); 406 #else 407 static inline void hpte_init_pseries(void) { } 408 #endif 409 410 extern void hpte_init_native(void); 411 412 extern void slb_initialize(void); 413 extern void slb_flush_and_rebolt(void); 414 415 extern void slb_vmalloc_update(void); 416 extern void slb_set_size(u16 size); 417 #endif /* __ASSEMBLY__ */ 418 419 /* 420 * VSID allocation (256MB segment) 421 * 422 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated 423 * from mmu context id and effective segment id of the address. 424 * 425 * For user processes max context id is limited to ((1ul << 19) - 5) 426 * for kernel space, we use the top 4 context ids to map address as below 427 * NOTE: each context only support 64TB now. 428 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ] 429 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ] 430 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ] 431 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ] 432 * 433 * The proto-VSIDs are then scrambled into real VSIDs with the 434 * multiplicative hash: 435 * 436 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS 437 * 438 * VSID_MULTIPLIER is prime, so in particular it is 439 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. 440 * Because the modulus is 2^n-1 we can compute it efficiently without 441 * a divide or extra multiply (see below). The scramble function gives 442 * robust scattering in the hash table (at least based on some initial 443 * results). 444 * 445 * We also consider VSID 0 special. We use VSID 0 for slb entries mapping 446 * bad address. This enables us to consolidate bad address handling in 447 * hash_page. 448 * 449 * We also need to avoid the last segment of the last context, because that 450 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0 451 * because of the modulo operation in vsid scramble. But the vmemmap 452 * (which is what uses region 0xf) will never be close to 64TB in size 453 * (it's 56 bytes per page of system memory). 454 */ 455 456 #define CONTEXT_BITS 19 457 #define ESID_BITS 18 458 #define ESID_BITS_1T 6 459 460 /* 461 * 256MB segment 462 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments 463 * available for user + kernel mapping. The top 4 contexts are used for 464 * kernel mapping. Each segment contains 2^28 bytes. Each 465 * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts 466 * (19 == 37 + 28 - 46). 467 */ 468 #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5) 469 470 /* 471 * This should be computed such that protovosid * vsid_mulitplier 472 * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus 473 */ 474 #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */ 475 #define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS) 476 #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1) 477 478 #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */ 479 #define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T) 480 #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1) 481 482 483 #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT)) 484 485 /* 486 * This macro generates asm code to compute the VSID scramble 487 * function. Used in slb_allocate() and do_stab_bolted. The function 488 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS 489 * 490 * rt = register containing the proto-VSID and into which the 491 * VSID will be stored 492 * rx = scratch register (clobbered) 493 * 494 * - rt and rx must be different registers 495 * - The answer will end up in the low VSID_BITS bits of rt. The higher 496 * bits may contain other garbage, so you may need to mask the 497 * result. 498 */ 499 #define ASM_VSID_SCRAMBLE(rt, rx, size) \ 500 lis rx,VSID_MULTIPLIER_##size@h; \ 501 ori rx,rx,VSID_MULTIPLIER_##size@l; \ 502 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \ 503 \ 504 srdi rx,rt,VSID_BITS_##size; \ 505 clrldi rt,rt,(64-VSID_BITS_##size); \ 506 add rt,rt,rx; /* add high and low bits */ \ 507 /* NOTE: explanation based on VSID_BITS_##size = 36 \ 508 * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \ 509 * 2^36-1+2^28-1. That in particular means that if r3 >= \ 510 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \ 511 * the bit clear, r3 already has the answer we want, if it \ 512 * doesn't, the answer is the low 36 bits of r3+1. So in all \ 513 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\ 514 addi rx,rt,1; \ 515 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \ 516 add rt,rt,rx 517 518 /* 4 bits per slice and we have one slice per 1TB */ 519 #define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41) 520 521 #ifndef __ASSEMBLY__ 522 523 #ifdef CONFIG_PPC_SUBPAGE_PROT 524 /* 525 * For the sub-page protection option, we extend the PGD with one of 526 * these. Basically we have a 3-level tree, with the top level being 527 * the protptrs array. To optimize speed and memory consumption when 528 * only addresses < 4GB are being protected, pointers to the first 529 * four pages of sub-page protection words are stored in the low_prot 530 * array. 531 * Each page of sub-page protection words protects 1GB (4 bytes 532 * protects 64k). For the 3-level tree, each page of pointers then 533 * protects 8TB. 534 */ 535 struct subpage_prot_table { 536 unsigned long maxaddr; /* only addresses < this are protected */ 537 unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)]; 538 unsigned int *low_prot[4]; 539 }; 540 541 #define SBP_L1_BITS (PAGE_SHIFT - 2) 542 #define SBP_L2_BITS (PAGE_SHIFT - 3) 543 #define SBP_L1_COUNT (1 << SBP_L1_BITS) 544 #define SBP_L2_COUNT (1 << SBP_L2_BITS) 545 #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS) 546 #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS) 547 548 extern void subpage_prot_free(struct mm_struct *mm); 549 extern void subpage_prot_init_new_context(struct mm_struct *mm); 550 #else 551 static inline void subpage_prot_free(struct mm_struct *mm) {} 552 static inline void subpage_prot_init_new_context(struct mm_struct *mm) { } 553 #endif /* CONFIG_PPC_SUBPAGE_PROT */ 554 555 #if 0 556 /* 557 * The code below is equivalent to this function for arguments 558 * < 2^VSID_BITS, which is all this should ever be called 559 * with. However gcc is not clever enough to compute the 560 * modulus (2^n-1) without a second multiply. 561 */ 562 #define vsid_scramble(protovsid, size) \ 563 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size)) 564 565 #else /* 1 */ 566 #define vsid_scramble(protovsid, size) \ 567 ({ \ 568 unsigned long x; \ 569 x = (protovsid) * VSID_MULTIPLIER_##size; \ 570 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \ 571 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \ 572 }) 573 #endif /* 1 */ 574 575 /* Returns the segment size indicator for a user address */ 576 static inline int user_segment_size(unsigned long addr) 577 { 578 /* Use 1T segments if possible for addresses >= 1T */ 579 if (addr >= (1UL << SID_SHIFT_1T)) 580 return mmu_highuser_ssize; 581 return MMU_SEGSIZE_256M; 582 } 583 584 static inline unsigned long get_vsid(unsigned long context, unsigned long ea, 585 int ssize) 586 { 587 /* 588 * Bad address. We return VSID 0 for that 589 */ 590 if ((ea & ~REGION_MASK) >= H_PGTABLE_RANGE) 591 return 0; 592 593 if (ssize == MMU_SEGSIZE_256M) 594 return vsid_scramble((context << ESID_BITS) 595 | (ea >> SID_SHIFT), 256M); 596 return vsid_scramble((context << ESID_BITS_1T) 597 | (ea >> SID_SHIFT_1T), 1T); 598 } 599 600 /* 601 * This is only valid for addresses >= PAGE_OFFSET 602 * 603 * For kernel space, we use the top 4 context ids to map address as below 604 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ] 605 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ] 606 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ] 607 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ] 608 */ 609 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize) 610 { 611 unsigned long context; 612 613 /* 614 * kernel take the top 4 context from the available range 615 */ 616 context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1; 617 return get_vsid(context, ea, ssize); 618 } 619 620 unsigned htab_shift_for_mem_size(unsigned long mem_size); 621 622 #endif /* __ASSEMBLY__ */ 623 624 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */ 625