1 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ 2 #define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ 3 /* 4 * PowerPC64 memory management structures 5 * 6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com> 7 * PPC64 rework. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 15 #include <asm/page.h> 16 #include <asm/bug.h> 17 #include <asm/asm-const.h> 18 19 /* 20 * This is necessary to get the definition of PGTABLE_RANGE which we 21 * need for various slices related matters. Note that this isn't the 22 * complete pgtable.h but only a portion of it. 23 */ 24 #include <asm/book3s/64/pgtable.h> 25 #include <asm/bug.h> 26 #include <asm/processor.h> 27 #include <asm/cpu_has_feature.h> 28 29 /* 30 * SLB 31 */ 32 33 #define SLB_NUM_BOLTED 3 34 #define SLB_CACHE_ENTRIES 8 35 #define SLB_MIN_SIZE 32 36 37 /* Bits in the SLB ESID word */ 38 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */ 39 40 /* Bits in the SLB VSID word */ 41 #define SLB_VSID_SHIFT 12 42 #define SLB_VSID_SHIFT_256M SLB_VSID_SHIFT 43 #define SLB_VSID_SHIFT_1T 24 44 #define SLB_VSID_SSIZE_SHIFT 62 45 #define SLB_VSID_B ASM_CONST(0xc000000000000000) 46 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000) 47 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000) 48 #define SLB_VSID_KS ASM_CONST(0x0000000000000800) 49 #define SLB_VSID_KP ASM_CONST(0x0000000000000400) 50 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ 51 #define SLB_VSID_L ASM_CONST(0x0000000000000100) 52 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */ 53 #define SLB_VSID_LP ASM_CONST(0x0000000000000030) 54 #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000) 55 #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010) 56 #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020) 57 #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030) 58 #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP) 59 60 #define SLB_VSID_KERNEL (SLB_VSID_KP) 61 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C) 62 63 #define SLBIE_C (0x08000000) 64 #define SLBIE_SSIZE_SHIFT 25 65 66 /* 67 * Hash table 68 */ 69 70 #define HPTES_PER_GROUP 8 71 72 #define HPTE_V_SSIZE_SHIFT 62 73 #define HPTE_V_AVPN_SHIFT 7 74 #define HPTE_V_COMMON_BITS ASM_CONST(0x000fffffffffffff) 75 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) 76 #define HPTE_V_AVPN_3_0 ASM_CONST(0x000fffffffffff80) 77 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) 78 #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) 79 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) 80 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008) 81 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004) 82 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002) 83 #define HPTE_V_VALID ASM_CONST(0x0000000000000001) 84 85 /* 86 * ISA 3.0 has a different HPTE format. 87 */ 88 #define HPTE_R_3_0_SSIZE_SHIFT 58 89 #define HPTE_R_3_0_SSIZE_MASK (3ull << HPTE_R_3_0_SSIZE_SHIFT) 90 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000) 91 #define HPTE_R_TS ASM_CONST(0x4000000000000000) 92 #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000) 93 #define HPTE_R_KEY_BIT0 ASM_CONST(0x2000000000000000) 94 #define HPTE_R_KEY_BIT1 ASM_CONST(0x1000000000000000) 95 #define HPTE_R_RPN_SHIFT 12 96 #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000) 97 #define HPTE_R_RPN_3_0 ASM_CONST(0x01fffffffffff000) 98 #define HPTE_R_PP ASM_CONST(0x0000000000000003) 99 #define HPTE_R_PPP ASM_CONST(0x8000000000000003) 100 #define HPTE_R_N ASM_CONST(0x0000000000000004) 101 #define HPTE_R_G ASM_CONST(0x0000000000000008) 102 #define HPTE_R_M ASM_CONST(0x0000000000000010) 103 #define HPTE_R_I ASM_CONST(0x0000000000000020) 104 #define HPTE_R_W ASM_CONST(0x0000000000000040) 105 #define HPTE_R_WIMG ASM_CONST(0x0000000000000078) 106 #define HPTE_R_C ASM_CONST(0x0000000000000080) 107 #define HPTE_R_R ASM_CONST(0x0000000000000100) 108 #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00) 109 #define HPTE_R_KEY_BIT2 ASM_CONST(0x0000000000000800) 110 #define HPTE_R_KEY_BIT3 ASM_CONST(0x0000000000000400) 111 #define HPTE_R_KEY_BIT4 ASM_CONST(0x0000000000000200) 112 #define HPTE_R_KEY (HPTE_R_KEY_LO | HPTE_R_KEY_HI) 113 114 #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000) 115 #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000) 116 117 /* Values for PP (assumes Ks=0, Kp=1) */ 118 #define PP_RWXX 0 /* Supervisor read/write, User none */ 119 #define PP_RWRX 1 /* Supervisor read/write, User read */ 120 #define PP_RWRW 2 /* Supervisor read/write, User read/write */ 121 #define PP_RXRX 3 /* Supervisor read, User read */ 122 #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */ 123 124 /* Fields for tlbiel instruction in architecture 2.06 */ 125 #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */ 126 #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */ 127 #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */ 128 #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */ 129 #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */ 130 #define TLBIEL_INVAL_SET_SHIFT 12 131 132 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */ 133 #define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */ 134 #define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */ 135 #define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */ 136 137 #ifndef __ASSEMBLY__ 138 139 struct mmu_hash_ops { 140 void (*hpte_invalidate)(unsigned long slot, 141 unsigned long vpn, 142 int bpsize, int apsize, 143 int ssize, int local); 144 long (*hpte_updatepp)(unsigned long slot, 145 unsigned long newpp, 146 unsigned long vpn, 147 int bpsize, int apsize, 148 int ssize, unsigned long flags); 149 void (*hpte_updateboltedpp)(unsigned long newpp, 150 unsigned long ea, 151 int psize, int ssize); 152 long (*hpte_insert)(unsigned long hpte_group, 153 unsigned long vpn, 154 unsigned long prpn, 155 unsigned long rflags, 156 unsigned long vflags, 157 int psize, int apsize, 158 int ssize); 159 long (*hpte_remove)(unsigned long hpte_group); 160 int (*hpte_removebolted)(unsigned long ea, 161 int psize, int ssize); 162 void (*flush_hash_range)(unsigned long number, int local); 163 void (*hugepage_invalidate)(unsigned long vsid, 164 unsigned long addr, 165 unsigned char *hpte_slot_array, 166 int psize, int ssize, int local); 167 int (*resize_hpt)(unsigned long shift); 168 /* 169 * Special for kexec. 170 * To be called in real mode with interrupts disabled. No locks are 171 * taken as such, concurrent access on pre POWER5 hardware could result 172 * in a deadlock. 173 * The linear mapping is destroyed as well. 174 */ 175 void (*hpte_clear_all)(void); 176 }; 177 extern struct mmu_hash_ops mmu_hash_ops; 178 179 struct hash_pte { 180 __be64 v; 181 __be64 r; 182 }; 183 184 extern struct hash_pte *htab_address; 185 extern unsigned long htab_size_bytes; 186 extern unsigned long htab_hash_mask; 187 188 189 static inline int shift_to_mmu_psize(unsigned int shift) 190 { 191 int psize; 192 193 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) 194 if (mmu_psize_defs[psize].shift == shift) 195 return psize; 196 return -1; 197 } 198 199 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) 200 { 201 if (mmu_psize_defs[mmu_psize].shift) 202 return mmu_psize_defs[mmu_psize].shift; 203 BUG(); 204 } 205 206 static inline unsigned long get_sllp_encoding(int psize) 207 { 208 unsigned long sllp; 209 210 sllp = ((mmu_psize_defs[psize].sllp & SLB_VSID_L) >> 6) | 211 ((mmu_psize_defs[psize].sllp & SLB_VSID_LP) >> 4); 212 return sllp; 213 } 214 215 #endif /* __ASSEMBLY__ */ 216 217 /* 218 * Segment sizes. 219 * These are the values used by hardware in the B field of 220 * SLB entries and the first dword of MMU hashtable entries. 221 * The B field is 2 bits; the values 2 and 3 are unused and reserved. 222 */ 223 #define MMU_SEGSIZE_256M 0 224 #define MMU_SEGSIZE_1T 1 225 226 /* 227 * encode page number shift. 228 * in order to fit the 78 bit va in a 64 bit variable we shift the va by 229 * 12 bits. This enable us to address upto 76 bit va. 230 * For hpt hash from a va we can ignore the page size bits of va and for 231 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure 232 * we work in all cases including 4k page size. 233 */ 234 #define VPN_SHIFT 12 235 236 /* 237 * HPTE Large Page (LP) details 238 */ 239 #define LP_SHIFT 12 240 #define LP_BITS 8 241 #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) 242 243 #ifndef __ASSEMBLY__ 244 245 static inline int slb_vsid_shift(int ssize) 246 { 247 if (ssize == MMU_SEGSIZE_256M) 248 return SLB_VSID_SHIFT; 249 return SLB_VSID_SHIFT_1T; 250 } 251 252 static inline int segment_shift(int ssize) 253 { 254 if (ssize == MMU_SEGSIZE_256M) 255 return SID_SHIFT; 256 return SID_SHIFT_1T; 257 } 258 259 /* 260 * This array is indexed by the LP field of the HPTE second dword. 261 * Since this field may contain some RPN bits, some entries are 262 * replicated so that we get the same value irrespective of RPN. 263 * The top 4 bits are the page size index (MMU_PAGE_*) for the 264 * actual page size, the bottom 4 bits are the base page size. 265 */ 266 extern u8 hpte_page_sizes[1 << LP_BITS]; 267 268 static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l, 269 bool is_base_size) 270 { 271 unsigned int i, lp; 272 273 if (!(h & HPTE_V_LARGE)) 274 return 1ul << 12; 275 276 /* Look at the 8 bit LP value */ 277 lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1); 278 i = hpte_page_sizes[lp]; 279 if (!i) 280 return 0; 281 if (!is_base_size) 282 i >>= 4; 283 return 1ul << mmu_psize_defs[i & 0xf].shift; 284 } 285 286 static inline unsigned long hpte_page_size(unsigned long h, unsigned long l) 287 { 288 return __hpte_page_size(h, l, 0); 289 } 290 291 static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l) 292 { 293 return __hpte_page_size(h, l, 1); 294 } 295 296 /* 297 * The current system page and segment sizes 298 */ 299 extern int mmu_kernel_ssize; 300 extern int mmu_highuser_ssize; 301 extern u16 mmu_slb_size; 302 extern unsigned long tce_alloc_start, tce_alloc_end; 303 304 /* 305 * If the processor supports 64k normal pages but not 64k cache 306 * inhibited pages, we have to be prepared to switch processes 307 * to use 4k pages when they create cache-inhibited mappings. 308 * If this is the case, mmu_ci_restrictions will be set to 1. 309 */ 310 extern int mmu_ci_restrictions; 311 312 /* 313 * This computes the AVPN and B fields of the first dword of a HPTE, 314 * for use when we want to match an existing PTE. The bottom 7 bits 315 * of the returned value are zero. 316 */ 317 static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize, 318 int ssize) 319 { 320 unsigned long v; 321 /* 322 * The AVA field omits the low-order 23 bits of the 78 bits VA. 323 * These bits are not needed in the PTE, because the 324 * low-order b of these bits are part of the byte offset 325 * into the virtual page and, if b < 23, the high-order 326 * 23-b of these bits are always used in selecting the 327 * PTEGs to be searched 328 */ 329 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm); 330 v <<= HPTE_V_AVPN_SHIFT; 331 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT; 332 return v; 333 } 334 335 /* 336 * ISA v3.0 defines a new HPTE format, which differs from the old 337 * format in having smaller AVPN and ARPN fields, and the B field 338 * in the second dword instead of the first. 339 */ 340 static inline unsigned long hpte_old_to_new_v(unsigned long v) 341 { 342 /* trim AVPN, drop B */ 343 return v & HPTE_V_COMMON_BITS; 344 } 345 346 static inline unsigned long hpte_old_to_new_r(unsigned long v, unsigned long r) 347 { 348 /* move B field from 1st to 2nd dword, trim ARPN */ 349 return (r & ~HPTE_R_3_0_SSIZE_MASK) | 350 (((v) >> HPTE_V_SSIZE_SHIFT) << HPTE_R_3_0_SSIZE_SHIFT); 351 } 352 353 static inline unsigned long hpte_new_to_old_v(unsigned long v, unsigned long r) 354 { 355 /* insert B field */ 356 return (v & HPTE_V_COMMON_BITS) | 357 ((r & HPTE_R_3_0_SSIZE_MASK) << 358 (HPTE_V_SSIZE_SHIFT - HPTE_R_3_0_SSIZE_SHIFT)); 359 } 360 361 static inline unsigned long hpte_new_to_old_r(unsigned long r) 362 { 363 /* clear out B field */ 364 return r & ~HPTE_R_3_0_SSIZE_MASK; 365 } 366 367 static inline unsigned long hpte_get_old_v(struct hash_pte *hptep) 368 { 369 unsigned long hpte_v; 370 371 hpte_v = be64_to_cpu(hptep->v); 372 if (cpu_has_feature(CPU_FTR_ARCH_300)) 373 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r)); 374 return hpte_v; 375 } 376 377 /* 378 * This function sets the AVPN and L fields of the HPTE appropriately 379 * using the base page size and actual page size. 380 */ 381 static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize, 382 int actual_psize, int ssize) 383 { 384 unsigned long v; 385 v = hpte_encode_avpn(vpn, base_psize, ssize); 386 if (actual_psize != MMU_PAGE_4K) 387 v |= HPTE_V_LARGE; 388 return v; 389 } 390 391 /* 392 * This function sets the ARPN, and LP fields of the HPTE appropriately 393 * for the page size. We assume the pa is already "clean" that is properly 394 * aligned for the requested page size 395 */ 396 static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize, 397 int actual_psize) 398 { 399 /* A 4K page needs no special encoding */ 400 if (actual_psize == MMU_PAGE_4K) 401 return pa & HPTE_R_RPN; 402 else { 403 unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize]; 404 unsigned int shift = mmu_psize_defs[actual_psize].shift; 405 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT); 406 } 407 } 408 409 /* 410 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size. 411 */ 412 static inline unsigned long hpt_vpn(unsigned long ea, 413 unsigned long vsid, int ssize) 414 { 415 unsigned long mask; 416 int s_shift = segment_shift(ssize); 417 418 mask = (1ul << (s_shift - VPN_SHIFT)) - 1; 419 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask); 420 } 421 422 /* 423 * This hashes a virtual address 424 */ 425 static inline unsigned long hpt_hash(unsigned long vpn, 426 unsigned int shift, int ssize) 427 { 428 unsigned long mask; 429 unsigned long hash, vsid; 430 431 /* VPN_SHIFT can be atmost 12 */ 432 if (ssize == MMU_SEGSIZE_256M) { 433 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1; 434 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^ 435 ((vpn & mask) >> (shift - VPN_SHIFT)); 436 } else { 437 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1; 438 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT); 439 hash = vsid ^ (vsid << 25) ^ 440 ((vpn & mask) >> (shift - VPN_SHIFT)) ; 441 } 442 return hash & 0x7fffffffffUL; 443 } 444 445 #define HPTE_LOCAL_UPDATE 0x1 446 #define HPTE_NOHPTE_UPDATE 0x2 447 448 extern int __hash_page_4K(unsigned long ea, unsigned long access, 449 unsigned long vsid, pte_t *ptep, unsigned long trap, 450 unsigned long flags, int ssize, int subpage_prot); 451 extern int __hash_page_64K(unsigned long ea, unsigned long access, 452 unsigned long vsid, pte_t *ptep, unsigned long trap, 453 unsigned long flags, int ssize); 454 struct mm_struct; 455 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap); 456 extern int hash_page_mm(struct mm_struct *mm, unsigned long ea, 457 unsigned long access, unsigned long trap, 458 unsigned long flags); 459 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap, 460 unsigned long dsisr); 461 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, 462 pte_t *ptep, unsigned long trap, unsigned long flags, 463 int ssize, unsigned int shift, unsigned int mmu_psize); 464 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 465 extern int __hash_page_thp(unsigned long ea, unsigned long access, 466 unsigned long vsid, pmd_t *pmdp, unsigned long trap, 467 unsigned long flags, int ssize, unsigned int psize); 468 #else 469 static inline int __hash_page_thp(unsigned long ea, unsigned long access, 470 unsigned long vsid, pmd_t *pmdp, 471 unsigned long trap, unsigned long flags, 472 int ssize, unsigned int psize) 473 { 474 BUG(); 475 return -1; 476 } 477 #endif 478 extern void hash_failure_debug(unsigned long ea, unsigned long access, 479 unsigned long vsid, unsigned long trap, 480 int ssize, int psize, int lpsize, 481 unsigned long pte); 482 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, 483 unsigned long pstart, unsigned long prot, 484 int psize, int ssize); 485 int htab_remove_mapping(unsigned long vstart, unsigned long vend, 486 int psize, int ssize); 487 extern void pseries_add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages); 488 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr); 489 490 #ifdef CONFIG_PPC_PSERIES 491 void hpte_init_pseries(void); 492 #else 493 static inline void hpte_init_pseries(void) { } 494 #endif 495 496 extern void hpte_init_native(void); 497 498 extern void slb_initialize(void); 499 extern void slb_flush_and_rebolt(void); 500 void slb_flush_all_realmode(void); 501 void __slb_restore_bolted_realmode(void); 502 void slb_restore_bolted_realmode(void); 503 504 extern void slb_vmalloc_update(void); 505 extern void slb_set_size(u16 size); 506 #endif /* __ASSEMBLY__ */ 507 508 /* 509 * VSID allocation (256MB segment) 510 * 511 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated 512 * from mmu context id and effective segment id of the address. 513 * 514 * For user processes max context id is limited to MAX_USER_CONTEXT. 515 516 * For kernel space, we use context ids 1-4 to map addresses as below: 517 * NOTE: each context only support 64TB now. 518 * 0x00001 - [ 0xc000000000000000 - 0xc0003fffffffffff ] 519 * 0x00002 - [ 0xd000000000000000 - 0xd0003fffffffffff ] 520 * 0x00003 - [ 0xe000000000000000 - 0xe0003fffffffffff ] 521 * 0x00004 - [ 0xf000000000000000 - 0xf0003fffffffffff ] 522 * 523 * The proto-VSIDs are then scrambled into real VSIDs with the 524 * multiplicative hash: 525 * 526 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS 527 * 528 * VSID_MULTIPLIER is prime, so in particular it is 529 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. 530 * Because the modulus is 2^n-1 we can compute it efficiently without 531 * a divide or extra multiply (see below). The scramble function gives 532 * robust scattering in the hash table (at least based on some initial 533 * results). 534 * 535 * We use VSID 0 to indicate an invalid VSID. The means we can't use context id 536 * 0, because a context id of 0 and an EA of 0 gives a proto-VSID of 0, which 537 * will produce a VSID of 0. 538 * 539 * We also need to avoid the last segment of the last context, because that 540 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0 541 * because of the modulo operation in vsid scramble. 542 */ 543 544 /* 545 * Max Va bits we support as of now is 68 bits. We want 19 bit 546 * context ID. 547 * Restrictions: 548 * GPU has restrictions of not able to access beyond 128TB 549 * (47 bit effective address). We also cannot do more than 20bit PID. 550 * For p4 and p5 which can only do 65 bit VA, we restrict our CONTEXT_BITS 551 * to 16 bits (ie, we can only have 2^16 pids at the same time). 552 */ 553 #define VA_BITS 68 554 #define CONTEXT_BITS 19 555 #define ESID_BITS (VA_BITS - (SID_SHIFT + CONTEXT_BITS)) 556 #define ESID_BITS_1T (VA_BITS - (SID_SHIFT_1T + CONTEXT_BITS)) 557 558 #define ESID_BITS_MASK ((1 << ESID_BITS) - 1) 559 #define ESID_BITS_1T_MASK ((1 << ESID_BITS_1T) - 1) 560 561 /* 562 * 256MB segment 563 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments 564 * available for user + kernel mapping. VSID 0 is reserved as invalid, contexts 565 * 1-4 are used for kernel mapping. Each segment contains 2^28 bytes. Each 566 * context maps 2^49 bytes (512TB). 567 * 568 * We also need to avoid the last segment of the last context, because that 569 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0 570 * because of the modulo operation in vsid scramble. 571 */ 572 #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 2) 573 #define MIN_USER_CONTEXT (5) 574 575 /* Would be nice to use KERNEL_REGION_ID here */ 576 #define KERNEL_REGION_CONTEXT_OFFSET (0xc - 1) 577 578 /* 579 * For platforms that support on 65bit VA we limit the context bits 580 */ 581 #define MAX_USER_CONTEXT_65BIT_VA ((ASM_CONST(1) << (65 - (SID_SHIFT + ESID_BITS))) - 2) 582 583 /* 584 * This should be computed such that protovosid * vsid_mulitplier 585 * doesn't overflow 64 bits. The vsid_mutliplier should also be 586 * co-prime to vsid_modulus. We also need to make sure that number 587 * of bits in multiplied result (dividend) is less than twice the number of 588 * protovsid bits for our modulus optmization to work. 589 * 590 * The below table shows the current values used. 591 * |-------+------------+----------------------+------------+-------------------| 592 * | | Prime Bits | proto VSID_BITS_65VA | Total Bits | 2* prot VSID_BITS | 593 * |-------+------------+----------------------+------------+-------------------| 594 * | 1T | 24 | 25 | 49 | 50 | 595 * |-------+------------+----------------------+------------+-------------------| 596 * | 256MB | 24 | 37 | 61 | 74 | 597 * |-------+------------+----------------------+------------+-------------------| 598 * 599 * |-------+------------+----------------------+------------+--------------------| 600 * | | Prime Bits | proto VSID_BITS_68VA | Total Bits | 2* proto VSID_BITS | 601 * |-------+------------+----------------------+------------+--------------------| 602 * | 1T | 24 | 28 | 52 | 56 | 603 * |-------+------------+----------------------+------------+--------------------| 604 * | 256MB | 24 | 40 | 64 | 80 | 605 * |-------+------------+----------------------+------------+--------------------| 606 * 607 */ 608 #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */ 609 #define VSID_BITS_256M (VA_BITS - SID_SHIFT) 610 #define VSID_BITS_65_256M (65 - SID_SHIFT) 611 /* 612 * Modular multiplicative inverse of VSID_MULTIPLIER under modulo VSID_MODULUS 613 */ 614 #define VSID_MULINV_256M ASM_CONST(665548017062) 615 616 #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */ 617 #define VSID_BITS_1T (VA_BITS - SID_SHIFT_1T) 618 #define VSID_BITS_65_1T (65 - SID_SHIFT_1T) 619 #define VSID_MULINV_1T ASM_CONST(209034062) 620 621 /* 1TB VSID reserved for VRMA */ 622 #define VRMA_VSID 0x1ffffffUL 623 #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT)) 624 625 /* 4 bits per slice and we have one slice per 1TB */ 626 #define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41) 627 #define TASK_SLICE_ARRAY_SZ(x) ((x)->context.slb_addr_limit >> 41) 628 629 #ifndef __ASSEMBLY__ 630 631 #ifdef CONFIG_PPC_SUBPAGE_PROT 632 /* 633 * For the sub-page protection option, we extend the PGD with one of 634 * these. Basically we have a 3-level tree, with the top level being 635 * the protptrs array. To optimize speed and memory consumption when 636 * only addresses < 4GB are being protected, pointers to the first 637 * four pages of sub-page protection words are stored in the low_prot 638 * array. 639 * Each page of sub-page protection words protects 1GB (4 bytes 640 * protects 64k). For the 3-level tree, each page of pointers then 641 * protects 8TB. 642 */ 643 struct subpage_prot_table { 644 unsigned long maxaddr; /* only addresses < this are protected */ 645 unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)]; 646 unsigned int *low_prot[4]; 647 }; 648 649 #define SBP_L1_BITS (PAGE_SHIFT - 2) 650 #define SBP_L2_BITS (PAGE_SHIFT - 3) 651 #define SBP_L1_COUNT (1 << SBP_L1_BITS) 652 #define SBP_L2_COUNT (1 << SBP_L2_BITS) 653 #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS) 654 #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS) 655 656 extern void subpage_prot_free(struct mm_struct *mm); 657 extern void subpage_prot_init_new_context(struct mm_struct *mm); 658 #else 659 static inline void subpage_prot_free(struct mm_struct *mm) {} 660 static inline void subpage_prot_init_new_context(struct mm_struct *mm) { } 661 #endif /* CONFIG_PPC_SUBPAGE_PROT */ 662 663 #if 0 664 /* 665 * The code below is equivalent to this function for arguments 666 * < 2^VSID_BITS, which is all this should ever be called 667 * with. However gcc is not clever enough to compute the 668 * modulus (2^n-1) without a second multiply. 669 */ 670 #define vsid_scramble(protovsid, size) \ 671 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size)) 672 673 /* simplified form avoiding mod operation */ 674 #define vsid_scramble(protovsid, size) \ 675 ({ \ 676 unsigned long x; \ 677 x = (protovsid) * VSID_MULTIPLIER_##size; \ 678 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \ 679 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \ 680 }) 681 682 #else /* 1 */ 683 static inline unsigned long vsid_scramble(unsigned long protovsid, 684 unsigned long vsid_multiplier, int vsid_bits) 685 { 686 unsigned long vsid; 687 unsigned long vsid_modulus = ((1UL << vsid_bits) - 1); 688 /* 689 * We have same multipler for both 256 and 1T segements now 690 */ 691 vsid = protovsid * vsid_multiplier; 692 vsid = (vsid >> vsid_bits) + (vsid & vsid_modulus); 693 return (vsid + ((vsid + 1) >> vsid_bits)) & vsid_modulus; 694 } 695 696 #endif /* 1 */ 697 698 /* Returns the segment size indicator for a user address */ 699 static inline int user_segment_size(unsigned long addr) 700 { 701 /* Use 1T segments if possible for addresses >= 1T */ 702 if (addr >= (1UL << SID_SHIFT_1T)) 703 return mmu_highuser_ssize; 704 return MMU_SEGSIZE_256M; 705 } 706 707 static inline unsigned long get_vsid(unsigned long context, unsigned long ea, 708 int ssize) 709 { 710 unsigned long va_bits = VA_BITS; 711 unsigned long vsid_bits; 712 unsigned long protovsid; 713 714 /* 715 * Bad address. We return VSID 0 for that 716 */ 717 if ((ea & ~REGION_MASK) >= H_PGTABLE_RANGE) 718 return 0; 719 720 if (!mmu_has_feature(MMU_FTR_68_BIT_VA)) 721 va_bits = 65; 722 723 if (ssize == MMU_SEGSIZE_256M) { 724 vsid_bits = va_bits - SID_SHIFT; 725 protovsid = (context << ESID_BITS) | 726 ((ea >> SID_SHIFT) & ESID_BITS_MASK); 727 return vsid_scramble(protovsid, VSID_MULTIPLIER_256M, vsid_bits); 728 } 729 /* 1T segment */ 730 vsid_bits = va_bits - SID_SHIFT_1T; 731 protovsid = (context << ESID_BITS_1T) | 732 ((ea >> SID_SHIFT_1T) & ESID_BITS_1T_MASK); 733 return vsid_scramble(protovsid, VSID_MULTIPLIER_1T, vsid_bits); 734 } 735 736 /* 737 * This is only valid for addresses >= PAGE_OFFSET 738 */ 739 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize) 740 { 741 unsigned long context; 742 743 if (!is_kernel_addr(ea)) 744 return 0; 745 746 /* 747 * For kernel space, we use context ids 1-4 to map the address space as 748 * below: 749 * 750 * 0x00001 - [ 0xc000000000000000 - 0xc0003fffffffffff ] 751 * 0x00002 - [ 0xd000000000000000 - 0xd0003fffffffffff ] 752 * 0x00003 - [ 0xe000000000000000 - 0xe0003fffffffffff ] 753 * 0x00004 - [ 0xf000000000000000 - 0xf0003fffffffffff ] 754 * 755 * So we can compute the context from the region (top nibble) by 756 * subtracting 11, or 0xc - 1. 757 */ 758 context = (ea >> 60) - KERNEL_REGION_CONTEXT_OFFSET; 759 760 return get_vsid(context, ea, ssize); 761 } 762 763 unsigned htab_shift_for_mem_size(unsigned long mem_size); 764 765 #endif /* __ASSEMBLY__ */ 766 767 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */ 768