1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_H 3 #define _ASM_POWERPC_BOOK3S_64_HASH_H 4 #ifdef __KERNEL__ 5 6 /* 7 * Common bits between 4K and 64K pages in a linux-style PTE. 8 * Additional bits may be defined in pgtable-hash64-*.h 9 * 10 */ 11 #define H_PTE_NONE_MASK _PAGE_HPTEFLAGS 12 13 #ifdef CONFIG_PPC_64K_PAGES 14 #include <asm/book3s/64/hash-64k.h> 15 #else 16 #include <asm/book3s/64/hash-4k.h> 17 #endif 18 19 /* 20 * Size of EA range mapped by our pagetables. 21 */ 22 #define H_PGTABLE_EADDR_SIZE (H_PTE_INDEX_SIZE + H_PMD_INDEX_SIZE + \ 23 H_PUD_INDEX_SIZE + H_PGD_INDEX_SIZE + PAGE_SHIFT) 24 #define H_PGTABLE_RANGE (ASM_CONST(1) << H_PGTABLE_EADDR_SIZE) 25 26 #if (defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)) && \ 27 defined(CONFIG_PPC_64K_PAGES) 28 /* 29 * only with hash 64k we need to use the second half of pmd page table 30 * to store pointer to deposited pgtable_t 31 */ 32 #define H_PMD_CACHE_INDEX (H_PMD_INDEX_SIZE + 1) 33 #else 34 #define H_PMD_CACHE_INDEX H_PMD_INDEX_SIZE 35 #endif 36 /* 37 * We store the slot details in the second half of page table. 38 * Increase the pud level table so that hugetlb ptes can be stored 39 * at pud level. 40 */ 41 #if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_64K_PAGES) 42 #define H_PUD_CACHE_INDEX (H_PUD_INDEX_SIZE + 1) 43 #else 44 #define H_PUD_CACHE_INDEX (H_PUD_INDEX_SIZE) 45 #endif 46 /* 47 * Define the address range of the kernel non-linear virtual area 48 */ 49 #define H_KERN_VIRT_START ASM_CONST(0xD000000000000000) 50 #define H_KERN_VIRT_SIZE ASM_CONST(0x0000400000000000) /* 64T */ 51 52 /* 53 * The vmalloc space starts at the beginning of that region, and 54 * occupies half of it on hash CPUs and a quarter of it on Book3E 55 * (we keep a quarter for the virtual memmap) 56 */ 57 #define H_VMALLOC_START H_KERN_VIRT_START 58 #define H_VMALLOC_SIZE ASM_CONST(0x380000000000) /* 56T */ 59 #define H_VMALLOC_END (H_VMALLOC_START + H_VMALLOC_SIZE) 60 61 #define H_KERN_IO_START H_VMALLOC_END 62 63 /* 64 * Region IDs 65 */ 66 #define REGION_SHIFT 60UL 67 #define REGION_MASK (0xfUL << REGION_SHIFT) 68 #define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT) 69 70 #define VMALLOC_REGION_ID (REGION_ID(H_VMALLOC_START)) 71 #define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET)) 72 #define VMEMMAP_REGION_ID (0xfUL) /* Server only */ 73 #define USER_REGION_ID (0UL) 74 75 /* 76 * Defines the address of the vmemap area, in its own region on 77 * hash table CPUs. 78 */ 79 #define H_VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT) 80 81 #ifdef CONFIG_PPC_MM_SLICES 82 #define HAVE_ARCH_UNMAPPED_AREA 83 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 84 #endif /* CONFIG_PPC_MM_SLICES */ 85 86 87 /* PTEIDX nibble */ 88 #define _PTEIDX_SECONDARY 0x8 89 #define _PTEIDX_GROUP_IX 0x7 90 91 #define H_PMD_BAD_BITS (PTE_TABLE_SIZE-1) 92 #define H_PUD_BAD_BITS (PMD_TABLE_SIZE-1) 93 94 #ifndef __ASSEMBLY__ 95 #define hash__pmd_bad(pmd) (pmd_val(pmd) & H_PMD_BAD_BITS) 96 #define hash__pud_bad(pud) (pud_val(pud) & H_PUD_BAD_BITS) 97 static inline int hash__pgd_bad(pgd_t pgd) 98 { 99 return (pgd_val(pgd) == 0); 100 } 101 #ifdef CONFIG_STRICT_KERNEL_RWX 102 extern void hash__mark_rodata_ro(void); 103 extern void hash__mark_initmem_nx(void); 104 #endif 105 106 extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr, 107 pte_t *ptep, unsigned long pte, int huge); 108 extern unsigned long htab_convert_pte_flags(unsigned long pteflags); 109 /* Atomic PTE updates */ 110 static inline unsigned long hash__pte_update(struct mm_struct *mm, 111 unsigned long addr, 112 pte_t *ptep, unsigned long clr, 113 unsigned long set, 114 int huge) 115 { 116 __be64 old_be, tmp_be; 117 unsigned long old; 118 119 __asm__ __volatile__( 120 "1: ldarx %0,0,%3 # pte_update\n\ 121 and. %1,%0,%6\n\ 122 bne- 1b \n\ 123 andc %1,%0,%4 \n\ 124 or %1,%1,%7\n\ 125 stdcx. %1,0,%3 \n\ 126 bne- 1b" 127 : "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep) 128 : "r" (ptep), "r" (cpu_to_be64(clr)), "m" (*ptep), 129 "r" (cpu_to_be64(H_PAGE_BUSY)), "r" (cpu_to_be64(set)) 130 : "cc" ); 131 /* huge pages use the old page table lock */ 132 if (!huge) 133 assert_pte_locked(mm, addr); 134 135 old = be64_to_cpu(old_be); 136 if (old & H_PAGE_HASHPTE) 137 hpte_need_flush(mm, addr, ptep, old, huge); 138 139 return old; 140 } 141 142 /* Set the dirty and/or accessed bits atomically in a linux PTE, this 143 * function doesn't need to flush the hash entry 144 */ 145 static inline void hash__ptep_set_access_flags(pte_t *ptep, pte_t entry) 146 { 147 __be64 old, tmp, val, mask; 148 149 mask = cpu_to_be64(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_READ | _PAGE_WRITE | 150 _PAGE_EXEC | _PAGE_SOFT_DIRTY); 151 152 val = pte_raw(entry) & mask; 153 154 __asm__ __volatile__( 155 "1: ldarx %0,0,%4\n\ 156 and. %1,%0,%6\n\ 157 bne- 1b \n\ 158 or %0,%3,%0\n\ 159 stdcx. %0,0,%4\n\ 160 bne- 1b" 161 :"=&r" (old), "=&r" (tmp), "=m" (*ptep) 162 :"r" (val), "r" (ptep), "m" (*ptep), "r" (cpu_to_be64(H_PAGE_BUSY)) 163 :"cc"); 164 } 165 166 static inline int hash__pte_same(pte_t pte_a, pte_t pte_b) 167 { 168 return (((pte_raw(pte_a) ^ pte_raw(pte_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0); 169 } 170 171 static inline int hash__pte_none(pte_t pte) 172 { 173 return (pte_val(pte) & ~H_PTE_NONE_MASK) == 0; 174 } 175 176 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift, 177 int ssize, real_pte_t rpte, unsigned int subpg_index); 178 179 /* This low level function performs the actual PTE insertion 180 * Setting the PTE depends on the MMU type and other factors. It's 181 * an horrible mess that I'm not going to try to clean up now but 182 * I'm keeping it in one place rather than spread around 183 */ 184 static inline void hash__set_pte_at(struct mm_struct *mm, unsigned long addr, 185 pte_t *ptep, pte_t pte, int percpu) 186 { 187 /* 188 * Anything else just stores the PTE normally. That covers all 64-bit 189 * cases, and 32-bit non-hash with 32-bit PTEs. 190 */ 191 *ptep = pte; 192 } 193 194 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 195 extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr, 196 pmd_t *pmdp, unsigned long old_pmd); 197 #else 198 static inline void hpte_do_hugepage_flush(struct mm_struct *mm, 199 unsigned long addr, pmd_t *pmdp, 200 unsigned long old_pmd) 201 { 202 WARN(1, "%s called with THP disabled\n", __func__); 203 } 204 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 205 206 207 extern int hash__map_kernel_page(unsigned long ea, unsigned long pa, 208 unsigned long flags); 209 extern int __meminit hash__vmemmap_create_mapping(unsigned long start, 210 unsigned long page_size, 211 unsigned long phys); 212 extern void hash__vmemmap_remove_mapping(unsigned long start, 213 unsigned long page_size); 214 215 int hash__create_section_mapping(unsigned long start, unsigned long end, int nid); 216 int hash__remove_section_mapping(unsigned long start, unsigned long end); 217 218 #endif /* !__ASSEMBLY__ */ 219 #endif /* __KERNEL__ */ 220 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */ 221