1 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_H 2 #define _ASM_POWERPC_BOOK3S_64_HASH_H 3 #ifdef __KERNEL__ 4 5 /* 6 * Common bits between 4K and 64K pages in a linux-style PTE. 7 * These match the bits in the (hardware-defined) PowerPC PTE as closely 8 * as possible. Additional bits may be defined in pgtable-hash64-*.h 9 * 10 * Note: We only support user read/write permissions. Supervisor always 11 * have full read/write to pages above PAGE_OFFSET (pages below that 12 * always use the user access permissions). 13 * 14 * We could create separate kernel read-only if we used the 3 PP bits 15 * combinations that newer processors provide but we currently don't. 16 */ 17 #define _PAGE_PTE 0x00001 18 #define _PAGE_PRESENT 0x00002 /* software: pte contains a translation */ 19 #define _PAGE_BIT_SWAP_TYPE 2 20 #define _PAGE_USER 0x00004 /* matches one of the PP bits */ 21 #define _PAGE_EXEC 0x00008 /* No execute on POWER4 and newer (we invert) */ 22 #define _PAGE_GUARDED 0x00010 23 /* We can derive Memory coherence from _PAGE_NO_CACHE */ 24 #define _PAGE_COHERENT 0x0 25 #define _PAGE_NO_CACHE 0x00020 /* I: cache inhibit */ 26 #define _PAGE_WRITETHRU 0x00040 /* W: cache write-through */ 27 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 28 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 29 #define _PAGE_RW 0x00200 /* software: user write access allowed */ 30 #define _PAGE_HASHPTE 0x00400 /* software: pte has an associated HPTE */ 31 #define _PAGE_BUSY 0x00800 /* software: PTE & hash are busy */ 32 #define _PAGE_F_GIX 0x07000 /* full page: hidx bits */ 33 #define _PAGE_F_GIX_SHIFT 12 34 #define _PAGE_F_SECOND 0x08000 /* Whether to use secondary hash or not */ 35 #define _PAGE_SPECIAL 0x10000 /* software: special page */ 36 37 #ifdef CONFIG_MEM_SOFT_DIRTY 38 #define _PAGE_SOFT_DIRTY 0x20000 /* software: software dirty tracking */ 39 #else 40 #define _PAGE_SOFT_DIRTY 0x00000 41 #endif 42 43 /* 44 * We need to differentiate between explicit huge page and THP huge 45 * page, since THP huge page also need to track real subpage details 46 */ 47 #define _PAGE_THP_HUGE _PAGE_4K_PFN 48 49 /* 50 * set of bits not changed in pmd_modify. 51 */ 52 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 53 _PAGE_ACCESSED | _PAGE_THP_HUGE) 54 55 #ifdef CONFIG_PPC_64K_PAGES 56 #include <asm/book3s/64/hash-64k.h> 57 #else 58 #include <asm/book3s/64/hash-4k.h> 59 #endif 60 61 /* 62 * Size of EA range mapped by our pagetables. 63 */ 64 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ 65 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT) 66 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE) 67 68 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 69 #define PMD_CACHE_INDEX (PMD_INDEX_SIZE + 1) 70 #else 71 #define PMD_CACHE_INDEX PMD_INDEX_SIZE 72 #endif 73 /* 74 * Define the address range of the kernel non-linear virtual area 75 */ 76 #define KERN_VIRT_START ASM_CONST(0xD000000000000000) 77 #define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000) 78 79 /* 80 * The vmalloc space starts at the beginning of that region, and 81 * occupies half of it on hash CPUs and a quarter of it on Book3E 82 * (we keep a quarter for the virtual memmap) 83 */ 84 #define VMALLOC_START KERN_VIRT_START 85 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 86 #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE) 87 88 /* 89 * Region IDs 90 */ 91 #define REGION_SHIFT 60UL 92 #define REGION_MASK (0xfUL << REGION_SHIFT) 93 #define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT) 94 95 #define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START)) 96 #define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET)) 97 #define VMEMMAP_REGION_ID (0xfUL) /* Server only */ 98 #define USER_REGION_ID (0UL) 99 100 /* 101 * Defines the address of the vmemap area, in its own region on 102 * hash table CPUs. 103 */ 104 #define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT) 105 106 #ifdef CONFIG_PPC_MM_SLICES 107 #define HAVE_ARCH_UNMAPPED_AREA 108 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 109 #endif /* CONFIG_PPC_MM_SLICES */ 110 111 /* No separate kernel read-only */ 112 #define _PAGE_KERNEL_RW (_PAGE_RW | _PAGE_DIRTY) /* user access blocked by key */ 113 #define _PAGE_KERNEL_RO _PAGE_KERNEL_RW 114 #define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 115 116 /* Strong Access Ordering */ 117 #define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT) 118 119 /* No page size encoding in the linux PTE */ 120 #define _PAGE_PSIZE 0 121 122 /* PTEIDX nibble */ 123 #define _PTEIDX_SECONDARY 0x8 124 #define _PTEIDX_GROUP_IX 0x7 125 126 /* Hash table based platforms need atomic updates of the linux PTE */ 127 #define PTE_ATOMIC_UPDATES 1 128 #define _PTE_NONE_MASK _PAGE_HPTEFLAGS 129 /* 130 * The mask convered by the RPN must be a ULL on 32-bit platforms with 131 * 64-bit PTEs 132 */ 133 #define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1)) 134 /* 135 * _PAGE_CHG_MASK masks of bits that are to be preserved across 136 * pgprot changes 137 */ 138 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 139 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 140 _PAGE_SOFT_DIRTY) 141 /* 142 * Mask of bits returned by pte_pgprot() 143 */ 144 #define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \ 145 _PAGE_WRITETHRU | _PAGE_4K_PFN | \ 146 _PAGE_USER | _PAGE_ACCESSED | \ 147 _PAGE_RW | _PAGE_DIRTY | _PAGE_EXEC | \ 148 _PAGE_SOFT_DIRTY) 149 /* 150 * We define 2 sets of base prot bits, one for basic pages (ie, 151 * cacheable kernel and user pages) and one for non cacheable 152 * pages. We always set _PAGE_COHERENT when SMP is enabled or 153 * the processor might need it for DMA coherency. 154 */ 155 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 156 #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 157 158 /* Permission masks used to generate the __P and __S table, 159 * 160 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 161 * 162 * Write permissions imply read permissions for now (we could make write-only 163 * pages on BookE but we don't bother for now). Execute permission control is 164 * possible on platforms that define _PAGE_EXEC 165 * 166 * Note due to the way vm flags are laid out, the bits are XWR 167 */ 168 #define PAGE_NONE __pgprot(_PAGE_BASE) 169 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 170 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | \ 171 _PAGE_EXEC) 172 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER ) 173 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 174 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER ) 175 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 176 177 #define __P000 PAGE_NONE 178 #define __P001 PAGE_READONLY 179 #define __P010 PAGE_COPY 180 #define __P011 PAGE_COPY 181 #define __P100 PAGE_READONLY_X 182 #define __P101 PAGE_READONLY_X 183 #define __P110 PAGE_COPY_X 184 #define __P111 PAGE_COPY_X 185 186 #define __S000 PAGE_NONE 187 #define __S001 PAGE_READONLY 188 #define __S010 PAGE_SHARED 189 #define __S011 PAGE_SHARED 190 #define __S100 PAGE_READONLY_X 191 #define __S101 PAGE_READONLY_X 192 #define __S110 PAGE_SHARED_X 193 #define __S111 PAGE_SHARED_X 194 195 /* Permission masks used for kernel mappings */ 196 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 197 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 198 _PAGE_NO_CACHE) 199 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 200 _PAGE_NO_CACHE | _PAGE_GUARDED) 201 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 202 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 203 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 204 205 /* Protection used for kernel text. We want the debuggers to be able to 206 * set breakpoints anywhere, so don't write protect the kernel text 207 * on platforms where such control is possible. 208 */ 209 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\ 210 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 211 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 212 #else 213 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 214 #endif 215 216 /* Make modules code happy. We don't set RO yet */ 217 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 218 #define PAGE_AGP (PAGE_KERNEL_NC) 219 220 #define PMD_BAD_BITS (PTE_TABLE_SIZE-1) 221 #define PUD_BAD_BITS (PMD_TABLE_SIZE-1) 222 223 #ifndef __ASSEMBLY__ 224 #define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \ 225 || (pmd_val(pmd) & PMD_BAD_BITS)) 226 #define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS) 227 228 #define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \ 229 || (pud_val(pud) & PUD_BAD_BITS)) 230 #define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS) 231 232 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 233 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 234 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 235 236 extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr, 237 pte_t *ptep, unsigned long pte, int huge); 238 extern unsigned long htab_convert_pte_flags(unsigned long pteflags); 239 /* Atomic PTE updates */ 240 static inline unsigned long pte_update(struct mm_struct *mm, 241 unsigned long addr, 242 pte_t *ptep, unsigned long clr, 243 unsigned long set, 244 int huge) 245 { 246 unsigned long old, tmp; 247 248 __asm__ __volatile__( 249 "1: ldarx %0,0,%3 # pte_update\n\ 250 andi. %1,%0,%6\n\ 251 bne- 1b \n\ 252 andc %1,%0,%4 \n\ 253 or %1,%1,%7\n\ 254 stdcx. %1,0,%3 \n\ 255 bne- 1b" 256 : "=&r" (old), "=&r" (tmp), "=m" (*ptep) 257 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set) 258 : "cc" ); 259 /* huge pages use the old page table lock */ 260 if (!huge) 261 assert_pte_locked(mm, addr); 262 263 if (old & _PAGE_HASHPTE) 264 hpte_need_flush(mm, addr, ptep, old, huge); 265 266 return old; 267 } 268 269 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 270 unsigned long addr, pte_t *ptep) 271 { 272 unsigned long old; 273 274 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0) 275 return 0; 276 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 277 return (old & _PAGE_ACCESSED) != 0; 278 } 279 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 280 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 281 ({ \ 282 int __r; \ 283 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 284 __r; \ 285 }) 286 287 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 288 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 289 pte_t *ptep) 290 { 291 292 if ((pte_val(*ptep) & _PAGE_RW) == 0) 293 return; 294 295 pte_update(mm, addr, ptep, _PAGE_RW, 0, 0); 296 } 297 298 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 299 unsigned long addr, pte_t *ptep) 300 { 301 if ((pte_val(*ptep) & _PAGE_RW) == 0) 302 return; 303 304 pte_update(mm, addr, ptep, _PAGE_RW, 0, 1); 305 } 306 307 /* 308 * We currently remove entries from the hashtable regardless of whether 309 * the entry was young or dirty. The generic routines only flush if the 310 * entry was young or dirty which is not good enough. 311 * 312 * We should be more intelligent about this but for the moment we override 313 * these functions and force a tlb flush unconditionally 314 */ 315 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 316 #define ptep_clear_flush_young(__vma, __address, __ptep) \ 317 ({ \ 318 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \ 319 __ptep); \ 320 __young; \ 321 }) 322 323 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 324 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 325 unsigned long addr, pte_t *ptep) 326 { 327 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 328 return __pte(old); 329 } 330 331 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 332 pte_t * ptep) 333 { 334 pte_update(mm, addr, ptep, ~0UL, 0, 0); 335 } 336 337 338 /* Set the dirty and/or accessed bits atomically in a linux PTE, this 339 * function doesn't need to flush the hash entry 340 */ 341 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry) 342 { 343 unsigned long bits = pte_val(entry) & 344 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC | 345 _PAGE_SOFT_DIRTY); 346 347 unsigned long old, tmp; 348 349 __asm__ __volatile__( 350 "1: ldarx %0,0,%4\n\ 351 andi. %1,%0,%6\n\ 352 bne- 1b \n\ 353 or %0,%3,%0\n\ 354 stdcx. %0,0,%4\n\ 355 bne- 1b" 356 :"=&r" (old), "=&r" (tmp), "=m" (*ptep) 357 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY) 358 :"cc"); 359 } 360 361 #define __HAVE_ARCH_PTE_SAME 362 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0) 363 364 /* Generic accessors to PTE bits */ 365 static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);} 366 static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); } 367 static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); } 368 static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); } 369 static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; } 370 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 371 372 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 373 static inline bool pte_soft_dirty(pte_t pte) 374 { 375 return !!(pte_val(pte) & _PAGE_SOFT_DIRTY); 376 } 377 static inline pte_t pte_mksoft_dirty(pte_t pte) 378 { 379 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); 380 } 381 382 static inline pte_t pte_clear_soft_dirty(pte_t pte) 383 { 384 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); 385 } 386 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 387 388 #ifdef CONFIG_NUMA_BALANCING 389 /* 390 * These work without NUMA balancing but the kernel does not care. See the 391 * comment in include/asm-generic/pgtable.h . On powerpc, this will only 392 * work for user pages and always return true for kernel pages. 393 */ 394 static inline int pte_protnone(pte_t pte) 395 { 396 return (pte_val(pte) & 397 (_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT; 398 } 399 #endif /* CONFIG_NUMA_BALANCING */ 400 401 static inline int pte_present(pte_t pte) 402 { 403 return pte_val(pte) & _PAGE_PRESENT; 404 } 405 406 /* Conversion functions: convert a page and protection to a page entry, 407 * and a page entry and page directory to the page they refer to. 408 * 409 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 410 * long for now. 411 */ 412 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 413 { 414 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) | 415 pgprot_val(pgprot)); 416 } 417 418 static inline unsigned long pte_pfn(pte_t pte) 419 { 420 return pte_val(pte) >> PTE_RPN_SHIFT; 421 } 422 423 /* Generic modifiers for PTE bits */ 424 static inline pte_t pte_wrprotect(pte_t pte) 425 { 426 return __pte(pte_val(pte) & ~_PAGE_RW); 427 } 428 429 static inline pte_t pte_mkclean(pte_t pte) 430 { 431 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 432 } 433 434 static inline pte_t pte_mkold(pte_t pte) 435 { 436 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 437 } 438 439 static inline pte_t pte_mkwrite(pte_t pte) 440 { 441 return __pte(pte_val(pte) | _PAGE_RW); 442 } 443 444 static inline pte_t pte_mkdirty(pte_t pte) 445 { 446 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 447 } 448 449 static inline pte_t pte_mkyoung(pte_t pte) 450 { 451 return __pte(pte_val(pte) | _PAGE_ACCESSED); 452 } 453 454 static inline pte_t pte_mkspecial(pte_t pte) 455 { 456 return __pte(pte_val(pte) | _PAGE_SPECIAL); 457 } 458 459 static inline pte_t pte_mkhuge(pte_t pte) 460 { 461 return pte; 462 } 463 464 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 465 { 466 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 467 } 468 469 /* This low level function performs the actual PTE insertion 470 * Setting the PTE depends on the MMU type and other factors. It's 471 * an horrible mess that I'm not going to try to clean up now but 472 * I'm keeping it in one place rather than spread around 473 */ 474 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 475 pte_t *ptep, pte_t pte, int percpu) 476 { 477 /* 478 * Anything else just stores the PTE normally. That covers all 64-bit 479 * cases, and 32-bit non-hash with 32-bit PTEs. 480 */ 481 *ptep = pte; 482 } 483 484 /* 485 * Macro to mark a page protection value as "uncacheable". 486 */ 487 488 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \ 489 _PAGE_WRITETHRU) 490 491 #define pgprot_noncached pgprot_noncached 492 static inline pgprot_t pgprot_noncached(pgprot_t prot) 493 { 494 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 495 _PAGE_NO_CACHE | _PAGE_GUARDED); 496 } 497 498 #define pgprot_noncached_wc pgprot_noncached_wc 499 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 500 { 501 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 502 _PAGE_NO_CACHE); 503 } 504 505 #define pgprot_cached pgprot_cached 506 static inline pgprot_t pgprot_cached(pgprot_t prot) 507 { 508 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 509 _PAGE_COHERENT); 510 } 511 512 #define pgprot_cached_wthru pgprot_cached_wthru 513 static inline pgprot_t pgprot_cached_wthru(pgprot_t prot) 514 { 515 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 516 _PAGE_COHERENT | _PAGE_WRITETHRU); 517 } 518 519 #define pgprot_cached_noncoherent pgprot_cached_noncoherent 520 static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot) 521 { 522 return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL); 523 } 524 525 #define pgprot_writecombine pgprot_writecombine 526 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 527 { 528 return pgprot_noncached_wc(prot); 529 } 530 531 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 532 extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr, 533 pmd_t *pmdp, unsigned long old_pmd); 534 #else 535 static inline void hpte_do_hugepage_flush(struct mm_struct *mm, 536 unsigned long addr, pmd_t *pmdp, 537 unsigned long old_pmd) 538 { 539 WARN(1, "%s called with THP disabled\n", __func__); 540 } 541 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 542 543 #endif /* !__ASSEMBLY__ */ 544 #endif /* __KERNEL__ */ 545 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */ 546