1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_64K_H 3 #define _ASM_POWERPC_BOOK3S_64_HASH_64K_H 4 5 #define H_PTE_INDEX_SIZE 8 6 #define H_PMD_INDEX_SIZE 10 7 #define H_PUD_INDEX_SIZE 7 8 #define H_PGD_INDEX_SIZE 8 9 10 /* 11 * Each context is 512TB size. SLB miss for first context/default context 12 * is handled in the hotpath. 13 */ 14 #define MAX_EA_BITS_PER_CONTEXT 49 15 16 /* 17 * 64k aligned address free up few of the lower bits of RPN for us 18 * We steal that here. For more deatils look at pte_pfn/pfn_pte() 19 */ 20 #define H_PAGE_COMBO _RPAGE_RPN0 /* this is a combo 4k page */ 21 #define H_PAGE_4K_PFN _RPAGE_RPN1 /* PFN is for a single 4k page */ 22 #define H_PAGE_BUSY _RPAGE_RPN44 /* software: PTE & hash are busy */ 23 #define H_PAGE_HASHPTE _RPAGE_RPN43 /* PTE has associated HPTE */ 24 25 /* memory key bits. */ 26 #define H_PTE_PKEY_BIT0 _RPAGE_RSV1 27 #define H_PTE_PKEY_BIT1 _RPAGE_RSV2 28 #define H_PTE_PKEY_BIT2 _RPAGE_RSV3 29 #define H_PTE_PKEY_BIT3 _RPAGE_RSV4 30 #define H_PTE_PKEY_BIT4 _RPAGE_RSV5 31 32 /* 33 * We need to differentiate between explicit huge page and THP huge 34 * page, since THP huge page also need to track real subpage details 35 */ 36 #define H_PAGE_THP_HUGE H_PAGE_4K_PFN 37 38 /* PTE flags to conserve for HPTE identification */ 39 #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | H_PAGE_COMBO) 40 /* 41 * we support 16 fragments per PTE page of 64K size. 42 */ 43 #define H_PTE_FRAG_NR 16 44 /* 45 * We use a 2K PTE page fragment and another 2K for storing 46 * real_pte_t hash index 47 */ 48 #define H_PTE_FRAG_SIZE_SHIFT 12 49 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 50 51 #ifndef __ASSEMBLY__ 52 #include <asm/errno.h> 53 54 /* 55 * With 64K pages on hash table, we have a special PTE format that 56 * uses a second "half" of the page table to encode sub-page information 57 * in order to deal with 64K made of 4K HW pages. Thus we override the 58 * generic accessors and iterators here 59 */ 60 #define __real_pte __real_pte 61 static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep, int offset) 62 { 63 real_pte_t rpte; 64 unsigned long *hidxp; 65 66 rpte.pte = pte; 67 68 /* 69 * Ensure that we do not read the hidx before we read the PTE. Because 70 * the writer side is expected to finish writing the hidx first followed 71 * by the PTE, by using smp_wmb(). pte_set_hash_slot() ensures that. 72 */ 73 smp_rmb(); 74 75 hidxp = (unsigned long *)(ptep + offset); 76 rpte.hidx = *hidxp; 77 return rpte; 78 } 79 80 /* 81 * shift the hidx representation by one-modulo-0xf; i.e hidx 0 is respresented 82 * as 1, 1 as 2,... , and 0xf as 0. This convention lets us represent a 83 * invalid hidx 0xf with a 0x0 bit value. PTEs are anyway zero'd when 84 * allocated. We dont have to zero them gain; thus save on the initialization. 85 */ 86 #define HIDX_UNSHIFT_BY_ONE(x) ((x + 0xfUL) & 0xfUL) /* shift backward by one */ 87 #define HIDX_SHIFT_BY_ONE(x) ((x + 0x1UL) & 0xfUL) /* shift forward by one */ 88 #define HIDX_BITS(x, index) (x << (index << 2)) 89 #define BITS_TO_HIDX(x, index) ((x >> (index << 2)) & 0xfUL) 90 #define INVALID_RPTE_HIDX 0x0UL 91 92 static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index) 93 { 94 return HIDX_UNSHIFT_BY_ONE(BITS_TO_HIDX(rpte.hidx, index)); 95 } 96 97 /* 98 * Commit the hidx and return PTE bits that needs to be modified. The caller is 99 * expected to modify the PTE bits accordingly and commit the PTE to memory. 100 */ 101 static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte, 102 unsigned int subpg_index, 103 unsigned long hidx, int offset) 104 { 105 unsigned long *hidxp = (unsigned long *)(ptep + offset); 106 107 rpte.hidx &= ~HIDX_BITS(0xfUL, subpg_index); 108 *hidxp = rpte.hidx | HIDX_BITS(HIDX_SHIFT_BY_ONE(hidx), subpg_index); 109 110 /* 111 * Anyone reading PTE must ensure hidx bits are read after reading the 112 * PTE by using the read-side barrier smp_rmb(). __real_pte() can be 113 * used for that. 114 */ 115 smp_wmb(); 116 117 /* No PTE bits to be modified, return 0x0UL */ 118 return 0x0UL; 119 } 120 121 #define __rpte_to_pte(r) ((r).pte) 122 extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index); 123 /* 124 * Trick: we set __end to va + 64k, which happens works for 125 * a 16M page as well as we want only one iteration 126 */ 127 #define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \ 128 do { \ 129 unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT)); \ 130 unsigned __split = (psize == MMU_PAGE_4K || \ 131 psize == MMU_PAGE_64K_AP); \ 132 shift = mmu_psize_defs[psize].shift; \ 133 for (index = 0; vpn < __end; index++, \ 134 vpn += (1L << (shift - VPN_SHIFT))) { \ 135 if (!__split || __rpte_sub_valid(rpte, index)) \ 136 do { 137 138 #define pte_iterate_hashed_end() } while(0); } } while(0) 139 140 #define pte_pagesize_index(mm, addr, pte) \ 141 (((pte) & H_PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K) 142 143 extern int remap_pfn_range(struct vm_area_struct *, unsigned long addr, 144 unsigned long pfn, unsigned long size, pgprot_t); 145 static inline int hash__remap_4k_pfn(struct vm_area_struct *vma, unsigned long addr, 146 unsigned long pfn, pgprot_t prot) 147 { 148 if (pfn > (PTE_RPN_MASK >> PAGE_SHIFT)) { 149 WARN(1, "remap_4k_pfn called with wrong pfn value\n"); 150 return -EINVAL; 151 } 152 return remap_pfn_range(vma, addr, pfn, PAGE_SIZE, 153 __pgprot(pgprot_val(prot) | H_PAGE_4K_PFN)); 154 } 155 156 #define H_PTE_TABLE_SIZE PTE_FRAG_SIZE 157 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined (CONFIG_HUGETLB_PAGE) 158 #define H_PMD_TABLE_SIZE ((sizeof(pmd_t) << PMD_INDEX_SIZE) + \ 159 (sizeof(unsigned long) << PMD_INDEX_SIZE)) 160 #else 161 #define H_PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) 162 #endif 163 #ifdef CONFIG_HUGETLB_PAGE 164 #define H_PUD_TABLE_SIZE ((sizeof(pud_t) << PUD_INDEX_SIZE) + \ 165 (sizeof(unsigned long) << PUD_INDEX_SIZE)) 166 #else 167 #define H_PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE) 168 #endif 169 #define H_PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 170 171 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 172 static inline char *get_hpte_slot_array(pmd_t *pmdp) 173 { 174 /* 175 * The hpte hindex is stored in the pgtable whose address is in the 176 * second half of the PMD 177 * 178 * Order this load with the test for pmd_trans_huge in the caller 179 */ 180 smp_rmb(); 181 return *(char **)(pmdp + PTRS_PER_PMD); 182 183 184 } 185 /* 186 * The linux hugepage PMD now include the pmd entries followed by the address 187 * to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits. 188 * [ 000 | 1 bit secondary | 3 bit hidx | 1 bit valid]. We use one byte per 189 * each HPTE entry. With 16MB hugepage and 64K HPTE we need 256 entries and 190 * with 4K HPTE we need 4096 entries. Both will fit in a 4K pgtable_t. 191 * 192 * The top three bits are intentionally left as zero. This memory location 193 * are also used as normal page PTE pointers. So if we have any pointers 194 * left around while we collapse a hugepage, we need to make sure 195 * _PAGE_PRESENT bit of that is zero when we look at them 196 */ 197 static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index) 198 { 199 return hpte_slot_array[index] & 0x1; 200 } 201 202 static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array, 203 int index) 204 { 205 return hpte_slot_array[index] >> 1; 206 } 207 208 static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array, 209 unsigned int index, unsigned int hidx) 210 { 211 hpte_slot_array[index] = (hidx << 1) | 0x1; 212 } 213 214 /* 215 * 216 * For core kernel code by design pmd_trans_huge is never run on any hugetlbfs 217 * page. The hugetlbfs page table walking and mangling paths are totally 218 * separated form the core VM paths and they're differentiated by 219 * VM_HUGETLB being set on vm_flags well before any pmd_trans_huge could run. 220 * 221 * pmd_trans_huge() is defined as false at build time if 222 * CONFIG_TRANSPARENT_HUGEPAGE=n to optimize away code blocks at build 223 * time in such case. 224 * 225 * For ppc64 we need to differntiate from explicit hugepages from THP, because 226 * for THP we also track the subpage details at the pmd level. We don't do 227 * that for explicit huge pages. 228 * 229 */ 230 static inline int hash__pmd_trans_huge(pmd_t pmd) 231 { 232 return !!((pmd_val(pmd) & (_PAGE_PTE | H_PAGE_THP_HUGE)) == 233 (_PAGE_PTE | H_PAGE_THP_HUGE)); 234 } 235 236 static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b) 237 { 238 return (((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0); 239 } 240 241 static inline pmd_t hash__pmd_mkhuge(pmd_t pmd) 242 { 243 return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE)); 244 } 245 246 extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm, 247 unsigned long addr, pmd_t *pmdp, 248 unsigned long clr, unsigned long set); 249 extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma, 250 unsigned long address, pmd_t *pmdp); 251 extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 252 pgtable_t pgtable); 253 extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 254 extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm, 255 unsigned long addr, pmd_t *pmdp); 256 extern int hash__has_transparent_hugepage(void); 257 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 258 #endif /* __ASSEMBLY__ */ 259 260 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_64K_H */ 261