1 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_64K_H 2 #define _ASM_POWERPC_BOOK3S_64_HASH_64K_H 3 4 #include <asm-generic/pgtable-nopud.h> 5 6 #define PTE_INDEX_SIZE 8 7 #define PMD_INDEX_SIZE 10 8 #define PUD_INDEX_SIZE 0 9 #define PGD_INDEX_SIZE 12 10 11 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 12 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 13 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 14 15 /* With 4k base page size, hugepage PTEs go at the PMD level */ 16 #define MIN_HUGEPTE_SHIFT PAGE_SHIFT 17 18 /* PMD_SHIFT determines what a second-level page table entry can map */ 19 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 20 #define PMD_SIZE (1UL << PMD_SHIFT) 21 #define PMD_MASK (~(PMD_SIZE-1)) 22 23 /* PGDIR_SHIFT determines what a third-level page table entry can map */ 24 #define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 25 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 26 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 27 28 /* Bits to mask out from a PMD to get to the PTE page */ 29 /* PMDs point to PTE table fragments which are 4K aligned. */ 30 #define PMD_MASKED_BITS 0xfff 31 /* Bits to mask out from a PGD/PUD to get to the PMD page */ 32 #define PUD_MASKED_BITS 0x1ff 33 34 #define _PAGE_COMBO 0x00020000 /* this is a combo 4k page */ 35 #define _PAGE_4K_PFN 0x00040000 /* PFN is for a single 4k page */ 36 /* 37 * Used to track subpage group valid if _PAGE_COMBO is set 38 * This overloads _PAGE_F_GIX and _PAGE_F_SECOND 39 */ 40 #define _PAGE_COMBO_VALID (_PAGE_F_GIX | _PAGE_F_SECOND) 41 42 /* PTE flags to conserve for HPTE identification */ 43 #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO) 44 45 /* Shift to put page number into pte. 46 * 47 * That gives us a max RPN of 34 bits, which means a max of 50 bits 48 * of addressable physical space, or 46 bits for the special 4k PFNs. 49 */ 50 #define PTE_RPN_SHIFT (30) 51 52 #ifndef __ASSEMBLY__ 53 54 /* 55 * With 64K pages on hash table, we have a special PTE format that 56 * uses a second "half" of the page table to encode sub-page information 57 * in order to deal with 64K made of 4K HW pages. Thus we override the 58 * generic accessors and iterators here 59 */ 60 #define __real_pte __real_pte 61 static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep) 62 { 63 real_pte_t rpte; 64 65 rpte.pte = pte; 66 rpte.hidx = 0; 67 if (pte_val(pte) & _PAGE_COMBO) { 68 /* 69 * Make sure we order the hidx load against the _PAGE_COMBO 70 * check. The store side ordering is done in __hash_page_4K 71 */ 72 smp_rmb(); 73 rpte.hidx = pte_val(*((ptep) + PTRS_PER_PTE)); 74 } 75 return rpte; 76 } 77 78 static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index) 79 { 80 if ((pte_val(rpte.pte) & _PAGE_COMBO)) 81 return (rpte.hidx >> (index<<2)) & 0xf; 82 return (pte_val(rpte.pte) >> 12) & 0xf; 83 } 84 85 #define __rpte_to_pte(r) ((r).pte) 86 extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index); 87 /* 88 * Trick: we set __end to va + 64k, which happens works for 89 * a 16M page as well as we want only one iteration 90 */ 91 #define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \ 92 do { \ 93 unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT)); \ 94 unsigned __split = (psize == MMU_PAGE_4K || \ 95 psize == MMU_PAGE_64K_AP); \ 96 shift = mmu_psize_defs[psize].shift; \ 97 for (index = 0; vpn < __end; index++, \ 98 vpn += (1L << (shift - VPN_SHIFT))) { \ 99 if (!__split || __rpte_sub_valid(rpte, index)) \ 100 do { 101 102 #define pte_iterate_hashed_end() } while(0); } } while(0) 103 104 #define pte_pagesize_index(mm, addr, pte) \ 105 (((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K) 106 107 #define remap_4k_pfn(vma, addr, pfn, prot) \ 108 (WARN_ON(((pfn) >= (1UL << (64 - PTE_RPN_SHIFT)))) ? -EINVAL : \ 109 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \ 110 __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))) 111 112 #define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE) 113 #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) 114 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 115 116 #define pgd_pte(pgd) (pud_pte(((pud_t){ pgd }))) 117 #define pte_pgd(pte) ((pgd_t)pte_pud(pte)) 118 119 #endif /* __ASSEMBLY__ */ 120 121 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_64K_H */ 122