1 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_64K_H 2 #define _ASM_POWERPC_BOOK3S_64_HASH_64K_H 3 4 #define H_PTE_INDEX_SIZE 8 5 #define H_PMD_INDEX_SIZE 10 6 #define H_PUD_INDEX_SIZE 7 7 #define H_PGD_INDEX_SIZE 8 8 9 /* 10 * 64k aligned address free up few of the lower bits of RPN for us 11 * We steal that here. For more deatils look at pte_pfn/pfn_pte() 12 */ 13 #define H_PAGE_COMBO _RPAGE_RPN0 /* this is a combo 4k page */ 14 #define H_PAGE_4K_PFN _RPAGE_RPN1 /* PFN is for a single 4k page */ 15 /* 16 * We need to differentiate between explicit huge page and THP huge 17 * page, since THP huge page also need to track real subpage details 18 */ 19 #define H_PAGE_THP_HUGE H_PAGE_4K_PFN 20 21 /* 22 * Used to track subpage group valid if H_PAGE_COMBO is set 23 * This overloads H_PAGE_F_GIX and H_PAGE_F_SECOND 24 */ 25 #define H_PAGE_COMBO_VALID (H_PAGE_F_GIX | H_PAGE_F_SECOND) 26 27 /* PTE flags to conserve for HPTE identification */ 28 #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_F_SECOND | \ 29 H_PAGE_F_GIX | H_PAGE_HASHPTE | H_PAGE_COMBO) 30 /* 31 * we support 16 fragments per PTE page of 64K size. 32 */ 33 #define H_PTE_FRAG_NR 16 34 /* 35 * We use a 2K PTE page fragment and another 2K for storing 36 * real_pte_t hash index 37 */ 38 #define H_PTE_FRAG_SIZE_SHIFT 12 39 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 40 41 #ifndef __ASSEMBLY__ 42 #include <asm/errno.h> 43 44 /* 45 * With 64K pages on hash table, we have a special PTE format that 46 * uses a second "half" of the page table to encode sub-page information 47 * in order to deal with 64K made of 4K HW pages. Thus we override the 48 * generic accessors and iterators here 49 */ 50 #define __real_pte __real_pte 51 static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep) 52 { 53 real_pte_t rpte; 54 unsigned long *hidxp; 55 56 rpte.pte = pte; 57 rpte.hidx = 0; 58 if (pte_val(pte) & H_PAGE_COMBO) { 59 /* 60 * Make sure we order the hidx load against the H_PAGE_COMBO 61 * check. The store side ordering is done in __hash_page_4K 62 */ 63 smp_rmb(); 64 hidxp = (unsigned long *)(ptep + PTRS_PER_PTE); 65 rpte.hidx = *hidxp; 66 } 67 return rpte; 68 } 69 70 static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index) 71 { 72 if ((pte_val(rpte.pte) & H_PAGE_COMBO)) 73 return (rpte.hidx >> (index<<2)) & 0xf; 74 return (pte_val(rpte.pte) >> H_PAGE_F_GIX_SHIFT) & 0xf; 75 } 76 77 #define __rpte_to_pte(r) ((r).pte) 78 extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index); 79 /* 80 * Trick: we set __end to va + 64k, which happens works for 81 * a 16M page as well as we want only one iteration 82 */ 83 #define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \ 84 do { \ 85 unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT)); \ 86 unsigned __split = (psize == MMU_PAGE_4K || \ 87 psize == MMU_PAGE_64K_AP); \ 88 shift = mmu_psize_defs[psize].shift; \ 89 for (index = 0; vpn < __end; index++, \ 90 vpn += (1L << (shift - VPN_SHIFT))) { \ 91 if (!__split || __rpte_sub_valid(rpte, index)) \ 92 do { 93 94 #define pte_iterate_hashed_end() } while(0); } } while(0) 95 96 #define pte_pagesize_index(mm, addr, pte) \ 97 (((pte) & H_PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K) 98 99 extern int remap_pfn_range(struct vm_area_struct *, unsigned long addr, 100 unsigned long pfn, unsigned long size, pgprot_t); 101 static inline int hash__remap_4k_pfn(struct vm_area_struct *vma, unsigned long addr, 102 unsigned long pfn, pgprot_t prot) 103 { 104 if (pfn > (PTE_RPN_MASK >> PAGE_SHIFT)) { 105 WARN(1, "remap_4k_pfn called with wrong pfn value\n"); 106 return -EINVAL; 107 } 108 return remap_pfn_range(vma, addr, pfn, PAGE_SIZE, 109 __pgprot(pgprot_val(prot) | H_PAGE_4K_PFN)); 110 } 111 112 #define H_PTE_TABLE_SIZE PTE_FRAG_SIZE 113 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 114 #define H_PMD_TABLE_SIZE ((sizeof(pmd_t) << PMD_INDEX_SIZE) + \ 115 (sizeof(unsigned long) << PMD_INDEX_SIZE)) 116 #else 117 #define H_PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) 118 #endif 119 #define H_PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE) 120 #define H_PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 121 122 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 123 static inline char *get_hpte_slot_array(pmd_t *pmdp) 124 { 125 /* 126 * The hpte hindex is stored in the pgtable whose address is in the 127 * second half of the PMD 128 * 129 * Order this load with the test for pmd_trans_huge in the caller 130 */ 131 smp_rmb(); 132 return *(char **)(pmdp + PTRS_PER_PMD); 133 134 135 } 136 /* 137 * The linux hugepage PMD now include the pmd entries followed by the address 138 * to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits. 139 * [ 000 | 1 bit secondary | 3 bit hidx | 1 bit valid]. We use one byte per 140 * each HPTE entry. With 16MB hugepage and 64K HPTE we need 256 entries and 141 * with 4K HPTE we need 4096 entries. Both will fit in a 4K pgtable_t. 142 * 143 * The top three bits are intentionally left as zero. This memory location 144 * are also used as normal page PTE pointers. So if we have any pointers 145 * left around while we collapse a hugepage, we need to make sure 146 * _PAGE_PRESENT bit of that is zero when we look at them 147 */ 148 static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index) 149 { 150 return hpte_slot_array[index] & 0x1; 151 } 152 153 static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array, 154 int index) 155 { 156 return hpte_slot_array[index] >> 1; 157 } 158 159 static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array, 160 unsigned int index, unsigned int hidx) 161 { 162 hpte_slot_array[index] = (hidx << 1) | 0x1; 163 } 164 165 /* 166 * 167 * For core kernel code by design pmd_trans_huge is never run on any hugetlbfs 168 * page. The hugetlbfs page table walking and mangling paths are totally 169 * separated form the core VM paths and they're differentiated by 170 * VM_HUGETLB being set on vm_flags well before any pmd_trans_huge could run. 171 * 172 * pmd_trans_huge() is defined as false at build time if 173 * CONFIG_TRANSPARENT_HUGEPAGE=n to optimize away code blocks at build 174 * time in such case. 175 * 176 * For ppc64 we need to differntiate from explicit hugepages from THP, because 177 * for THP we also track the subpage details at the pmd level. We don't do 178 * that for explicit huge pages. 179 * 180 */ 181 static inline int hash__pmd_trans_huge(pmd_t pmd) 182 { 183 return !!((pmd_val(pmd) & (_PAGE_PTE | H_PAGE_THP_HUGE)) == 184 (_PAGE_PTE | H_PAGE_THP_HUGE)); 185 } 186 187 static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b) 188 { 189 return (((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0); 190 } 191 192 static inline pmd_t hash__pmd_mkhuge(pmd_t pmd) 193 { 194 return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE)); 195 } 196 197 extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm, 198 unsigned long addr, pmd_t *pmdp, 199 unsigned long clr, unsigned long set); 200 extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma, 201 unsigned long address, pmd_t *pmdp); 202 extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 203 pgtable_t pgtable); 204 extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 205 extern void hash__pmdp_huge_split_prepare(struct vm_area_struct *vma, 206 unsigned long address, pmd_t *pmdp); 207 extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm, 208 unsigned long addr, pmd_t *pmdp); 209 extern int hash__has_transparent_hugepage(void); 210 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 211 #endif /* __ASSEMBLY__ */ 212 213 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_64K_H */ 214