1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_32_PGTABLE_H 3 #define _ASM_POWERPC_BOOK3S_32_PGTABLE_H 4 5 #include <asm-generic/pgtable-nopmd.h> 6 7 /* 8 * The "classic" 32-bit implementation of the PowerPC MMU uses a hash 9 * table containing PTEs, together with a set of 16 segment registers, 10 * to define the virtual to physical address mapping. 11 * 12 * We use the hash table as an extended TLB, i.e. a cache of currently 13 * active mappings. We maintain a two-level page table tree, much 14 * like that used by the i386, for the sake of the Linux memory 15 * management code. Low-level assembler code in hash_low_32.S 16 * (procedure hash_page) is responsible for extracting ptes from the 17 * tree and putting them into the hash table when necessary, and 18 * updating the accessed and modified bits in the page table tree. 19 */ 20 21 #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ 22 #define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */ 23 #define _PAGE_USER 0x004 /* usermode access allowed */ 24 #define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */ 25 #define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ 26 #define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ 27 #define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ 28 #define _PAGE_DIRTY 0x080 /* C: page changed */ 29 #define _PAGE_ACCESSED 0x100 /* R: page referenced */ 30 #define _PAGE_EXEC 0x200 /* software: exec allowed */ 31 #define _PAGE_RW 0x400 /* software: user write access allowed */ 32 #define _PAGE_SPECIAL 0x800 /* software: Special page */ 33 34 #ifdef CONFIG_PTE_64BIT 35 /* We never clear the high word of the pte */ 36 #define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE) 37 #else 38 #define _PTE_NONE_MASK _PAGE_HASHPTE 39 #endif 40 41 #define _PMD_PRESENT 0 42 #define _PMD_PRESENT_MASK (PAGE_MASK) 43 #define _PMD_BAD (~PAGE_MASK) 44 45 /* And here we include common definitions */ 46 47 #define _PAGE_KERNEL_RO 0 48 #define _PAGE_KERNEL_ROX (_PAGE_EXEC) 49 #define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW) 50 #define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 51 52 #define _PAGE_HPTEFLAGS _PAGE_HASHPTE 53 54 #ifndef __ASSEMBLY__ 55 56 static inline bool pte_user(pte_t pte) 57 { 58 return pte_val(pte) & _PAGE_USER; 59 } 60 #endif /* __ASSEMBLY__ */ 61 62 /* 63 * Location of the PFN in the PTE. Most 32-bit platforms use the same 64 * as _PAGE_SHIFT here (ie, naturally aligned). 65 * Platform who don't just pre-define the value so we don't override it here. 66 */ 67 #define PTE_RPN_SHIFT (PAGE_SHIFT) 68 69 /* 70 * The mask covered by the RPN must be a ULL on 32-bit platforms with 71 * 64-bit PTEs. 72 */ 73 #ifdef CONFIG_PTE_64BIT 74 #define PTE_RPN_MASK (~((1ULL << PTE_RPN_SHIFT) - 1)) 75 #define MAX_POSSIBLE_PHYSMEM_BITS 36 76 #else 77 #define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1)) 78 #define MAX_POSSIBLE_PHYSMEM_BITS 32 79 #endif 80 81 /* 82 * _PAGE_CHG_MASK masks of bits that are to be preserved across 83 * pgprot changes. 84 */ 85 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HASHPTE | _PAGE_DIRTY | \ 86 _PAGE_ACCESSED | _PAGE_SPECIAL) 87 88 /* 89 * We define 2 sets of base prot bits, one for basic pages (ie, 90 * cacheable kernel and user pages) and one for non cacheable 91 * pages. We always set _PAGE_COHERENT when SMP is enabled or 92 * the processor might need it for DMA coherency. 93 */ 94 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 95 #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 96 97 /* 98 * Permission masks used to generate the __P and __S table. 99 * 100 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 101 * 102 * Write permissions imply read permissions for now. 103 */ 104 #define PAGE_NONE __pgprot(_PAGE_BASE) 105 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 106 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 107 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 108 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 109 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 110 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 111 112 /* Permission masks used for kernel mappings */ 113 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 114 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE) 115 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE | _PAGE_GUARDED) 116 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 117 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 118 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 119 120 #define PTE_INDEX_SIZE PTE_SHIFT 121 #define PMD_INDEX_SIZE 0 122 #define PUD_INDEX_SIZE 0 123 #define PGD_INDEX_SIZE (32 - PGDIR_SHIFT) 124 125 #define PMD_CACHE_INDEX PMD_INDEX_SIZE 126 #define PUD_CACHE_INDEX PUD_INDEX_SIZE 127 128 #ifndef __ASSEMBLY__ 129 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) 130 #define PMD_TABLE_SIZE 0 131 #define PUD_TABLE_SIZE 0 132 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 133 134 /* Bits to mask out from a PMD to get to the PTE page */ 135 #define PMD_MASKED_BITS (PTE_TABLE_SIZE - 1) 136 #endif /* __ASSEMBLY__ */ 137 138 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 139 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 140 141 /* 142 * The normal case is that PTEs are 32-bits and we have a 1-page 143 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 144 * 145 * For any >32-bit physical address platform, we can use the following 146 * two level page table layout where the pgdir is 8KB and the MS 13 bits 147 * are an index to the second level table. The combined pgdir/pmd first 148 * level has 2048 entries and the second level has 512 64-bit PTE entries. 149 * -Matt 150 */ 151 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 152 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 153 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 154 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 155 156 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 157 158 #ifndef __ASSEMBLY__ 159 160 int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot); 161 void unmap_kernel_page(unsigned long va); 162 163 #endif /* !__ASSEMBLY__ */ 164 165 /* 166 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary 167 * value (for now) on others, from where we can start layout kernel 168 * virtual space that goes below PKMAP and FIXMAP 169 */ 170 #include <asm/fixmap.h> 171 172 /* 173 * ioremap_bot starts at that address. Early ioremaps move down from there, 174 * until mem_init() at which point this becomes the top of the vmalloc 175 * and ioremap space 176 */ 177 #ifdef CONFIG_HIGHMEM 178 #define IOREMAP_TOP PKMAP_BASE 179 #else 180 #define IOREMAP_TOP FIXADDR_START 181 #endif 182 183 /* PPC32 shares vmalloc area with ioremap */ 184 #define IOREMAP_START VMALLOC_START 185 #define IOREMAP_END VMALLOC_END 186 187 /* 188 * Just any arbitrary offset to the start of the vmalloc VM area: the 189 * current 16MB value just means that there will be a 64MB "hole" after the 190 * physical memory until the kernel virtual memory starts. That means that 191 * any out-of-bounds memory accesses will hopefully be caught. 192 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 193 * area for the same reason. ;) 194 * 195 * We no longer map larger than phys RAM with the BATs so we don't have 196 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry 197 * about clashes between our early calls to ioremap() that start growing down 198 * from ioremap_base being run into the VM area allocations (growing upwards 199 * from VMALLOC_START). For this reason we have ioremap_bot to check when 200 * we actually run into our mappings setup in the early boot with the VM 201 * system. This really does become a problem for machines with good amounts 202 * of RAM. -- Cort 203 */ 204 #define VMALLOC_OFFSET (0x1000000) /* 16M */ 205 206 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) 207 208 #ifdef CONFIG_KASAN_VMALLOC 209 #define VMALLOC_END ALIGN_DOWN(ioremap_bot, PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT) 210 #else 211 #define VMALLOC_END ioremap_bot 212 #endif 213 214 #define MODULES_END ALIGN_DOWN(PAGE_OFFSET, SZ_256M) 215 #define MODULES_VADDR (MODULES_END - SZ_256M) 216 217 #ifndef __ASSEMBLY__ 218 #include <linux/sched.h> 219 #include <linux/threads.h> 220 221 /* Bits to mask out from a PGD to get to the PUD page */ 222 #define PGD_MASKED_BITS 0 223 224 #define pte_ERROR(e) \ 225 pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \ 226 (unsigned long long)pte_val(e)) 227 #define pgd_ERROR(e) \ 228 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 229 /* 230 * Bits in a linux-style PTE. These match the bits in the 231 * (hardware-defined) PowerPC PTE as closely as possible. 232 */ 233 234 #define pte_clear(mm, addr, ptep) \ 235 do { pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0); } while (0) 236 237 #define pmd_none(pmd) (!pmd_val(pmd)) 238 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) 239 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) 240 static inline void pmd_clear(pmd_t *pmdp) 241 { 242 *pmdp = __pmd(0); 243 } 244 245 246 /* 247 * When flushing the tlb entry for a page, we also need to flush the hash 248 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S. 249 */ 250 extern int flush_hash_pages(unsigned context, unsigned long va, 251 unsigned long pmdval, int count); 252 253 /* Add an HPTE to the hash table */ 254 extern void add_hash_page(unsigned context, unsigned long va, 255 unsigned long pmdval); 256 257 /* Flush an entry from the TLB/hash table */ 258 static inline void flush_hash_entry(struct mm_struct *mm, pte_t *ptep, unsigned long addr) 259 { 260 if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) { 261 unsigned long ptephys = __pa(ptep) & PAGE_MASK; 262 263 flush_hash_pages(mm->context.id, addr, ptephys, 1); 264 } 265 } 266 267 /* 268 * PTE updates. This function is called whenever an existing 269 * valid PTE is updated. This does -not- include set_pte_at() 270 * which nowadays only sets a new PTE. 271 * 272 * Depending on the type of MMU, we may need to use atomic updates 273 * and the PTE may be either 32 or 64 bit wide. In the later case, 274 * when using atomic updates, only the low part of the PTE is 275 * accessed atomically. 276 */ 277 static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p, 278 unsigned long clr, unsigned long set, int huge) 279 { 280 pte_basic_t old; 281 282 if (mmu_has_feature(MMU_FTR_HPTE_TABLE)) { 283 unsigned long tmp; 284 285 asm volatile( 286 #ifndef CONFIG_PTE_64BIT 287 "1: lwarx %0, 0, %3\n" 288 " andc %1, %0, %4\n" 289 #else 290 "1: lwarx %L0, 0, %3\n" 291 " lwz %0, -4(%3)\n" 292 " andc %1, %L0, %4\n" 293 #endif 294 " or %1, %1, %5\n" 295 " stwcx. %1, 0, %3\n" 296 " bne- 1b" 297 : "=&r" (old), "=&r" (tmp), "=m" (*p) 298 #ifndef CONFIG_PTE_64BIT 299 : "r" (p), 300 #else 301 : "b" ((unsigned long)(p) + 4), 302 #endif 303 "r" (clr), "r" (set), "m" (*p) 304 : "cc" ); 305 } else { 306 old = pte_val(*p); 307 308 *p = __pte((old & ~(pte_basic_t)clr) | set); 309 } 310 311 return old; 312 } 313 314 /* 315 * 2.6 calls this without flushing the TLB entry; this is wrong 316 * for our hash-based implementation, we fix that up here. 317 */ 318 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 319 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 320 unsigned long addr, pte_t *ptep) 321 { 322 unsigned long old; 323 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 324 if (old & _PAGE_HASHPTE) 325 flush_hash_entry(mm, ptep, addr); 326 327 return (old & _PAGE_ACCESSED) != 0; 328 } 329 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 330 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep) 331 332 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 333 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 334 pte_t *ptep) 335 { 336 return __pte(pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0)); 337 } 338 339 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 340 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 341 pte_t *ptep) 342 { 343 pte_update(mm, addr, ptep, _PAGE_RW, 0, 0); 344 } 345 346 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 347 pte_t *ptep, pte_t entry, 348 unsigned long address, 349 int psize) 350 { 351 unsigned long set = pte_val(entry) & 352 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); 353 354 pte_update(vma->vm_mm, address, ptep, 0, set, 0); 355 356 flush_tlb_page(vma, address); 357 } 358 359 #define __HAVE_ARCH_PTE_SAME 360 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) 361 362 #define pmd_pfn(pmd) (pmd_val(pmd) >> PAGE_SHIFT) 363 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 364 365 /* 366 * Encode and decode a swap entry. 367 * Note that the bits we use in a PTE for representing a swap entry 368 * must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used). 369 * -- paulus 370 */ 371 #define __swp_type(entry) ((entry).val & 0x1f) 372 #define __swp_offset(entry) ((entry).val >> 5) 373 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) 374 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) 375 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) 376 377 /* Generic accessors to PTE bits */ 378 static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);} 379 static inline int pte_read(pte_t pte) { return 1; } 380 static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); } 381 static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); } 382 static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); } 383 static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; } 384 static inline bool pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 385 386 static inline int pte_present(pte_t pte) 387 { 388 return pte_val(pte) & _PAGE_PRESENT; 389 } 390 391 static inline bool pte_hw_valid(pte_t pte) 392 { 393 return pte_val(pte) & _PAGE_PRESENT; 394 } 395 396 static inline bool pte_hashpte(pte_t pte) 397 { 398 return !!(pte_val(pte) & _PAGE_HASHPTE); 399 } 400 401 static inline bool pte_ci(pte_t pte) 402 { 403 return !!(pte_val(pte) & _PAGE_NO_CACHE); 404 } 405 406 /* 407 * We only find page table entry in the last level 408 * Hence no need for other accessors 409 */ 410 #define pte_access_permitted pte_access_permitted 411 static inline bool pte_access_permitted(pte_t pte, bool write) 412 { 413 /* 414 * A read-only access is controlled by _PAGE_USER bit. 415 * We have _PAGE_READ set for WRITE and EXECUTE 416 */ 417 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 418 return false; 419 420 if (write && !pte_write(pte)) 421 return false; 422 423 return true; 424 } 425 426 /* Conversion functions: convert a page and protection to a page entry, 427 * and a page entry and page directory to the page they refer to. 428 * 429 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 430 * long for now. 431 */ 432 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 433 { 434 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) | 435 pgprot_val(pgprot)); 436 } 437 438 static inline unsigned long pte_pfn(pte_t pte) 439 { 440 return pte_val(pte) >> PTE_RPN_SHIFT; 441 } 442 443 /* Generic modifiers for PTE bits */ 444 static inline pte_t pte_wrprotect(pte_t pte) 445 { 446 return __pte(pte_val(pte) & ~_PAGE_RW); 447 } 448 449 static inline pte_t pte_exprotect(pte_t pte) 450 { 451 return __pte(pte_val(pte) & ~_PAGE_EXEC); 452 } 453 454 static inline pte_t pte_mkclean(pte_t pte) 455 { 456 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 457 } 458 459 static inline pte_t pte_mkold(pte_t pte) 460 { 461 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 462 } 463 464 static inline pte_t pte_mkexec(pte_t pte) 465 { 466 return __pte(pte_val(pte) | _PAGE_EXEC); 467 } 468 469 static inline pte_t pte_mkpte(pte_t pte) 470 { 471 return pte; 472 } 473 474 static inline pte_t pte_mkwrite(pte_t pte) 475 { 476 return __pte(pte_val(pte) | _PAGE_RW); 477 } 478 479 static inline pte_t pte_mkdirty(pte_t pte) 480 { 481 return __pte(pte_val(pte) | _PAGE_DIRTY); 482 } 483 484 static inline pte_t pte_mkyoung(pte_t pte) 485 { 486 return __pte(pte_val(pte) | _PAGE_ACCESSED); 487 } 488 489 static inline pte_t pte_mkspecial(pte_t pte) 490 { 491 return __pte(pte_val(pte) | _PAGE_SPECIAL); 492 } 493 494 static inline pte_t pte_mkhuge(pte_t pte) 495 { 496 return pte; 497 } 498 499 static inline pte_t pte_mkprivileged(pte_t pte) 500 { 501 return __pte(pte_val(pte) & ~_PAGE_USER); 502 } 503 504 static inline pte_t pte_mkuser(pte_t pte) 505 { 506 return __pte(pte_val(pte) | _PAGE_USER); 507 } 508 509 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 510 { 511 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 512 } 513 514 515 516 /* This low level function performs the actual PTE insertion 517 * Setting the PTE depends on the MMU type and other factors. It's 518 * an horrible mess that I'm not going to try to clean up now but 519 * I'm keeping it in one place rather than spread around 520 */ 521 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 522 pte_t *ptep, pte_t pte, int percpu) 523 { 524 #if defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT) 525 /* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the 526 * helper pte_update() which does an atomic update. We need to do that 527 * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a 528 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving 529 * the hash bits instead (ie, same as the non-SMP case) 530 */ 531 if (percpu) 532 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 533 | (pte_val(pte) & ~_PAGE_HASHPTE)); 534 else 535 pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, pte_val(pte), 0); 536 537 #elif defined(CONFIG_PTE_64BIT) 538 /* Second case is 32-bit with 64-bit PTE. In this case, we 539 * can just store as long as we do the two halves in the right order 540 * with a barrier in between. This is possible because we take care, 541 * in the hash code, to pre-invalidate if the PTE was already hashed, 542 * which synchronizes us with any concurrent invalidation. 543 * In the percpu case, we also fallback to the simple update preserving 544 * the hash bits 545 */ 546 if (percpu) { 547 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 548 | (pte_val(pte) & ~_PAGE_HASHPTE)); 549 return; 550 } 551 if (pte_val(*ptep) & _PAGE_HASHPTE) 552 flush_hash_entry(mm, ptep, addr); 553 __asm__ __volatile__("\ 554 stw%X0 %2,%0\n\ 555 eieio\n\ 556 stw%X1 %L2,%1" 557 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4)) 558 : "r" (pte) : "memory"); 559 560 #else 561 /* Third case is 32-bit hash table in UP mode, we need to preserve 562 * the _PAGE_HASHPTE bit since we may not have invalidated the previous 563 * translation in the hash yet (done in a subsequent flush_tlb_xxx()) 564 * and see we need to keep track that this PTE needs invalidating 565 */ 566 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 567 | (pte_val(pte) & ~_PAGE_HASHPTE)); 568 #endif 569 } 570 571 /* 572 * Macro to mark a page protection value as "uncacheable". 573 */ 574 575 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \ 576 _PAGE_WRITETHRU) 577 578 #define pgprot_noncached pgprot_noncached 579 static inline pgprot_t pgprot_noncached(pgprot_t prot) 580 { 581 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 582 _PAGE_NO_CACHE | _PAGE_GUARDED); 583 } 584 585 #define pgprot_noncached_wc pgprot_noncached_wc 586 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 587 { 588 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 589 _PAGE_NO_CACHE); 590 } 591 592 #define pgprot_cached pgprot_cached 593 static inline pgprot_t pgprot_cached(pgprot_t prot) 594 { 595 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 596 _PAGE_COHERENT); 597 } 598 599 #define pgprot_cached_wthru pgprot_cached_wthru 600 static inline pgprot_t pgprot_cached_wthru(pgprot_t prot) 601 { 602 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 603 _PAGE_COHERENT | _PAGE_WRITETHRU); 604 } 605 606 #define pgprot_cached_noncoherent pgprot_cached_noncoherent 607 static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot) 608 { 609 return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL); 610 } 611 612 #define pgprot_writecombine pgprot_writecombine 613 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 614 { 615 return pgprot_noncached_wc(prot); 616 } 617 618 #endif /* !__ASSEMBLY__ */ 619 620 #endif /* _ASM_POWERPC_BOOK3S_32_PGTABLE_H */ 621