1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_32_PGTABLE_H 3 #define _ASM_POWERPC_BOOK3S_32_PGTABLE_H 4 5 #include <asm-generic/pgtable-nopmd.h> 6 7 #include <asm/book3s/32/hash.h> 8 9 /* And here we include common definitions */ 10 11 #define _PAGE_KERNEL_RO 0 12 #define _PAGE_KERNEL_ROX (_PAGE_EXEC) 13 #define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW) 14 #define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 15 16 #define _PAGE_HPTEFLAGS _PAGE_HASHPTE 17 18 #ifndef __ASSEMBLY__ 19 20 static inline bool pte_user(pte_t pte) 21 { 22 return pte_val(pte) & _PAGE_USER; 23 } 24 #endif /* __ASSEMBLY__ */ 25 26 /* 27 * Location of the PFN in the PTE. Most 32-bit platforms use the same 28 * as _PAGE_SHIFT here (ie, naturally aligned). 29 * Platform who don't just pre-define the value so we don't override it here. 30 */ 31 #define PTE_RPN_SHIFT (PAGE_SHIFT) 32 33 /* 34 * The mask covered by the RPN must be a ULL on 32-bit platforms with 35 * 64-bit PTEs. 36 */ 37 #ifdef CONFIG_PTE_64BIT 38 #define PTE_RPN_MASK (~((1ULL << PTE_RPN_SHIFT) - 1)) 39 #else 40 #define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1)) 41 #endif 42 43 /* 44 * _PAGE_CHG_MASK masks of bits that are to be preserved across 45 * pgprot changes. 46 */ 47 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HASHPTE | _PAGE_DIRTY | \ 48 _PAGE_ACCESSED | _PAGE_SPECIAL) 49 50 /* 51 * We define 2 sets of base prot bits, one for basic pages (ie, 52 * cacheable kernel and user pages) and one for non cacheable 53 * pages. We always set _PAGE_COHERENT when SMP is enabled or 54 * the processor might need it for DMA coherency. 55 */ 56 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 57 #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 58 59 /* 60 * Permission masks used to generate the __P and __S table. 61 * 62 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 63 * 64 * Write permissions imply read permissions for now. 65 */ 66 #define PAGE_NONE __pgprot(_PAGE_BASE) 67 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 68 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 69 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 70 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 71 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 72 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 73 74 /* Permission masks used for kernel mappings */ 75 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 76 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE) 77 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 78 _PAGE_NO_CACHE | _PAGE_GUARDED) 79 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 80 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 81 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 82 83 /* 84 * Protection used for kernel text. We want the debuggers to be able to 85 * set breakpoints anywhere, so don't write protect the kernel text 86 * on platforms where such control is possible. 87 */ 88 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\ 89 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 90 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 91 #else 92 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 93 #endif 94 95 /* Make modules code happy. We don't set RO yet */ 96 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 97 98 /* Advertise special mapping type for AGP */ 99 #define PAGE_AGP (PAGE_KERNEL_NC) 100 #define HAVE_PAGE_AGP 101 102 #define PTE_INDEX_SIZE PTE_SHIFT 103 #define PMD_INDEX_SIZE 0 104 #define PUD_INDEX_SIZE 0 105 #define PGD_INDEX_SIZE (32 - PGDIR_SHIFT) 106 107 #define PMD_CACHE_INDEX PMD_INDEX_SIZE 108 #define PUD_CACHE_INDEX PUD_INDEX_SIZE 109 110 #ifndef __ASSEMBLY__ 111 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) 112 #define PMD_TABLE_SIZE 0 113 #define PUD_TABLE_SIZE 0 114 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 115 #endif /* __ASSEMBLY__ */ 116 117 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 118 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 119 120 /* 121 * The normal case is that PTEs are 32-bits and we have a 1-page 122 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 123 * 124 * For any >32-bit physical address platform, we can use the following 125 * two level page table layout where the pgdir is 8KB and the MS 13 bits 126 * are an index to the second level table. The combined pgdir/pmd first 127 * level has 2048 entries and the second level has 512 64-bit PTE entries. 128 * -Matt 129 */ 130 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 131 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 132 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 133 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 134 135 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 136 137 #ifndef __ASSEMBLY__ 138 139 int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot); 140 141 #endif /* !__ASSEMBLY__ */ 142 143 /* 144 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary 145 * value (for now) on others, from where we can start layout kernel 146 * virtual space that goes below PKMAP and FIXMAP 147 */ 148 #include <asm/fixmap.h> 149 150 /* 151 * ioremap_bot starts at that address. Early ioremaps move down from there, 152 * until mem_init() at which point this becomes the top of the vmalloc 153 * and ioremap space 154 */ 155 #ifdef CONFIG_HIGHMEM 156 #define IOREMAP_TOP PKMAP_BASE 157 #else 158 #define IOREMAP_TOP FIXADDR_START 159 #endif 160 161 /* PPC32 shares vmalloc area with ioremap */ 162 #define IOREMAP_START VMALLOC_START 163 #define IOREMAP_END VMALLOC_END 164 165 /* 166 * Just any arbitrary offset to the start of the vmalloc VM area: the 167 * current 16MB value just means that there will be a 64MB "hole" after the 168 * physical memory until the kernel virtual memory starts. That means that 169 * any out-of-bounds memory accesses will hopefully be caught. 170 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 171 * area for the same reason. ;) 172 * 173 * We no longer map larger than phys RAM with the BATs so we don't have 174 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry 175 * about clashes between our early calls to ioremap() that start growing down 176 * from ioremap_base being run into the VM area allocations (growing upwards 177 * from VMALLOC_START). For this reason we have ioremap_bot to check when 178 * we actually run into our mappings setup in the early boot with the VM 179 * system. This really does become a problem for machines with good amounts 180 * of RAM. -- Cort 181 */ 182 #define VMALLOC_OFFSET (0x1000000) /* 16M */ 183 184 /* 185 * With CONFIG_STRICT_KERNEL_RWX, kernel segments are set NX. But when modules 186 * are used, NX cannot be set on VMALLOC space. So vmalloc VM space and linear 187 * memory shall not share segments. 188 */ 189 #if defined(CONFIG_STRICT_KERNEL_RWX) && defined(CONFIG_MODULES) 190 #define VMALLOC_START ((_ALIGN((long)high_memory, 256L << 20) + VMALLOC_OFFSET) & \ 191 ~(VMALLOC_OFFSET - 1)) 192 #else 193 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) 194 #endif 195 196 #ifdef CONFIG_KASAN_VMALLOC 197 #define VMALLOC_END _ALIGN_DOWN(ioremap_bot, PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT) 198 #else 199 #define VMALLOC_END ioremap_bot 200 #endif 201 202 #ifndef __ASSEMBLY__ 203 #include <linux/sched.h> 204 #include <linux/threads.h> 205 206 /* Bits to mask out from a PGD to get to the PUD page */ 207 #define PGD_MASKED_BITS 0 208 209 #define pte_ERROR(e) \ 210 pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \ 211 (unsigned long long)pte_val(e)) 212 #define pgd_ERROR(e) \ 213 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 214 /* 215 * Bits in a linux-style PTE. These match the bits in the 216 * (hardware-defined) PowerPC PTE as closely as possible. 217 */ 218 219 #define pte_clear(mm, addr, ptep) \ 220 do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0) 221 222 #define pmd_none(pmd) (!pmd_val(pmd)) 223 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) 224 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) 225 static inline void pmd_clear(pmd_t *pmdp) 226 { 227 *pmdp = __pmd(0); 228 } 229 230 231 /* 232 * When flushing the tlb entry for a page, we also need to flush the hash 233 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S. 234 */ 235 extern int flush_hash_pages(unsigned context, unsigned long va, 236 unsigned long pmdval, int count); 237 238 /* Add an HPTE to the hash table */ 239 extern void add_hash_page(unsigned context, unsigned long va, 240 unsigned long pmdval); 241 242 /* Flush an entry from the TLB/hash table */ 243 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep, 244 unsigned long address); 245 246 /* 247 * PTE updates. This function is called whenever an existing 248 * valid PTE is updated. This does -not- include set_pte_at() 249 * which nowadays only sets a new PTE. 250 * 251 * Depending on the type of MMU, we may need to use atomic updates 252 * and the PTE may be either 32 or 64 bit wide. In the later case, 253 * when using atomic updates, only the low part of the PTE is 254 * accessed atomically. 255 * 256 * In addition, on 44x, we also maintain a global flag indicating 257 * that an executable user mapping was modified, which is needed 258 * to properly flush the virtually tagged instruction cache of 259 * those implementations. 260 */ 261 #ifndef CONFIG_PTE_64BIT 262 static inline unsigned long pte_update(pte_t *p, 263 unsigned long clr, 264 unsigned long set) 265 { 266 unsigned long old, tmp; 267 268 __asm__ __volatile__("\ 269 1: lwarx %0,0,%3\n\ 270 andc %1,%0,%4\n\ 271 or %1,%1,%5\n" 272 " stwcx. %1,0,%3\n\ 273 bne- 1b" 274 : "=&r" (old), "=&r" (tmp), "=m" (*p) 275 : "r" (p), "r" (clr), "r" (set), "m" (*p) 276 : "cc" ); 277 278 return old; 279 } 280 #else /* CONFIG_PTE_64BIT */ 281 static inline unsigned long long pte_update(pte_t *p, 282 unsigned long clr, 283 unsigned long set) 284 { 285 unsigned long long old; 286 unsigned long tmp; 287 288 __asm__ __volatile__("\ 289 1: lwarx %L0,0,%4\n\ 290 lwzx %0,0,%3\n\ 291 andc %1,%L0,%5\n\ 292 or %1,%1,%6\n" 293 " stwcx. %1,0,%4\n\ 294 bne- 1b" 295 : "=&r" (old), "=&r" (tmp), "=m" (*p) 296 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) 297 : "cc" ); 298 299 return old; 300 } 301 #endif /* CONFIG_PTE_64BIT */ 302 303 /* 304 * 2.6 calls this without flushing the TLB entry; this is wrong 305 * for our hash-based implementation, we fix that up here. 306 */ 307 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 308 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep) 309 { 310 unsigned long old; 311 old = pte_update(ptep, _PAGE_ACCESSED, 0); 312 if (old & _PAGE_HASHPTE) { 313 unsigned long ptephys = __pa(ptep) & PAGE_MASK; 314 flush_hash_pages(context, addr, ptephys, 1); 315 } 316 return (old & _PAGE_ACCESSED) != 0; 317 } 318 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 319 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep) 320 321 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 322 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 323 pte_t *ptep) 324 { 325 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); 326 } 327 328 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 329 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 330 pte_t *ptep) 331 { 332 pte_update(ptep, _PAGE_RW, 0); 333 } 334 335 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 336 pte_t *ptep, pte_t entry, 337 unsigned long address, 338 int psize) 339 { 340 unsigned long set = pte_val(entry) & 341 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); 342 343 pte_update(ptep, 0, set); 344 345 flush_tlb_page(vma, address); 346 } 347 348 #define __HAVE_ARCH_PTE_SAME 349 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) 350 351 #define pmd_page_vaddr(pmd) \ 352 ((unsigned long)__va(pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1))) 353 #define pmd_page(pmd) \ 354 pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 355 356 /* to find an entry in a kernel page-table-directory */ 357 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 358 359 /* to find an entry in a page-table-directory */ 360 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 361 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 362 363 /* Find an entry in the third-level page table.. */ 364 #define pte_index(address) \ 365 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 366 #define pte_offset_kernel(dir, addr) \ 367 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr)) 368 #define pte_offset_map(dir, addr) pte_offset_kernel((dir), (addr)) 369 static inline void pte_unmap(pte_t *pte) { } 370 371 /* 372 * Encode and decode a swap entry. 373 * Note that the bits we use in a PTE for representing a swap entry 374 * must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used). 375 * -- paulus 376 */ 377 #define __swp_type(entry) ((entry).val & 0x1f) 378 #define __swp_offset(entry) ((entry).val >> 5) 379 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) 380 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) 381 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) 382 383 /* Generic accessors to PTE bits */ 384 static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);} 385 static inline int pte_read(pte_t pte) { return 1; } 386 static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); } 387 static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); } 388 static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); } 389 static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; } 390 static inline bool pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 391 392 static inline int pte_present(pte_t pte) 393 { 394 return pte_val(pte) & _PAGE_PRESENT; 395 } 396 397 static inline bool pte_hw_valid(pte_t pte) 398 { 399 return pte_val(pte) & _PAGE_PRESENT; 400 } 401 402 static inline bool pte_hashpte(pte_t pte) 403 { 404 return !!(pte_val(pte) & _PAGE_HASHPTE); 405 } 406 407 static inline bool pte_ci(pte_t pte) 408 { 409 return !!(pte_val(pte) & _PAGE_NO_CACHE); 410 } 411 412 /* 413 * We only find page table entry in the last level 414 * Hence no need for other accessors 415 */ 416 #define pte_access_permitted pte_access_permitted 417 static inline bool pte_access_permitted(pte_t pte, bool write) 418 { 419 /* 420 * A read-only access is controlled by _PAGE_USER bit. 421 * We have _PAGE_READ set for WRITE and EXECUTE 422 */ 423 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 424 return false; 425 426 if (write && !pte_write(pte)) 427 return false; 428 429 return true; 430 } 431 432 /* Conversion functions: convert a page and protection to a page entry, 433 * and a page entry and page directory to the page they refer to. 434 * 435 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 436 * long for now. 437 */ 438 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 439 { 440 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) | 441 pgprot_val(pgprot)); 442 } 443 444 static inline unsigned long pte_pfn(pte_t pte) 445 { 446 return pte_val(pte) >> PTE_RPN_SHIFT; 447 } 448 449 /* Generic modifiers for PTE bits */ 450 static inline pte_t pte_wrprotect(pte_t pte) 451 { 452 return __pte(pte_val(pte) & ~_PAGE_RW); 453 } 454 455 static inline pte_t pte_exprotect(pte_t pte) 456 { 457 return __pte(pte_val(pte) & ~_PAGE_EXEC); 458 } 459 460 static inline pte_t pte_mkclean(pte_t pte) 461 { 462 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 463 } 464 465 static inline pte_t pte_mkold(pte_t pte) 466 { 467 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 468 } 469 470 static inline pte_t pte_mkexec(pte_t pte) 471 { 472 return __pte(pte_val(pte) | _PAGE_EXEC); 473 } 474 475 static inline pte_t pte_mkpte(pte_t pte) 476 { 477 return pte; 478 } 479 480 static inline pte_t pte_mkwrite(pte_t pte) 481 { 482 return __pte(pte_val(pte) | _PAGE_RW); 483 } 484 485 static inline pte_t pte_mkdirty(pte_t pte) 486 { 487 return __pte(pte_val(pte) | _PAGE_DIRTY); 488 } 489 490 static inline pte_t pte_mkyoung(pte_t pte) 491 { 492 return __pte(pte_val(pte) | _PAGE_ACCESSED); 493 } 494 495 static inline pte_t pte_mkspecial(pte_t pte) 496 { 497 return __pte(pte_val(pte) | _PAGE_SPECIAL); 498 } 499 500 static inline pte_t pte_mkhuge(pte_t pte) 501 { 502 return pte; 503 } 504 505 static inline pte_t pte_mkprivileged(pte_t pte) 506 { 507 return __pte(pte_val(pte) & ~_PAGE_USER); 508 } 509 510 static inline pte_t pte_mkuser(pte_t pte) 511 { 512 return __pte(pte_val(pte) | _PAGE_USER); 513 } 514 515 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 516 { 517 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 518 } 519 520 521 522 /* This low level function performs the actual PTE insertion 523 * Setting the PTE depends on the MMU type and other factors. It's 524 * an horrible mess that I'm not going to try to clean up now but 525 * I'm keeping it in one place rather than spread around 526 */ 527 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 528 pte_t *ptep, pte_t pte, int percpu) 529 { 530 #if defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT) 531 /* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the 532 * helper pte_update() which does an atomic update. We need to do that 533 * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a 534 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving 535 * the hash bits instead (ie, same as the non-SMP case) 536 */ 537 if (percpu) 538 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 539 | (pte_val(pte) & ~_PAGE_HASHPTE)); 540 else 541 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte)); 542 543 #elif defined(CONFIG_PTE_64BIT) 544 /* Second case is 32-bit with 64-bit PTE. In this case, we 545 * can just store as long as we do the two halves in the right order 546 * with a barrier in between. This is possible because we take care, 547 * in the hash code, to pre-invalidate if the PTE was already hashed, 548 * which synchronizes us with any concurrent invalidation. 549 * In the percpu case, we also fallback to the simple update preserving 550 * the hash bits 551 */ 552 if (percpu) { 553 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 554 | (pte_val(pte) & ~_PAGE_HASHPTE)); 555 return; 556 } 557 if (pte_val(*ptep) & _PAGE_HASHPTE) 558 flush_hash_entry(mm, ptep, addr); 559 __asm__ __volatile__("\ 560 stw%U0%X0 %2,%0\n\ 561 eieio\n\ 562 stw%U0%X0 %L2,%1" 563 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4)) 564 : "r" (pte) : "memory"); 565 566 #else 567 /* Third case is 32-bit hash table in UP mode, we need to preserve 568 * the _PAGE_HASHPTE bit since we may not have invalidated the previous 569 * translation in the hash yet (done in a subsequent flush_tlb_xxx()) 570 * and see we need to keep track that this PTE needs invalidating 571 */ 572 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 573 | (pte_val(pte) & ~_PAGE_HASHPTE)); 574 #endif 575 } 576 577 /* 578 * Macro to mark a page protection value as "uncacheable". 579 */ 580 581 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \ 582 _PAGE_WRITETHRU) 583 584 #define pgprot_noncached pgprot_noncached 585 static inline pgprot_t pgprot_noncached(pgprot_t prot) 586 { 587 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 588 _PAGE_NO_CACHE | _PAGE_GUARDED); 589 } 590 591 #define pgprot_noncached_wc pgprot_noncached_wc 592 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 593 { 594 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 595 _PAGE_NO_CACHE); 596 } 597 598 #define pgprot_cached pgprot_cached 599 static inline pgprot_t pgprot_cached(pgprot_t prot) 600 { 601 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 602 _PAGE_COHERENT); 603 } 604 605 #define pgprot_cached_wthru pgprot_cached_wthru 606 static inline pgprot_t pgprot_cached_wthru(pgprot_t prot) 607 { 608 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 609 _PAGE_COHERENT | _PAGE_WRITETHRU); 610 } 611 612 #define pgprot_cached_noncoherent pgprot_cached_noncoherent 613 static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot) 614 { 615 return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL); 616 } 617 618 #define pgprot_writecombine pgprot_writecombine 619 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 620 { 621 return pgprot_noncached_wc(prot); 622 } 623 624 #endif /* !__ASSEMBLY__ */ 625 626 #endif /* _ASM_POWERPC_BOOK3S_32_PGTABLE_H */ 627