1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ 3 #define _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ 4 5 /* 6 * 32-bit hash table MMU support 7 */ 8 9 /* 10 * BATs 11 */ 12 13 #include <asm/page.h> 14 15 /* Block size masks */ 16 #define BL_128K 0x000 17 #define BL_256K 0x001 18 #define BL_512K 0x003 19 #define BL_1M 0x007 20 #define BL_2M 0x00F 21 #define BL_4M 0x01F 22 #define BL_8M 0x03F 23 #define BL_16M 0x07F 24 #define BL_32M 0x0FF 25 #define BL_64M 0x1FF 26 #define BL_128M 0x3FF 27 #define BL_256M 0x7FF 28 29 /* BAT Access Protection */ 30 #define BPP_XX 0x00 /* No access */ 31 #define BPP_RX 0x01 /* Read only */ 32 #define BPP_RW 0x02 /* Read/write */ 33 34 #ifndef __ASSEMBLY__ 35 /* Contort a phys_addr_t into the right format/bits for a BAT */ 36 #ifdef CONFIG_PHYS_64BIT 37 #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \ 38 ((x & 0x0000000e00000000ULL) >> 24) | \ 39 ((x & 0x0000000100000000ULL) >> 30))) 40 #define PHYS_BAT_ADDR(x) (((u64)(x) & 0x00000000fffe0000ULL) | \ 41 (((u64)(x) << 24) & 0x0000000e00000000ULL) | \ 42 (((u64)(x) << 30) & 0x0000000100000000ULL)) 43 #else 44 #define BAT_PHYS_ADDR(x) (x) 45 #define PHYS_BAT_ADDR(x) ((x) & 0xfffe0000) 46 #endif 47 48 struct ppc_bat { 49 u32 batu; 50 u32 batl; 51 }; 52 53 typedef pte_t *pgtable_t; 54 #endif /* !__ASSEMBLY__ */ 55 56 /* 57 * Hash table 58 */ 59 60 /* Values for PP (assumes Ks=0, Kp=1) */ 61 #define PP_RWXX 0 /* Supervisor read/write, User none */ 62 #define PP_RWRX 1 /* Supervisor read/write, User read */ 63 #define PP_RWRW 2 /* Supervisor read/write, User read/write */ 64 #define PP_RXRX 3 /* Supervisor read, User read */ 65 66 #ifndef __ASSEMBLY__ 67 68 /* 69 * Hardware Page Table Entry 70 * Note that the xpn and x bitfields are used only by processors that 71 * support extended addressing; otherwise, those bits are reserved. 72 */ 73 struct hash_pte { 74 unsigned long v:1; /* Entry is valid */ 75 unsigned long vsid:24; /* Virtual segment identifier */ 76 unsigned long h:1; /* Hash algorithm indicator */ 77 unsigned long api:6; /* Abbreviated page index */ 78 unsigned long rpn:20; /* Real (physical) page number */ 79 unsigned long xpn:3; /* Real page number bits 0-2, optional */ 80 unsigned long r:1; /* Referenced */ 81 unsigned long c:1; /* Changed */ 82 unsigned long w:1; /* Write-thru cache mode */ 83 unsigned long i:1; /* Cache inhibited */ 84 unsigned long m:1; /* Memory coherence */ 85 unsigned long g:1; /* Guarded */ 86 unsigned long x:1; /* Real page number bit 3, optional */ 87 unsigned long pp:2; /* Page protection */ 88 }; 89 90 typedef struct { 91 unsigned long id; 92 unsigned long vdso_base; 93 } mm_context_t; 94 95 void update_bats(void); 96 97 /* patch sites */ 98 extern s32 patch__hash_page_A0, patch__hash_page_A1, patch__hash_page_A2; 99 extern s32 patch__hash_page_B, patch__hash_page_C; 100 extern s32 patch__flush_hash_A0, patch__flush_hash_A1, patch__flush_hash_A2; 101 extern s32 patch__flush_hash_B; 102 103 #endif /* !__ASSEMBLY__ */ 104 105 /* We happily ignore the smaller BATs on 601, we don't actually use 106 * those definitions on hash32 at the moment anyway 107 */ 108 #define mmu_virtual_psize MMU_PAGE_4K 109 #define mmu_linear_psize MMU_PAGE_256M 110 111 #endif /* _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ */ 112