1 /* 2 * PowerPC atomic bit operations. 3 * 4 * Merged version by David Gibson <david@gibson.dropbear.id.au>. 5 * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don 6 * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard. They 7 * originally took it from the ppc32 code. 8 * 9 * Within a word, bits are numbered LSB first. Lot's of places make 10 * this assumption by directly testing bits with (val & (1<<nr)). 11 * This can cause confusion for large (> 1 word) bitmaps on a 12 * big-endian system because, unlike little endian, the number of each 13 * bit depends on the word size. 14 * 15 * The bitop functions are defined to work on unsigned longs, so for a 16 * ppc64 system the bits end up numbered: 17 * |63..............0|127............64|191...........128|255...........192| 18 * and on ppc32: 19 * |31.....0|63....32|95....64|127...96|159..128|191..160|223..192|255..224| 20 * 21 * There are a few little-endian macros used mostly for filesystem 22 * bitmaps, these work on similar bit arrays layouts, but 23 * byte-oriented: 24 * |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56| 25 * 26 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit 27 * number field needs to be reversed compared to the big-endian bit 28 * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b). 29 * 30 * This program is free software; you can redistribute it and/or 31 * modify it under the terms of the GNU General Public License 32 * as published by the Free Software Foundation; either version 33 * 2 of the License, or (at your option) any later version. 34 */ 35 36 #ifndef _ASM_POWERPC_BITOPS_H 37 #define _ASM_POWERPC_BITOPS_H 38 39 #ifdef __KERNEL__ 40 41 #ifndef _LINUX_BITOPS_H 42 #error only <linux/bitops.h> can be included directly 43 #endif 44 45 #include <linux/compiler.h> 46 #include <asm/asm-compat.h> 47 #include <asm/synch.h> 48 #include <asm/asm-405.h> 49 50 /* PPC bit number conversion */ 51 #define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be)) 52 #define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit)) 53 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) 54 55 /* Put a PPC bit into a "normal" bit position */ 56 #define PPC_BITEXTRACT(bits, ppc_bit, dst_bit) \ 57 ((((bits) >> PPC_BITLSHIFT(ppc_bit)) & 1) << (dst_bit)) 58 59 #define PPC_BITLSHIFT32(be) (32 - 1 - (be)) 60 #define PPC_BIT32(bit) (1UL << PPC_BITLSHIFT32(bit)) 61 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be))|PPC_BIT32(bs)) 62 63 #define PPC_BITLSHIFT8(be) (8 - 1 - (be)) 64 #define PPC_BIT8(bit) (1UL << PPC_BITLSHIFT8(bit)) 65 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be))|PPC_BIT8(bs)) 66 67 #include <asm/barrier.h> 68 69 /* Macro for generating the ***_bits() functions */ 70 #define DEFINE_BITOP(fn, op, prefix) \ 71 static __inline__ void fn(unsigned long mask, \ 72 volatile unsigned long *_p) \ 73 { \ 74 unsigned long old; \ 75 unsigned long *p = (unsigned long *)_p; \ 76 __asm__ __volatile__ ( \ 77 prefix \ 78 "1:" PPC_LLARX(%0,0,%3,0) "\n" \ 79 stringify_in_c(op) "%0,%0,%2\n" \ 80 PPC405_ERR77(0,%3) \ 81 PPC_STLCX "%0,0,%3\n" \ 82 "bne- 1b\n" \ 83 : "=&r" (old), "+m" (*p) \ 84 : "r" (mask), "r" (p) \ 85 : "cc", "memory"); \ 86 } 87 88 DEFINE_BITOP(set_bits, or, "") 89 DEFINE_BITOP(clear_bits, andc, "") 90 DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER) 91 DEFINE_BITOP(change_bits, xor, "") 92 93 static __inline__ void set_bit(int nr, volatile unsigned long *addr) 94 { 95 set_bits(BIT_MASK(nr), addr + BIT_WORD(nr)); 96 } 97 98 static __inline__ void clear_bit(int nr, volatile unsigned long *addr) 99 { 100 clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr)); 101 } 102 103 static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr) 104 { 105 clear_bits_unlock(BIT_MASK(nr), addr + BIT_WORD(nr)); 106 } 107 108 static __inline__ void change_bit(int nr, volatile unsigned long *addr) 109 { 110 change_bits(BIT_MASK(nr), addr + BIT_WORD(nr)); 111 } 112 113 /* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output 114 * operands. */ 115 #define DEFINE_TESTOP(fn, op, prefix, postfix, eh) \ 116 static __inline__ unsigned long fn( \ 117 unsigned long mask, \ 118 volatile unsigned long *_p) \ 119 { \ 120 unsigned long old, t; \ 121 unsigned long *p = (unsigned long *)_p; \ 122 __asm__ __volatile__ ( \ 123 prefix \ 124 "1:" PPC_LLARX(%0,0,%3,eh) "\n" \ 125 stringify_in_c(op) "%1,%0,%2\n" \ 126 PPC405_ERR77(0,%3) \ 127 PPC_STLCX "%1,0,%3\n" \ 128 "bne- 1b\n" \ 129 postfix \ 130 : "=&r" (old), "=&r" (t) \ 131 : "r" (mask), "r" (p) \ 132 : "cc", "memory"); \ 133 return (old & mask); \ 134 } 135 136 DEFINE_TESTOP(test_and_set_bits, or, PPC_ATOMIC_ENTRY_BARRIER, 137 PPC_ATOMIC_EXIT_BARRIER, 0) 138 DEFINE_TESTOP(test_and_set_bits_lock, or, "", 139 PPC_ACQUIRE_BARRIER, 1) 140 DEFINE_TESTOP(test_and_clear_bits, andc, PPC_ATOMIC_ENTRY_BARRIER, 141 PPC_ATOMIC_EXIT_BARRIER, 0) 142 DEFINE_TESTOP(test_and_change_bits, xor, PPC_ATOMIC_ENTRY_BARRIER, 143 PPC_ATOMIC_EXIT_BARRIER, 0) 144 145 static __inline__ int test_and_set_bit(unsigned long nr, 146 volatile unsigned long *addr) 147 { 148 return test_and_set_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0; 149 } 150 151 static __inline__ int test_and_set_bit_lock(unsigned long nr, 152 volatile unsigned long *addr) 153 { 154 return test_and_set_bits_lock(BIT_MASK(nr), 155 addr + BIT_WORD(nr)) != 0; 156 } 157 158 static __inline__ int test_and_clear_bit(unsigned long nr, 159 volatile unsigned long *addr) 160 { 161 return test_and_clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0; 162 } 163 164 static __inline__ int test_and_change_bit(unsigned long nr, 165 volatile unsigned long *addr) 166 { 167 return test_and_change_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0; 168 } 169 170 #ifdef CONFIG_PPC64 171 static __inline__ unsigned long clear_bit_unlock_return_word(int nr, 172 volatile unsigned long *addr) 173 { 174 unsigned long old, t; 175 unsigned long *p = (unsigned long *)addr + BIT_WORD(nr); 176 unsigned long mask = BIT_MASK(nr); 177 178 __asm__ __volatile__ ( 179 PPC_RELEASE_BARRIER 180 "1:" PPC_LLARX(%0,0,%3,0) "\n" 181 "andc %1,%0,%2\n" 182 PPC405_ERR77(0,%3) 183 PPC_STLCX "%1,0,%3\n" 184 "bne- 1b\n" 185 : "=&r" (old), "=&r" (t) 186 : "r" (mask), "r" (p) 187 : "cc", "memory"); 188 189 return old; 190 } 191 192 /* This is a special function for mm/filemap.c */ 193 #define clear_bit_unlock_is_negative_byte(nr, addr) \ 194 (clear_bit_unlock_return_word(nr, addr) & BIT_MASK(PG_waiters)) 195 196 #endif /* CONFIG_PPC64 */ 197 198 #include <asm-generic/bitops/non-atomic.h> 199 200 static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr) 201 { 202 __asm__ __volatile__(PPC_RELEASE_BARRIER "" ::: "memory"); 203 __clear_bit(nr, addr); 204 } 205 206 /* 207 * Return the zero-based bit position (LE, not IBM bit numbering) of 208 * the most significant 1-bit in a double word. 209 */ 210 #define __ilog2(x) ilog2(x) 211 212 #include <asm-generic/bitops/ffz.h> 213 214 #include <asm-generic/bitops/builtin-__ffs.h> 215 216 #include <asm-generic/bitops/builtin-ffs.h> 217 218 /* 219 * fls: find last (most-significant) bit set. 220 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. 221 */ 222 static __inline__ int fls(unsigned int x) 223 { 224 return 32 - __builtin_clz(x); 225 } 226 227 #include <asm-generic/bitops/builtin-__fls.h> 228 229 static __inline__ int fls64(__u64 x) 230 { 231 return 64 - __builtin_clzll(x); 232 } 233 234 #ifdef CONFIG_PPC64 235 unsigned int __arch_hweight8(unsigned int w); 236 unsigned int __arch_hweight16(unsigned int w); 237 unsigned int __arch_hweight32(unsigned int w); 238 unsigned long __arch_hweight64(__u64 w); 239 #include <asm-generic/bitops/const_hweight.h> 240 #else 241 #include <asm-generic/bitops/hweight.h> 242 #endif 243 244 #include <asm-generic/bitops/find.h> 245 246 /* Little-endian versions */ 247 #include <asm-generic/bitops/le.h> 248 249 /* Bitmap functions for the ext2 filesystem */ 250 251 #include <asm-generic/bitops/ext2-atomic-setbit.h> 252 253 #include <asm-generic/bitops/sched.h> 254 255 #endif /* __KERNEL__ */ 256 257 #endif /* _ASM_POWERPC_BITOPS_H */ 258