1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> 4 */ 5 #ifndef _ASM_POWERPC_BARRIER_H 6 #define _ASM_POWERPC_BARRIER_H 7 8 #include <asm/asm-const.h> 9 10 #ifndef __ASSEMBLY__ 11 #include <asm/ppc-opcode.h> 12 #endif 13 14 /* 15 * Memory barrier. 16 * The sync instruction guarantees that all memory accesses initiated 17 * by this processor have been performed (with respect to all other 18 * mechanisms that access memory). The eieio instruction is a barrier 19 * providing an ordering (separately) for (a) cacheable stores and (b) 20 * loads and stores to non-cacheable memory (e.g. I/O devices). 21 * 22 * mb() prevents loads and stores being reordered across this point. 23 * rmb() prevents loads being reordered across this point. 24 * wmb() prevents stores being reordered across this point. 25 * 26 * *mb() variants without smp_ prefix must order all types of memory 27 * operations with one another. sync is the only instruction sufficient 28 * to do this. 29 * 30 * For the smp_ barriers, ordering is for cacheable memory operations 31 * only. We have to use the sync instruction for smp_mb(), since lwsync 32 * doesn't order loads with respect to previous stores. Lwsync can be 33 * used for smp_rmb() and smp_wmb(). 34 * 35 * However, on CPUs that don't support lwsync, lwsync actually maps to a 36 * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio. 37 */ 38 #define mb() __asm__ __volatile__ ("sync" : : : "memory") 39 #define rmb() __asm__ __volatile__ ("sync" : : : "memory") 40 #define wmb() __asm__ __volatile__ ("sync" : : : "memory") 41 42 /* The sub-arch has lwsync */ 43 #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC) 44 # define SMPWMB LWSYNC 45 #else 46 # define SMPWMB eieio 47 #endif 48 49 /* clang defines this macro for a builtin, which will not work with runtime patching */ 50 #undef __lwsync 51 #define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory") 52 #define dma_rmb() __lwsync() 53 #define dma_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory") 54 55 #define __smp_lwsync() __lwsync() 56 57 #define __smp_mb() mb() 58 #define __smp_rmb() __lwsync() 59 #define __smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory") 60 61 /* 62 * This is a barrier which prevents following instructions from being 63 * started until the value of the argument x is known. For example, if 64 * x is a variable loaded from memory, this prevents following 65 * instructions from being executed until the load has been performed. 66 */ 67 #define data_barrier(x) \ 68 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory"); 69 70 #define __smp_store_release(p, v) \ 71 do { \ 72 compiletime_assert_atomic_type(*p); \ 73 __smp_lwsync(); \ 74 WRITE_ONCE(*p, v); \ 75 } while (0) 76 77 #define __smp_load_acquire(p) \ 78 ({ \ 79 typeof(*p) ___p1 = READ_ONCE(*p); \ 80 compiletime_assert_atomic_type(*p); \ 81 __smp_lwsync(); \ 82 ___p1; \ 83 }) 84 85 #ifdef CONFIG_PPC_BOOK3S_64 86 #define NOSPEC_BARRIER_SLOT nop 87 #elif defined(CONFIG_PPC_FSL_BOOK3E) 88 #define NOSPEC_BARRIER_SLOT nop; nop 89 #endif 90 91 #ifdef CONFIG_PPC_BARRIER_NOSPEC 92 /* 93 * Prevent execution of subsequent instructions until preceding branches have 94 * been fully resolved and are no longer executing speculatively. 95 */ 96 #define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; NOSPEC_BARRIER_SLOT 97 98 // This also acts as a compiler barrier due to the memory clobber. 99 #define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory") 100 101 #else /* !CONFIG_PPC_BARRIER_NOSPEC */ 102 #define barrier_nospec_asm 103 #define barrier_nospec() 104 #endif /* CONFIG_PPC_BARRIER_NOSPEC */ 105 106 /* 107 * pmem_wmb() ensures that all stores for which the modification 108 * are written to persistent storage by preceding dcbfps/dcbstps 109 * instructions have updated persistent storage before any data 110 * access or data transfer caused by subsequent instructions is 111 * initiated. 112 */ 113 #define pmem_wmb() __asm__ __volatile__(PPC_PHWSYNC ::: "memory") 114 115 #include <asm-generic/barrier.h> 116 117 #endif /* _ASM_POWERPC_BARRIER_H */ 118