1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> 4 */ 5 #ifndef _ASM_POWERPC_BARRIER_H 6 #define _ASM_POWERPC_BARRIER_H 7 8 /* 9 * Memory barrier. 10 * The sync instruction guarantees that all memory accesses initiated 11 * by this processor have been performed (with respect to all other 12 * mechanisms that access memory). The eieio instruction is a barrier 13 * providing an ordering (separately) for (a) cacheable stores and (b) 14 * loads and stores to non-cacheable memory (e.g. I/O devices). 15 * 16 * mb() prevents loads and stores being reordered across this point. 17 * rmb() prevents loads being reordered across this point. 18 * wmb() prevents stores being reordered across this point. 19 * read_barrier_depends() prevents data-dependent loads being reordered 20 * across this point (nop on PPC). 21 * 22 * *mb() variants without smp_ prefix must order all types of memory 23 * operations with one another. sync is the only instruction sufficient 24 * to do this. 25 * 26 * For the smp_ barriers, ordering is for cacheable memory operations 27 * only. We have to use the sync instruction for smp_mb(), since lwsync 28 * doesn't order loads with respect to previous stores. Lwsync can be 29 * used for smp_rmb() and smp_wmb(). 30 * 31 * However, on CPUs that don't support lwsync, lwsync actually maps to a 32 * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio. 33 */ 34 #define mb() __asm__ __volatile__ ("sync" : : : "memory") 35 #define rmb() __asm__ __volatile__ ("sync" : : : "memory") 36 #define wmb() __asm__ __volatile__ ("sync" : : : "memory") 37 38 /* The sub-arch has lwsync */ 39 #if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC) 40 # define SMPWMB LWSYNC 41 #else 42 # define SMPWMB eieio 43 #endif 44 45 #define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory") 46 #define dma_rmb() __lwsync() 47 #define dma_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory") 48 49 #define __smp_lwsync() __lwsync() 50 51 #define __smp_mb() mb() 52 #define __smp_rmb() __lwsync() 53 #define __smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory") 54 55 /* 56 * This is a barrier which prevents following instructions from being 57 * started until the value of the argument x is known. For example, if 58 * x is a variable loaded from memory, this prevents following 59 * instructions from being executed until the load has been performed. 60 */ 61 #define data_barrier(x) \ 62 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory"); 63 64 #define __smp_store_release(p, v) \ 65 do { \ 66 compiletime_assert_atomic_type(*p); \ 67 __smp_lwsync(); \ 68 WRITE_ONCE(*p, v); \ 69 } while (0) 70 71 #define __smp_load_acquire(p) \ 72 ({ \ 73 typeof(*p) ___p1 = READ_ONCE(*p); \ 74 compiletime_assert_atomic_type(*p); \ 75 __smp_lwsync(); \ 76 ___p1; \ 77 }) 78 79 #ifdef CONFIG_PPC_BOOK3S_64 80 /* 81 * Prevent execution of subsequent instructions until preceding branches have 82 * been fully resolved and are no longer executing speculatively. 83 */ 84 #define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; nop 85 86 // This also acts as a compiler barrier due to the memory clobber. 87 #define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory") 88 89 #else /* !CONFIG_PPC_BOOK3S_64 */ 90 #define barrier_nospec_asm 91 #define barrier_nospec() 92 #endif 93 94 #include <asm-generic/barrier.h> 95 96 #endif /* _ASM_POWERPC_BARRIER_H */ 97