1/* 2 * TQM8548 Device Tree Source 3 * 4 * Copyright 2006 Freescale Semiconductor Inc. 5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13/dts-v1/; 14 15/ { 16 model = "tqc,tqm8548"; 17 compatible = "tqc,tqm8548"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 aliases { 22 ethernet0 = &enet0; 23 ethernet1 = &enet1; 24 ethernet2 = &enet2; 25 ethernet3 = &enet3; 26 27 serial0 = &serial0; 28 serial1 = &serial1; 29 pci0 = &pci0; 30 pci1 = &pci1; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 PowerPC,8548@0 { 38 device_type = "cpu"; 39 reg = <0>; 40 d-cache-line-size = <32>; // 32 bytes 41 i-cache-line-size = <32>; // 32 bytes 42 d-cache-size = <0x8000>; // L1, 32K 43 i-cache-size = <0x8000>; // L1, 32K 44 next-level-cache = <&L2>; 45 }; 46 }; 47 48 memory { 49 device_type = "memory"; 50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot 51 }; 52 53 soc8548@a0000000 { 54 #address-cells = <1>; 55 #size-cells = <1>; 56 device_type = "soc"; 57 ranges = <0x0 0xa0000000 0x100000>; 58 reg = <0xa0000000 0x1000>; // CCSRBAR 59 bus-frequency = <0>; 60 61 memory-controller@2000 { 62 compatible = "fsl,mpc8548-memory-controller"; 63 reg = <0x2000 0x1000>; 64 interrupt-parent = <&mpic>; 65 interrupts = <18 2>; 66 }; 67 68 L2: l2-cache-controller@20000 { 69 compatible = "fsl,mpc8548-l2-cache-controller"; 70 reg = <0x20000 0x1000>; 71 cache-line-size = <32>; // 32 bytes 72 cache-size = <0x80000>; // L2, 512K 73 interrupt-parent = <&mpic>; 74 interrupts = <16 2>; 75 }; 76 77 i2c@3000 { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 cell-index = <0>; 81 compatible = "fsl-i2c"; 82 reg = <0x3000 0x100>; 83 interrupts = <43 2>; 84 interrupt-parent = <&mpic>; 85 dfsrr; 86 }; 87 88 i2c@3100 { 89 #address-cells = <1>; 90 #size-cells = <0>; 91 cell-index = <1>; 92 compatible = "fsl-i2c"; 93 reg = <0x3100 0x100>; 94 interrupts = <43 2>; 95 interrupt-parent = <&mpic>; 96 dfsrr; 97 }; 98 99 dma@21300 { 100 #address-cells = <1>; 101 #size-cells = <1>; 102 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; 103 reg = <0x21300 0x4>; 104 ranges = <0x0 0x21100 0x200>; 105 cell-index = <0>; 106 dma-channel@0 { 107 compatible = "fsl,mpc8548-dma-channel", 108 "fsl,eloplus-dma-channel"; 109 reg = <0x0 0x80>; 110 cell-index = <0>; 111 interrupt-parent = <&mpic>; 112 interrupts = <20 2>; 113 }; 114 dma-channel@80 { 115 compatible = "fsl,mpc8548-dma-channel", 116 "fsl,eloplus-dma-channel"; 117 reg = <0x80 0x80>; 118 cell-index = <1>; 119 interrupt-parent = <&mpic>; 120 interrupts = <21 2>; 121 }; 122 dma-channel@100 { 123 compatible = "fsl,mpc8548-dma-channel", 124 "fsl,eloplus-dma-channel"; 125 reg = <0x100 0x80>; 126 cell-index = <2>; 127 interrupt-parent = <&mpic>; 128 interrupts = <22 2>; 129 }; 130 dma-channel@180 { 131 compatible = "fsl,mpc8548-dma-channel", 132 "fsl,eloplus-dma-channel"; 133 reg = <0x180 0x80>; 134 cell-index = <3>; 135 interrupt-parent = <&mpic>; 136 interrupts = <23 2>; 137 }; 138 }; 139 140 mdio@24520 { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 compatible = "fsl,gianfar-mdio"; 144 reg = <0x24520 0x20>; 145 146 phy1: ethernet-phy@0 { 147 interrupt-parent = <&mpic>; 148 interrupts = <8 1>; 149 reg = <1>; 150 device_type = "ethernet-phy"; 151 }; 152 phy2: ethernet-phy@1 { 153 interrupt-parent = <&mpic>; 154 interrupts = <8 1>; 155 reg = <2>; 156 device_type = "ethernet-phy"; 157 }; 158 phy3: ethernet-phy@3 { 159 interrupt-parent = <&mpic>; 160 interrupts = <8 1>; 161 reg = <3>; 162 device_type = "ethernet-phy"; 163 }; 164 phy4: ethernet-phy@4 { 165 interrupt-parent = <&mpic>; 166 interrupts = <8 1>; 167 reg = <4>; 168 device_type = "ethernet-phy"; 169 }; 170 phy5: ethernet-phy@5 { 171 interrupt-parent = <&mpic>; 172 interrupts = <8 1>; 173 reg = <5>; 174 device_type = "ethernet-phy"; 175 }; 176 }; 177 178 enet0: ethernet@24000 { 179 cell-index = <0>; 180 device_type = "network"; 181 model = "eTSEC"; 182 compatible = "gianfar"; 183 reg = <0x24000 0x1000>; 184 local-mac-address = [ 00 00 00 00 00 00 ]; 185 interrupts = <29 2 30 2 34 2>; 186 interrupt-parent = <&mpic>; 187 phy-handle = <&phy2>; 188 }; 189 190 enet1: ethernet@25000 { 191 cell-index = <1>; 192 device_type = "network"; 193 model = "eTSEC"; 194 compatible = "gianfar"; 195 reg = <0x25000 0x1000>; 196 local-mac-address = [ 00 00 00 00 00 00 ]; 197 interrupts = <35 2 36 2 40 2>; 198 interrupt-parent = <&mpic>; 199 phy-handle = <&phy1>; 200 }; 201 202 enet2: ethernet@26000 { 203 cell-index = <2>; 204 device_type = "network"; 205 model = "eTSEC"; 206 compatible = "gianfar"; 207 reg = <0x26000 0x1000>; 208 local-mac-address = [ 00 00 00 00 00 00 ]; 209 interrupts = <31 2 32 2 33 2>; 210 interrupt-parent = <&mpic>; 211 phy-handle = <&phy3>; 212 }; 213 214 enet3: ethernet@27000 { 215 cell-index = <3>; 216 device_type = "network"; 217 model = "eTSEC"; 218 compatible = "gianfar"; 219 reg = <0x27000 0x1000>; 220 local-mac-address = [ 00 00 00 00 00 00 ]; 221 interrupts = <37 2 38 2 39 2>; 222 interrupt-parent = <&mpic>; 223 phy-handle = <&phy4>; 224 }; 225 226 serial0: serial@4500 { 227 cell-index = <0>; 228 device_type = "serial"; 229 compatible = "ns16550"; 230 reg = <0x4500 0x100>; // reg base, size 231 clock-frequency = <0>; // should we fill in in uboot? 232 current-speed = <115200>; 233 interrupts = <42 2>; 234 interrupt-parent = <&mpic>; 235 }; 236 237 serial1: serial@4600 { 238 cell-index = <1>; 239 device_type = "serial"; 240 compatible = "ns16550"; 241 reg = <0x4600 0x100>; // reg base, size 242 clock-frequency = <0>; // should we fill in in uboot? 243 current-speed = <115200>; 244 interrupts = <42 2>; 245 interrupt-parent = <&mpic>; 246 }; 247 248 global-utilities@e0000 { // global utilities reg 249 compatible = "fsl,mpc8548-guts"; 250 reg = <0xe0000 0x1000>; 251 fsl,has-rstcr; 252 }; 253 254 mpic: pic@40000 { 255 interrupt-controller; 256 #address-cells = <0>; 257 #interrupt-cells = <2>; 258 reg = <0x40000 0x40000>; 259 compatible = "chrp,open-pic"; 260 device_type = "open-pic"; 261 }; 262 }; 263 264 localbus@a0005000 { 265 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 266 "simple-bus"; 267 #address-cells = <2>; 268 #size-cells = <1>; 269 reg = <0xa0005000 0x100>; // BRx, ORx, etc. 270 271 ranges = < 272 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 273 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 274 2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527) 275 3 0x0 0xa3010000 0x00008000 // NAND FLASH 276 277 >; 278 279 flash@1,0 { 280 #address-cells = <1>; 281 #size-cells = <1>; 282 compatible = "cfi-flash"; 283 reg = <1 0x0 0x8000000>; 284 bank-width = <4>; 285 device-width = <1>; 286 287 partition@0 { 288 label = "kernel"; 289 reg = <0x00000000 0x00200000>; 290 }; 291 partition@200000 { 292 label = "root"; 293 reg = <0x00200000 0x00300000>; 294 }; 295 partition@500000 { 296 label = "user"; 297 reg = <0x00500000 0x07a00000>; 298 }; 299 partition@7f00000 { 300 label = "env1"; 301 reg = <0x07f00000 0x00040000>; 302 }; 303 partition@7f40000 { 304 label = "env2"; 305 reg = <0x07f40000 0x00040000>; 306 }; 307 partition@7f80000 { 308 label = "u-boot"; 309 reg = <0x07f80000 0x00080000>; 310 read-only; 311 }; 312 }; 313 314 /* Note: CAN support needs be enabled in U-Boot */ 315 can0@2,0 { 316 compatible = "intel,82527"; // Bosch CC770 317 reg = <2 0x0 0x100>; 318 interrupts = <4 0>; 319 interrupt-parent = <&mpic>; 320 }; 321 322 can1@2,100 { 323 compatible = "intel,82527"; // Bosch CC770 324 reg = <2 0x100 0x100>; 325 interrupts = <4 0>; 326 interrupt-parent = <&mpic>; 327 }; 328 329 /* Note: NAND support needs to be enabled in U-Boot */ 330 upm@3,0 { 331 #address-cells = <0>; 332 #size-cells = <0>; 333 compatible = "fsl,upm-nand"; 334 reg = <3 0x0 0x800>; 335 fsl,upm-addr-offset = <0x10>; 336 fsl,upm-cmd-offset = <0x08>; 337 chip-delay = <25>; // in micro-seconds 338 339 nand@0 { 340 #address-cells = <1>; 341 #size-cells = <1>; 342 343 partition@0 { 344 label = "fs"; 345 reg = <0x00000000 0x01000000>; 346 }; 347 }; 348 }; 349 }; 350 351 pci0: pci@a0008000 { 352 cell-index = <0>; 353 #interrupt-cells = <1>; 354 #size-cells = <2>; 355 #address-cells = <3>; 356 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 357 device_type = "pci"; 358 reg = <0xa0008000 0x1000>; 359 clock-frequency = <33333333>; 360 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 361 interrupt-map = < 362 /* IDSEL 28 */ 363 0xe000 0 0 1 &mpic 2 1 364 0xe000 0 0 2 &mpic 3 1>; 365 366 interrupt-parent = <&mpic>; 367 interrupts = <24 2>; 368 bus-range = <0 0>; 369 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 370 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>; 371 }; 372 373 pci1: pcie@a000a000 { 374 cell-index = <2>; 375 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 376 interrupt-map = < 377 /* IDSEL 0x0 (PEX) */ 378 0x00000 0 0 1 &mpic 0 1 379 0x00000 0 0 2 &mpic 1 1 380 0x00000 0 0 3 &mpic 2 1 381 0x00000 0 0 4 &mpic 3 1>; 382 383 interrupt-parent = <&mpic>; 384 interrupts = <26 2>; 385 bus-range = <0 0xff>; 386 ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000 387 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>; 388 clock-frequency = <33333333>; 389 #interrupt-cells = <1>; 390 #size-cells = <2>; 391 #address-cells = <3>; 392 reg = <0xa000a000 0x1000>; 393 compatible = "fsl,mpc8548-pcie"; 394 device_type = "pci"; 395 pcie@0 { 396 reg = <0 0 0 0 0>; 397 #size-cells = <2>; 398 #address-cells = <3>; 399 device_type = "pci"; 400 ranges = <0x02000000 0 0xb0000000 0x02000000 0 401 0xb0000000 0 0x10000000 402 0x01000000 0 0x00000000 0x01000000 0 403 0x00000000 0 0x08000000>; 404 }; 405 }; 406}; 407