1/* 2 * TQM 8540 Device Tree Source 3 * 4 * Copyright 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "tqc,tqm8540"; 16 compatible = "tqc,tqm8540"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 ethernet2 = &enet2; 24 serial0 = &serial0; 25 serial1 = &serial1; 26 pci0 = &pci0; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 PowerPC,8540@0 { 34 device_type = "cpu"; 35 reg = <0>; 36 d-cache-line-size = <32>; 37 i-cache-line-size = <32>; 38 d-cache-size = <32768>; 39 i-cache-size = <32768>; 40 timebase-frequency = <0>; 41 bus-frequency = <0>; 42 clock-frequency = <0>; 43 next-level-cache = <&L2>; 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x00000000 0x10000000>; 50 }; 51 52 soc@e0000000 { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 device_type = "soc"; 56 ranges = <0x0 0xe0000000 0x100000>; 57 reg = <0xe0000000 0x200>; 58 bus-frequency = <0>; 59 compatible = "fsl,mpc8540-immr", "simple-bus"; 60 61 memory-controller@2000 { 62 compatible = "fsl,8540-memory-controller"; 63 reg = <0x2000 0x1000>; 64 interrupt-parent = <&mpic>; 65 interrupts = <18 2>; 66 }; 67 68 L2: l2-cache-controller@20000 { 69 compatible = "fsl,8540-l2-cache-controller"; 70 reg = <0x20000 0x1000>; 71 cache-line-size = <32>; 72 cache-size = <0x40000>; // L2, 256K 73 interrupt-parent = <&mpic>; 74 interrupts = <16 2>; 75 }; 76 77 i2c@3000 { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 cell-index = <0>; 81 compatible = "fsl-i2c"; 82 reg = <0x3000 0x100>; 83 interrupts = <43 2>; 84 interrupt-parent = <&mpic>; 85 dfsrr; 86 87 rtc@68 { 88 compatible = "dallas,ds1337"; 89 reg = <0x68>; 90 }; 91 }; 92 93 dma@21300 { 94 #address-cells = <1>; 95 #size-cells = <1>; 96 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; 97 reg = <0x21300 0x4>; 98 ranges = <0x0 0x21100 0x200>; 99 cell-index = <0>; 100 dma-channel@0 { 101 compatible = "fsl,mpc8540-dma-channel", 102 "fsl,eloplus-dma-channel"; 103 reg = <0x0 0x80>; 104 cell-index = <0>; 105 interrupt-parent = <&mpic>; 106 interrupts = <20 2>; 107 }; 108 dma-channel@80 { 109 compatible = "fsl,mpc8540-dma-channel", 110 "fsl,eloplus-dma-channel"; 111 reg = <0x80 0x80>; 112 cell-index = <1>; 113 interrupt-parent = <&mpic>; 114 interrupts = <21 2>; 115 }; 116 dma-channel@100 { 117 compatible = "fsl,mpc8540-dma-channel", 118 "fsl,eloplus-dma-channel"; 119 reg = <0x100 0x80>; 120 cell-index = <2>; 121 interrupt-parent = <&mpic>; 122 interrupts = <22 2>; 123 }; 124 dma-channel@180 { 125 compatible = "fsl,mpc8540-dma-channel", 126 "fsl,eloplus-dma-channel"; 127 reg = <0x180 0x80>; 128 cell-index = <3>; 129 interrupt-parent = <&mpic>; 130 interrupts = <23 2>; 131 }; 132 }; 133 134 mdio@24520 { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 compatible = "fsl,gianfar-mdio"; 138 reg = <0x24520 0x20>; 139 140 phy1: ethernet-phy@1 { 141 interrupt-parent = <&mpic>; 142 interrupts = <8 1>; 143 reg = <1>; 144 device_type = "ethernet-phy"; 145 }; 146 phy2: ethernet-phy@2 { 147 interrupt-parent = <&mpic>; 148 interrupts = <8 1>; 149 reg = <2>; 150 device_type = "ethernet-phy"; 151 }; 152 phy3: ethernet-phy@3 { 153 interrupt-parent = <&mpic>; 154 interrupts = <8 1>; 155 reg = <3>; 156 device_type = "ethernet-phy"; 157 }; 158 }; 159 160 enet0: ethernet@24000 { 161 cell-index = <0>; 162 device_type = "network"; 163 model = "TSEC"; 164 compatible = "gianfar"; 165 reg = <0x24000 0x1000>; 166 local-mac-address = [ 00 00 00 00 00 00 ]; 167 interrupts = <29 2 30 2 34 2>; 168 interrupt-parent = <&mpic>; 169 phy-handle = <&phy2>; 170 }; 171 172 enet1: ethernet@25000 { 173 cell-index = <1>; 174 device_type = "network"; 175 model = "TSEC"; 176 compatible = "gianfar"; 177 reg = <0x25000 0x1000>; 178 local-mac-address = [ 00 00 00 00 00 00 ]; 179 interrupts = <35 2 36 2 40 2>; 180 interrupt-parent = <&mpic>; 181 phy-handle = <&phy1>; 182 }; 183 184 enet2: ethernet@26000 { 185 cell-index = <2>; 186 device_type = "network"; 187 model = "FEC"; 188 compatible = "gianfar"; 189 reg = <0x26000 0x1000>; 190 local-mac-address = [ 00 00 00 00 00 00 ]; 191 interrupts = <41 2>; 192 interrupt-parent = <&mpic>; 193 phy-handle = <&phy3>; 194 }; 195 196 serial0: serial@4500 { 197 cell-index = <0>; 198 device_type = "serial"; 199 compatible = "ns16550"; 200 reg = <0x4500 0x100>; // reg base, size 201 clock-frequency = <0>; // should we fill in in uboot? 202 interrupts = <42 2>; 203 interrupt-parent = <&mpic>; 204 }; 205 206 serial1: serial@4600 { 207 cell-index = <1>; 208 device_type = "serial"; 209 compatible = "ns16550"; 210 reg = <0x4600 0x100>; // reg base, size 211 clock-frequency = <0>; // should we fill in in uboot? 212 interrupts = <42 2>; 213 interrupt-parent = <&mpic>; 214 }; 215 216 mpic: pic@40000 { 217 interrupt-controller; 218 #address-cells = <0>; 219 #interrupt-cells = <2>; 220 reg = <0x40000 0x40000>; 221 device_type = "open-pic"; 222 compatible = "chrp,open-pic"; 223 }; 224 }; 225 226 pci0: pci@e0008000 { 227 cell-index = <0>; 228 #interrupt-cells = <1>; 229 #size-cells = <2>; 230 #address-cells = <3>; 231 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 232 device_type = "pci"; 233 reg = <0xe0008000 0x1000>; 234 clock-frequency = <66666666>; 235 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 236 interrupt-map = < 237 /* IDSEL 28 */ 238 0xe000 0 0 1 &mpic 2 1 239 0xe000 0 0 2 &mpic 3 1>; 240 241 interrupt-parent = <&mpic>; 242 interrupts = <24 2>; 243 bus-range = <0 0>; 244 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 245 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 246 }; 247}; 248